libboard_zynq: eth phy for Marvell 88E1518
* add support for LED control registers * support for registers on different pages
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43e0440911
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@ -82,6 +82,10 @@ impl PhyRegister for Control {
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fn addr() -> u8 {
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fn addr() -> u8 {
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0
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0
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}
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}
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fn page() -> u8 {
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0
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}
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}
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}
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impl From<u16> for Control {
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impl From<u16> for Control {
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@ -0,0 +1,64 @@
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use bit_field::BitField;
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use super::{PhyRegister, Link, LinkDuplex, LinkSpeed};
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#[derive(Copy, Clone, Debug, PartialEq)]
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pub enum LedControl {
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OnLinkOffNoLink = 0b0000,
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OnLinkBlinkActivityOffNoLink = 0b0001,
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OnFullDuplexBlinkCollisionOffHalfDuplex = 0b0010,
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OnActivityOffNoActivity = 0b0011,
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BlinkActivityOffNoActivity = 0b0100,
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OnTransmitOffNoTransmit = 0b0101,
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On101000LinkOffElse = 0b0110,
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On10LinkOffElse = 0b0111,
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ForceOff = 0b1000,
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ForceOn = 0b1001,
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ForceHiZ = 0b1010,
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ForceBlink = 0b1011,
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//LED[0] only
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Mode1 = 0b1100,
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Mode2 = 0b1101,
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Mode3 = 0b1110,
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Mode4 = 0b1111
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}
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#[derive(Clone, Copy, Debug)]
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/// LED Control Register
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pub struct Leds(pub u16);
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impl Leds {
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pub fn led(led_no: u8) -> LedControl {
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match self.0.get_bits((led_no*4)..=(led_no*4+3)) {
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0b0000 => LedControl::OnLinkOffNoLink,
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0b0001 => LedControl::OnLinkBlinkActivityOffNoLink,
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0b0010 => LedControl::OnFullDuplexBlinkCollisionOffHalfDuplex,
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0b0011 => LedControl::OnActivityOffNoActivity,
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0b0100 => LedControl::BlinkActivityOffNoActivity,
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0b0101 => LedControl::OnTransmitOffNoTransmit,
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0b0110 => LedControl::On101000LinkOffElse,
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0b0111 => LedControl::On10LinkOffElse,
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0b1000 => LedControl::ForceOff,
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0b1001 => LedControl::ForceOn,
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0b1010 => LedControl::ForceHiZ,
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0b1011 => LedControl::ForceBlink,
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0b1100 => LedControl::Mode1,
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0b1101 => LedControl::Mode2,
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0b1110 => LedControl::Mode3,
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0b1111 => LedControl::Mode4,
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}
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}
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pub fn set_led(led_no: u8, setting: LedControl) -> Self {
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self.0.set_bits((led_no*4)..=(led_no*4+3), setting as u8)
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}
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}
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impl PhyRegister for Leds {
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fn addr() -> u8 {
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0x10
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}
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fn page() -> u8 {
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3
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}
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}
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@ -33,6 +33,7 @@ pub trait PhyAccess {
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pub trait PhyRegister {
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pub trait PhyRegister {
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fn addr() -> u8;
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fn addr() -> u8;
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fn page() -> u8;
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}
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}
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@ -45,6 +46,8 @@ const OUI_MARVELL: u32 = 0x005043;
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const OUI_REALTEK: u32 = 0x000732;
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const OUI_REALTEK: u32 = 0x000732;
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const OUI_LANTIQ : u32 = 0x355969;
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const OUI_LANTIQ : u32 = 0x355969;
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const PAGE_REGISTER: u8 = 0x16;
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impl Phy {
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impl Phy {
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/// Probe all addresses on MDIO for a known PHY
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/// Probe all addresses on MDIO for a known PHY
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pub fn find<PA: PhyAccess>(pa: &mut PA) -> Option<Phy> {
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pub fn find<PA: PhyAccess>(pa: &mut PA) -> Option<Phy> {
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@ -84,6 +87,7 @@ impl Phy {
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PA: PhyAccess,
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PA: PhyAccess,
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PR: PhyRegister + From<u16>,
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PR: PhyRegister + From<u16>,
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{
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{
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pa.write_phy(self.addr, PAGE_REGISTER, PR::page());
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pa.read_phy(self.addr, PR::addr()).into()
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pa.read_phy(self.addr, PR::addr()).into()
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}
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}
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@ -93,6 +97,7 @@ impl Phy {
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PR: PhyRegister + From<u16> + Into<u16>,
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PR: PhyRegister + From<u16> + Into<u16>,
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F: FnMut(PR) -> PR,
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F: FnMut(PR) -> PR,
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{
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{
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pa.write_phy(self.addr, PAGE_REGISTER, PR::page());
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let reg = pa.read_phy(self.addr, PR::addr()).into();
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let reg = pa.read_phy(self.addr, PR::addr()).into();
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let reg = f(reg);
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let reg = f(reg);
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pa.write_phy(self.addr, PR::addr(), reg.into())
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pa.write_phy(self.addr, PR::addr(), reg.into())
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@ -43,6 +43,10 @@ impl PhyRegister for PSSR {
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fn addr() -> u8 {
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fn addr() -> u8 {
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0x11
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0x11
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}
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}
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fn page() -> u8 {
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0
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}
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}
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}
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impl From<u16> for PSSR {
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impl From<u16> for PSSR {
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@ -100,6 +100,10 @@ impl PhyRegister for Status {
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fn addr() -> u8 {
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fn addr() -> u8 {
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1
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1
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}
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}
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fn page() -> u8 {
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0
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}
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}
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}
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impl From<u16> for Status {
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impl From<u16> for Status {
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