regs: properly emit doc_comments
This commit is contained in:
parent
56c2f1d833
commit
6bf210366a
149
src/eth/regs.rs
149
src/eth/regs.rs
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@ -127,61 +127,87 @@ register!(net_ctrl, NetCtrl, RW, u32);
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register_bit!(net_ctrl, clear_stat_regs, 5);
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register!(net_cfg, NetCfg, RW, u32);
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/// false for 10Mbps, true for 100Mbps
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register_bit!(net_cfg, speed, 0);
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register_bit!(net_cfg,
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/// false for 10Mbps, true for 100Mbps
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speed, 0);
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register_bit!(net_cfg, full_duplex, 1);
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/// Discard non-VLAN frames
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register_bit!(net_cfg, disc_non_vlan, 2);
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/// Accept all valid frames?
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register_bit!(net_cfg, copy_all, 4);
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/// Don't accept broadcast destination address
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register_bit!(net_cfg, no_broadcast, 5);
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/// Multicast hash enable
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register_bit!(net_cfg, multi_hash_en, 6);
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/// Unicast hash enable
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register_bit!(net_cfg, uni_hash_en, 7);
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/// Accept frames up to 1536 bytes (instead of up to 1518 bytes)
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register_bit!(net_cfg, rx_1536_byte_frames, 8);
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/// External address match enable - when set the external address
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/// match interface can be used to copy frames to memory.
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register_bit!(net_cfg, ext_addr_match_en, 9);
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/// Gigabit mode enable
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register_bit!(net_cfg, gige_en, 10);
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/// Enable TBI instead of GMII/MII interface?
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register_bit!(net_cfg, pcs_sel, 11);
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/// Retry test (reduces backoff between collisions to one slot)
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register_bit!(net_cfg, retry_test, 12);
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/// Pause frame enable
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register_bit!(net_cfg, pause_en, 13);
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/// Receive buffer offset
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register_bits!(net_cfg, rx_buf_offset, u8, 14, 15);
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/// Length field error frame discard
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register_bit!(net_cfg, len_err_frame_disc, 16);
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/// Write received frames to memory with Frame Check Sequence removed
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register_bit!(net_cfg, fcs_remove, 17);
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/// MDC clock divison
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register_bits!(net_cfg, mdc_clk_div, u8, 18, 20);
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/// Data bus width
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register_bits!(net_cfg, dbus_width, u8, 21, 22);
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/// Disable copy of pause frames
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register_bit!(net_cfg, dis_cp_pause_frame, 23);
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/// Receive checksum offload enable
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register_bit!(net_cfg, rx_chksum_offld_en, 24);
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/// Enable frames to be received in half-duplex mode while
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/// transmitting
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register_bit!(net_cfg, rx_hd_while_tx, 25);
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/// Ignore Rx Framce Check Sequence (errors will not be rejected)
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register_bit!(net_cfg, ignore_rx_fcs, 26);
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/// SGMII mode enable
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register_bit!(net_cfg, sgmii_en, 27);
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/// IPG stretch enable
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register_bit!(net_cfg, ipg_stretch_en, 28);
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/// Receive bad preamble
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register_bit!(net_cfg, rx_bad_preamble, 29);
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/// Ignore IPG rx_er
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register_bit!(net_cfg, ignore_ipg_rx_er, 30);
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/// NA
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register_bit!(net_cfg, unidir_en, 31);
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register_bit!(net_cfg,
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/// Discard non-VLAN frames
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disc_non_vlan, 2);
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register_bit!(net_cfg,
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/// Accept all valid frames?
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copy_all, 4);
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register_bit!(net_cfg,
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/// Don't accept broadcast destination address
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no_broadcast, 5);
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register_bit!(net_cfg,
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/// Multicast hash enable
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multi_hash_en, 6);
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register_bit!(net_cfg,
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/// Unicast hash enable
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uni_hash_en, 7);
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register_bit!(net_cfg,
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/// Accept frames up to 1536 bytes (instead of up to 1518 bytes)
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rx_1536_byte_frames, 8);
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register_bit!(net_cfg,
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/// match interface can be used to copy frames to memory.
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/// External address match enable - when set the external address
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ext_addr_match_en, 9);
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register_bit!(net_cfg,
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/// Gigabit mode enable
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gige_en, 10);
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register_bit!(net_cfg,
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/// Enable TBI instead of GMII/MII interface?
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pcs_sel, 11);
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register_bit!(net_cfg,
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/// Retry test (reduces backoff between collisions to one slot)
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retry_test, 12);
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register_bit!(net_cfg,
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/// Pause frame enable
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pause_en, 13);
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register_bits!(net_cfg,
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/// Receive buffer offset
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rx_buf_offset, u8, 14, 15);
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register_bit!(net_cfg,
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/// Length field error frame discard
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len_err_frame_disc, 16);
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register_bit!(net_cfg,
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/// Write received frames to memory with Frame Check Sequence removed
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fcs_remove, 17);
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register_bits!(net_cfg,
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/// MDC clock divison
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mdc_clk_div, u8, 18, 20);
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register_bits!(net_cfg,
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/// Data bus width
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dbus_width, u8, 21, 22);
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register_bit!(net_cfg,
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/// Disable copy of pause frames
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dis_cp_pause_frame, 23);
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register_bit!(net_cfg,
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/// Receive checksum offload enable
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rx_chksum_offld_en, 24);
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register_bit!(net_cfg,
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/// Enable frames to be received in half-duplex mode while
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/// transmitting
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rx_hd_while_tx, 25);
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register_bit!(net_cfg,
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/// Ignore Rx Framce Check Sequence (errors will not be rejected)
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ignore_rx_fcs, 26);
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register_bit!(net_cfg,
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/// SGMII mode enable
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sgmii_en, 27);
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register_bit!(net_cfg,
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/// IPG stretch enable
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ipg_stretch_en, 28);
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register_bit!(net_cfg,
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/// Receive bad preamble
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rx_bad_preamble, 29);
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register_bit!(net_cfg,
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/// Ignore IPG rx_er
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ignore_ipg_rx_er, 30);
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register_bit!(net_cfg,
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/// NA
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unidir_en, 31);
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register!(net_status, NetStatus, RW, u32);
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register_bit!(net_status, pcs_link_state, 0);
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@ -250,14 +276,17 @@ pub enum PhyOperation {
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}
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register!(phy_maint, PhyMaint, RW, u32);
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/// Read from/write to the PHY
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register_bits!(phy_maint, data, u16, 0, 15);
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register_bits!(phy_maint,
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/// Read from/write to the PHY
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data, u16, 0, 15);
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// Write `0b10`
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register_bits!(phy_maint, must_10, u8, 16, 17);
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/// Register address
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register_bits!(phy_maint, reg_addr, u8, 18, 22);
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/// PHY address
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register_bits!(phy_maint, phy_addr, u8, 23, 27);
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register_bits!(phy_maint,
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/// Register address
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reg_addr, u8, 18, 22);
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register_bits!(phy_maint,
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/// PHY address
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phy_addr, u8, 23, 27);
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register_bits_typed!(phy_maint, operation, u8, PhyOperation, 28, 29);
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// PHY clause 22 compliant (not clause 45)?
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register_bit!(phy_maint, clause_22, 30);
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20
src/regs.rs
20
src/regs.rs
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@ -121,8 +121,10 @@ macro_rules! register {
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/// Define a 1-bit field of a register
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#[macro_export]
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macro_rules! register_bit {
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($mod_name: ident, $name: ident, $bit: expr) => (
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($mod_name: ident, $(#[$outer:meta])* $name: ident, $bit: expr) => (
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$(#[$outer])*
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impl $mod_name::Read {
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#[allow(unused)]
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pub fn $name(&self) -> bool {
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use bit_field::BitField;
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@ -130,7 +132,9 @@ macro_rules! register_bit {
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}
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}
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$(#[$outer])*
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impl $mod_name::Write {
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#[allow(unused)]
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pub fn $name(mut self, value: bool) -> Self {
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use bit_field::BitField;
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@ -144,8 +148,10 @@ macro_rules! register_bit {
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/// Define a multi-bit field of a register
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#[macro_export]
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macro_rules! register_bits {
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($mod_name: ident, $name: ident, $type: ty, $bit_begin: expr, $bit_end: expr) => (
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($mod_name: ident, $(#[$outer:meta])* $name: ident, $type: ty, $bit_begin: expr, $bit_end: expr) => (
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impl $mod_name::Read {
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#[allow(unused)]
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$(#[$outer])*
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pub fn $name(&self) -> $type {
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use bit_field::BitField;
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@ -153,7 +159,10 @@ macro_rules! register_bits {
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}
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}
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#[allow(unused)]
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$(#[$outer])*
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impl $mod_name::Write {
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#[allow(unused)]
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pub fn $name(mut self, value: $type) -> Self {
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use bit_field::BitField;
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@ -170,8 +179,10 @@ macro_rules! register_bits {
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/// definition must be annotated with `#[repr($bit_type)]`!
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#[macro_export]
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macro_rules! register_bits_typed {
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($mod_name: ident, $name: ident, $bit_type: ty, $type: ty, $bit_begin: expr, $bit_end: expr) => (
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($mod_name: ident, $(#[$outer:meta])* $name: ident, $bit_type: ty, $type: ty, $bit_begin: expr, $bit_end: expr) => (
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impl $mod_name::Read {
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#[allow(unused)]
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$(#[$outer])*
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pub fn $name(&self) -> $type {
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use bit_field::BitField;
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@ -181,6 +192,8 @@ macro_rules! register_bits_typed {
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}
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impl $mod_name::Write {
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#[allow(unused)]
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$(#[$outer])*
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pub fn $name(mut self, value: $type) -> Self {
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use bit_field::BitField;
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@ -196,6 +209,7 @@ macro_rules! register_bits_typed {
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macro_rules! register_at {
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($name: ident, $addr: expr, $ctor: ident) => (
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impl $name {
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#[allow(unused)]
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pub fn $ctor() -> &'static mut Self {
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let addr = $addr as *mut Self;
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unsafe { &mut *addr }
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@ -1,5 +1,3 @@
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#![allow(unused)]
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use core::fmt;
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use volatile_register::RW;
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@ -62,41 +62,56 @@ register_bit!(control, sttbrk, 7);
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register_bit!(control, stpbrk, 8);
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register!(mode, Mode, RW, u32);
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/// Channel mode: Defines the mode of operation of the UART.
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register_bits_typed!(mode, chmode, u8, ChannelMode, 8, 9);
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/// Number of stop bits
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register_bits_typed!(mode, nbstop, u8, StopBits, 6, 7);
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/// Parity type select
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register_bits_typed!(mode, par, u8, ParityMode, 3, 5);
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/// Character length select
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register_bits!(mode, chrl, u8, 1, 2);
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/// Clock source select
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register_bit!(mode, clks, 0);
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register_bits_typed!(mode,
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/// Channel mode: Defines the mode of operation of the UART.
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chmode, u8, ChannelMode, 8, 9);
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register_bits_typed!(mode,
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/// Number of stop bits
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nbstop, u8, StopBits, 6, 7);
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register_bits_typed!(mode,
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/// Parity type select
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par, u8, ParityMode, 3, 5);
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register_bits!(mode,
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/// Character length select
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chrl, u8, 1, 2);
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register_bit!(mode,
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/// Clock source select
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clks, 0);
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register!(baud_rate_gen, BaudRateGen, RW, u32);
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register_bits!(baud_rate_gen, cd, u16, 0, 15);
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register!(channel_sts, ChannelSts, RO, u32);
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/// Transmitter FIFO Nearly Full
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register_bit!(channel_sts, tnful, 14);
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/// Tx FIFO fill level is greater than or equal to TTRIG?
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register_bit!(channel_sts, ttrig, 13);
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/// Rx FIFO fill level is greater than or equal to FDEL?
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register_bit!(channel_sts, flowdel, 12);
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/// Transmitter state machine active?
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register_bit!(channel_sts, tactive, 11);
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/// Receiver state machine active?
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register_bit!(channel_sts, ractive, 10);
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/// Tx FIFO is full?
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register_bit!(channel_sts, txfull, 4);
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/// Tx FIFO is empty?
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register_bit!(channel_sts, txempty, 3);
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/// Rx FIFO is full?
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register_bit!(channel_sts, rxfull, 2);
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/// Rx FIFO is empty?
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register_bit!(channel_sts, rxempty, 1);
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/// Rx FIFO fill level is greater than or equal to RTRIG?
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register_bit!(channel_sts, rxovr, 0);
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register_bit!(channel_sts,
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/// Transmitter FIFO Nearly Full
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tnful, 14);
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register_bit!(channel_sts,
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/// Tx FIFO fill level is greater than or equal to TTRIG?
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ttrig, 13);
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register_bit!(channel_sts,
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/// Rx FIFO fill level is greater than or equal to FDEL?
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flowdel, 12);
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register_bit!(channel_sts,
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/// Transmitter state machine active?
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tactive, 11);
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register_bit!(channel_sts,
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/// Receiver state machine active?
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ractive, 10);
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register_bit!(channel_sts,
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/// Tx FIFO is full?
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txfull, 4);
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register_bit!(channel_sts,
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/// Tx FIFO is empty?
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txempty, 3);
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register_bit!(channel_sts,
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/// Rx FIFO is full?
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rxfull, 2);
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register_bit!(channel_sts,
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/// Rx FIFO is empty?
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rxempty, 1);
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register_bit!(channel_sts,
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/// Rx FIFO fill level is greater than or equal to RTRIG?
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rxovr, 0);
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register!(tx_rx_fifo, TxRxFifo, RW, u32);
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register_bits!(tx_rx_fifo, data, u32, 0, 31);
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