libcortex_a9: make functions public for use with r5
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@ -125,8 +125,8 @@ pub fn dcciall() {
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dsb();
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}
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const CACHE_LINE: usize = 0x20;
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const CACHE_LINE_MASK: usize = CACHE_LINE - 1;
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pub const CACHE_LINE: usize = 0x20;
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pub const CACHE_LINE_MASK: usize = CACHE_LINE - 1;
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#[inline]
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fn cache_line_addrs(first_addr: usize, beyond_addr: usize) -> impl Iterator<Item = usize> {
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@ -136,13 +136,13 @@ fn cache_line_addrs(first_addr: usize, beyond_addr: usize) -> impl Iterator<Item
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(first_addr..beyond_addr).step_by(CACHE_LINE)
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}
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fn object_cache_line_addrs<T>(object: &T) -> impl Iterator<Item = usize> {
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pub fn object_cache_line_addrs<T>(object: &T) -> impl Iterator<Item = usize> {
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let first_addr = object as *const _ as usize;
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let beyond_addr = (object as *const _ as usize) + core::mem::size_of_val(object);
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cache_line_addrs(first_addr, beyond_addr)
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}
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fn slice_cache_line_addrs<T>(slice: &[T]) -> impl Iterator<Item = usize> {
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pub fn slice_cache_line_addrs<T>(slice: &[T]) -> impl Iterator<Item = usize> {
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let first_addr = &slice[0] as *const _ as usize;
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let beyond_addr = (&slice[slice.len() - 1] as *const _ as usize) +
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core::mem::size_of_val(&slice[slice.len() - 1]);
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@ -3,6 +3,7 @@ use libregister::{
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RegisterR, RegisterW, RegisterRW,
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};
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#[macro_export]
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macro_rules! def_reg_r {
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($name:tt, $type: ty, $asm_instr:tt) => {
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impl RegisterR for $name {
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@ -18,6 +19,7 @@ macro_rules! def_reg_r {
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}
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}
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#[macro_export]
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macro_rules! def_reg_w {
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($name:ty, $type:ty, $asm_instr:tt) => {
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impl RegisterW for $name {
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@ -37,6 +39,7 @@ macro_rules! def_reg_w {
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}
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}
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#[macro_export]
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macro_rules! wrap_reg {
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($mod_name: ident) => {
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pub mod $mod_name {
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