libcortex_a9: allow access for full 1GB of DDR

libcortex_a9/src/mmu.rs

@@ -123,7 +123,7 @@ impl L1Table {
             bufferable: true,
         });
         /* (DDR cacheable) */
-        for ddr in 1..=0x1ff {
+        for ddr in 1..=0x3ff {
             self.direct_mapped_section(ddr, L1Section {
                 global: true,
                 shareable: true,
@@ -135,19 +135,6 @@ impl L1Table {
                 bufferable: false,
             });
         }
-        /* (unassigned/reserved). */
-        for undef in 0x1ff..=0x3ff {
-            self.direct_mapped_section(undef, L1Section {
-                global: false,
-                shareable: false,
-                access: AccessPermissions::PermissionFault,
-                tex: 0,
-                domain: 0,
-                exec: false,
-                cacheable: false,
-                bufferable: false,
-            });
-        }
         /* 0x40000000 - 0x7fffffff (FPGA slave0) */
         for fpga_slave in 0x400..=0x7ff {
             self.direct_mapped_section(fpga_slave, L1Section {