M-Labs/zynq-rs
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zynq::ddr: fix memtest progress calculation

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Astro 2019-10-27 20:38:35 +01:00
parent 85bd506132
commit 637bb35f43
1 changed files with 4 additions and 4 deletions
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8
src/zynq/ddr/mod.rs
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@ -202,7 +202,8 @@ impl DdrRam {
for (i, pattern) in patterns.iter().enumerate() { for (i, pattern) in patterns.iter().enumerate() {
println!("memtest phase {} (status: {:?})", i, self.status()); println!("memtest phase {} (status: {:?})", i, self.status());
let slice_len = slice.len(); // shift by 7 bits to be able to multiply with 100 (%)
let progress_max = (slice.len() >> 7) - 1;
let mut progress = 0; let mut progress = 0;
for (j, b) in slice.iter_mut().enumerate() { for (j, b) in slice.iter_mut().enumerate() {
expected.map(|expected| { expected.map(|expected| {
@ -212,9 +213,8 @@ impl DdrRam {
} }
}); });
*b = *pattern; *b = *pattern;
// println!("{:08X}", b as *mut u8 as usize); let new_progress = 100 * (j >> 7) / progress_max;
let new_progress = 100 * j / slice_len; if new_progress != progress {
if new_progress > progress {
progress = new_progress; progress = new_progress;
println!("{}%", progress); println!("{}%", progress);
} }