M-Labs/zynq-rs
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main: just test for qspi flash

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This commit is contained in:
Astro 2020-02-05 18:22:14 +01:00
parent b5b3cf69f7
commit 2f754de64b
3 changed files with 9 additions and 171 deletions
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172
experiments/src/main.rs
View File

@ -1,34 +1,16 @@
#![no_std] #![no_std]
#![no_main] #![no_main]
use core::mem::transmute;
use libcortex_a9::mutex::Mutex;
use libboard_zynq::{print, println, self as zynq, clocks::Clocks, clocks::source::{ClockSource, ArmPll, IoPll}}; use libboard_zynq::{print, println, self as zynq, clocks::Clocks, clocks::source::{ClockSource, ArmPll, IoPll}};
use libsupport_zynq::{ use libsupport_zynq as _;
ram, alloc::{vec, vec::Vec},
boot,
smoltcp::wire::{EthernetAddress, IpAddress, IpCidr},
smoltcp::iface::{NeighborCache, EthernetInterfaceBuilder},
smoltcp::time::Instant,
smoltcp::socket::SocketSet,
smoltcp::socket::{TcpSocket, TcpSocketBuffer},
};
const HWADDR: [u8; 6] = [0, 0x23, 0xde, 0xea, 0xbe, 0xef];
static mut STACK_CORE1: [u32; 512] = [0; 512];
#[no_mangle] #[no_mangle]
pub fn main_core0() { pub fn main_core0() {
// zynq::clocks::Clocks::enable_io(1_250_000_000);
println!("\nzc706 main"); println!("\nzc706 main");
let clocks = zynq::clocks::Clocks::get(); let clocks = zynq::clocks::Clocks::get();
println!("CPU Clocks: {}/{}/{}/{}", clocks.cpu_6x4x(), clocks.cpu_3x2x(), clocks.cpu_2x(), clocks.cpu_1x()); println!("CPU Clocks: {}/{}/{}/{}", clocks.cpu_6x4x(), clocks.cpu_3x2x(), clocks.cpu_2x(), clocks.cpu_1x());
{
use libregister::RegisterR;
println!("Boot mode: {:?}", zynq::slcr::RegisterBlock::new().boot_mode.read().boot_mode_pins());
}
// Clock setup
#[cfg(feature = "target_zc706")] #[cfg(feature = "target_zc706")]
const CPU_FREQ: u32 = 800_000_000; const CPU_FREQ: u32 = 800_000_000;
#[cfg(feature = "target_cora_z7_10")] #[cfg(feature = "target_cora_z7_10")]
@ -43,6 +25,7 @@ pub fn main_core0() {
let clocks = zynq::clocks::Clocks::get(); let clocks = zynq::clocks::Clocks::get();
println!("CPU Clocks: {}/{}/{}/{}", clocks.cpu_6x4x(), clocks.cpu_3x2x(), clocks.cpu_2x(), clocks.cpu_1x()); println!("CPU Clocks: {}/{}/{}/{}", clocks.cpu_6x4x(), clocks.cpu_3x2x(), clocks.cpu_2x(), clocks.cpu_1x());
// Flash: Linear Addressing Mode
let mut flash = zynq::flash::Flash::new(200_000_000).linear_addressing_mode(); let mut flash = zynq::flash::Flash::new(200_000_000).linear_addressing_mode();
let flash_ram: &[u8] = unsafe { core::slice::from_raw_parts(flash.ptr(), flash.size()) }; let flash_ram: &[u8] = unsafe { core::slice::from_raw_parts(flash.ptr(), flash.size()) };
for i in 0..=1 { for i in 0..=1 {
@ -54,26 +37,10 @@ pub fn main_core0() {
} }
let mut flash = flash.stop(); let mut flash = flash.stop();
for i in 0../*=*/1 { // Flash: Manual I/O Mode
for i in 0..=1 {
let mut flash_io = flash.manual_mode(i); let mut flash_io = flash.manual_mode(i);
let mut cr: zynq::flash::CR = flash_io.read_reg();
println!("rdcr={:02X}", cr.inner);
// if cr.quad() {
// println!("disabling quad mode...");
// cr.set_quad(false);
// let sr1: zynq::flash::SR1 = flash_io.read_reg();
// println!("sr1={:02X}", sr1.inner);
// flash_io.write_regs(sr1, cr);
// }
// if ! cr.quad() {
// println!("setting quad mode...");
// cr.set_quad(true);
// let sr1: zynq::flash::SR1 = flash_io.read_reg();
// // println!("sr1={:02X}", sr1.inner);
// flash_io.write_regs(sr1, cr);
// }
print!("Flash {} ID:", i); print!("Flash {} ID:", i);
for (i, b) in flash_io.rdid().enumerate() { for (i, b) in flash_io.rdid().enumerate() {
print!(" {:02X}", b); print!(" {:02X}", b);
@ -108,15 +75,13 @@ pub fn main_core0() {
for o in 0..8 { for o in 0..8 {
const SIZE: u32 = 0x100; const SIZE: u32 = 0x100;
println!("WREN");
flash_io.write_enabled(|flash_io| { flash_io.write_enabled(|flash_io| {
println!("Erase page {}", o); println!("Erase page {}", o);
flash_io.erase(o * SIZE); flash_io.erase(o * SIZE);
}); });
println!("WREN");
flash_io.write_enabled(|flash_io| { flash_io.write_enabled(|flash_io| {
println!("Program page {}", o); println!("Program page {}", o);
flash_io.program(o * SIZE, [0x26121984; (SIZE >> 2) as usize].iter().cloned()); flash_io.program(o * SIZE, [0x55FD02AA; (SIZE >> 2) as usize].iter().cloned());
}); });
} }
@ -131,134 +96,9 @@ pub fn main_core0() {
flash = flash_io.stop(); flash = flash_io.stop();
} }
let core1_stack = unsafe { &mut STACK_CORE1[..] };
println!("{} bytes stack for core1", core1_stack.len());
let core1 = boot::Core1::start(core1_stack);
for _ in 0..0x1000000 {
let mut l = SHARED.lock();
*l += 1;
}
while !*DONE.lock() {
let x = { *SHARED.lock() };
println!("shared: {:08X}", x);
}
let x = { *SHARED.lock() };
println!("done shared: {:08X}", x);
core1.reset();
libcortex_a9::asm::dsb();
print!("Core1 stack [{:08X}..{:08X}]:", &core1.stack[0] as *const _ as u32, &core1.stack[core1.stack.len() - 1] as *const _ as u32);
for w in core1.stack {
print!(" {:08X}", w);
}
println!(".");
let mut ddr = zynq::ddr::DdrRam::new();
// #[cfg(not(feature = "target_zc706"))]
ddr.memtest();
ram::init_alloc(&mut ddr);
let eth = zynq::eth::Eth::default(HWADDR.clone());
println!("Eth on");
const RX_LEN: usize = 8;
let mut rx_descs = (0..RX_LEN)
.map(|_| zynq::eth::rx::DescEntry::zeroed())
.collect::<Vec<_>>();
let mut rx_buffers = vec![[0u8; zynq::eth::MTU]; RX_LEN];
// Number of transmission buffers (minimum is two because with
// one, duplicate packet transmission occurs)
const TX_LEN: usize = 8;
let mut tx_descs = (0..TX_LEN)
.map(|_| zynq::eth::tx::DescEntry::zeroed())
.collect::<Vec<_>>();
let mut tx_buffers = vec![[0u8; zynq::eth::MTU]; TX_LEN];
let eth = eth.start_rx(&mut rx_descs, &mut rx_buffers);
//let mut eth = eth.start_tx(&mut tx_descs, &mut tx_buffers);
let mut eth = eth.start_tx(
// HACK
unsafe { transmute(tx_descs.as_mut_slice()) },
unsafe { transmute(tx_buffers.as_mut_slice()) },
);
let ethernet_addr = EthernetAddress(HWADDR);
// IP stack
let local_addr = IpAddress::v4(192, 168, 1, 51);
let mut ip_addrs = [IpCidr::new(local_addr, 24)];
let mut neighbor_storage = vec![None; 256];
let neighbor_cache = NeighborCache::new(&mut neighbor_storage[..]);
let mut iface = EthernetInterfaceBuilder::new(&mut eth)
.ethernet_addr(ethernet_addr)
.ip_addrs(&mut ip_addrs[..])
.neighbor_cache(neighbor_cache)
.finalize();
let mut sockets_storage = [
None, None, None, None,
None, None, None, None
];
let mut sockets = SocketSet::new(&mut sockets_storage[..]);
// taken from example code for smoltcp
let mut tcp_server_rx_data = vec![0; 512 * 1024];
let mut tcp_server_tx_data = vec![0; 512 * 1024];
let tcp_rx_buffer = TcpSocketBuffer::new(&mut tcp_server_rx_data[..]);
let tcp_tx_buffer = TcpSocketBuffer::new(&mut tcp_server_tx_data[..]);
let tcp_socket = TcpSocket::new(tcp_rx_buffer, tcp_tx_buffer);
let tcp_handle = sockets.add(tcp_socket);
/// `chargen`
const TCP_PORT: u16 = 19;
let mut time = 0u32;
loop {
time += 1;
let timestamp = Instant::from_millis(time);
match iface.poll(&mut sockets, timestamp) {
Ok(_) => {},
Err(e) => {
println!("poll error: {}", e);
}
}
// (mostly) taken from smoltcp example: TCP echo server
let mut socket = sockets.get::<TcpSocket>(tcp_handle);
if !socket.is_open() {
socket.listen(TCP_PORT).unwrap()
}
if socket.may_recv() && socket.can_send() {
socket.recv(|buf| {
let len = buf.len().min(4096);
let buffer = buf[..len].iter().cloned().collect::<Vec<_>>();
(len, buffer)
})
.and_then(|buffer| socket.send_slice(&buffer[..]))
.map(|_| {})
.unwrap_or_else(|e| println!("tcp: {:?}", e));
}
}
// #[allow(unreachable_code)]
// drop(tx_descs);
// #[allow(unreachable_code)]
// drop(tx_buffers);
} }
static SHARED: Mutex<u32> = Mutex::new(0);
static DONE: Mutex<bool> = Mutex::new(false);
#[no_mangle] #[no_mangle]
pub fn main_core1() { pub fn main_core1() {
println!("Hello from core1!");
for _ in 0..0x1000000 {
let mut l = SHARED.lock();
*l += 1;
}
println!("core1 done!");
*DONE.lock() = true;
loop {} loop {}
} }

2
libboard_zynq/src/flash/mod.rs
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@ -388,7 +388,7 @@ impl Flash<Manual> {
sr1.inner, sr1.inner,
cr.inner, cr.inner,
]; ];
flash.transfer(args.into_iter().cloned(), 3); flash.transfer(args.iter().cloned(), 3);
}); });
} }

6
libboard_zynq/src/flash/transfer.rs
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@ -1,7 +1,5 @@
use libregister::{RegisterR, RegisterW, RegisterRW}; use libregister::{RegisterR, RegisterRW};
use super::regs;
use super::{SpiWord, Flash, Manual}; use super::{SpiWord, Flash, Manual};
use crate::{print, println};
pub struct Transfer<'a, Args: Iterator<Item = W>, W: Into<SpiWord>> { pub struct Transfer<'a, Args: Iterator<Item = W>, W: Into<SpiWord>> {
flash: &'a mut Flash<Manual>, flash: &'a mut Flash<Manual>,
@ -114,7 +112,7 @@ impl<'a, Args: Iterator<Item = W>, W: Into<SpiWord>> Drop for Transfer<'a, Args,
.man_start_com(false) .man_start_com(false)
); );
/// Leave PCS high for a few cycles // Leave PCS high for a few cycles
for _ in 0..0x100 { for _ in 0..0x100 {
libcortex_a9::asm::nop(); libcortex_a9::asm::nop();
} }