M-Labs
/
zynq-rs
11
0
Fork 15
Code Issues 6 Pull Requests 1 Releases Wiki Activity

zynq::slcr: fix a bitfield index 

that didn't solve our problems.
This commit is contained in:
Astro 2019-11-03 02:01:42 +01:00
parent 6bee1f44f4
commit 04e816d99e
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/zynq/slcr.rs
View File

@ -376,7 +376,7 @@ register_bits!(gem_clk_ctrl,
divisor, u8, 8, 13); divisor, u8, 8, 13);
register_bits_typed!(gem_clk_ctrl, register_bits_typed!(gem_clk_ctrl,
/// Source to generate the ref clock /// Source to generate the ref clock
srcsel, u8, PllSource, 4, 5); srcsel, u8, PllSource, 4, 6);
register_bit!(gem_clk_ctrl, register_bit!(gem_clk_ctrl,
/// SMC reference clock control /// SMC reference clock control
clkact, 0); clkact, 0);