libboard_zynq: flush Uart by waiting for tx idle

libboard_zynq/src/logger.rs

@@ -29,6 +29,6 @@ impl log::Log for Logger {
     }
     fn flush(&self) {
         let uart = stdio::get_uart();
-        while !uart.tx_fifo_empty() {}
+        while !uart.tx_idle() {}
     }
 }

libboard_zynq/src/stdio.rs

@@ -63,6 +63,7 @@ macro_rules! println {
         let mut uart = $crate::stdio::get_uart();
         let _ = write!(uart, $($arg)*);
         let _ = write!(uart, "\n");
-        while !uart.tx_fifo_empty() {}
+        // flush after the newline
+        while !uart.tx_idle() {}
     })
 }

libboard_zynq/src/uart/mod.rs

@@ -192,15 +192,14 @@ impl Uart {
         self.regs.channel_sts.read().txfull()
     }
 
-    pub fn tx_fifo_empty(&self) -> bool {
-        self.regs.channel_sts.read().txempty()
+    pub fn tx_idle(&self) -> bool {
+        let status = self.regs.channel_sts.read();
+        status.txempty() && !status.tactive()
     }
 }
 
 impl fmt::Write for Uart {
     fn write_str(&mut self, s: &str) -> Result<(), fmt::Error> {
-        while !self.tx_fifo_empty() {}
-
         for b in s.bytes() {
             self.write_byte(b);
         }
@@ -222,7 +221,7 @@ impl embedded_hal::serial::Write<u8> for Uart {
     }
 
     fn flush(&mut self) -> nb::Result<(), Void> {
-        if self.tx_fifo_empty() {
+        if self.tx_idle() {
             Ok(())
         } else {
             Err(nb::Error::WouldBlock)