add dcxo frequency change settling time

wrapper: add default settling value
sim: gate frequency change behind settling time
example: update adpll_period to 200μs to account for settling delay
example: update docs for adpll_period minimum value
docs: remove the settling time limitation

README.md

@@ -54,5 +54,4 @@ nix develop
 </details><br>
 
 ## Limitation
-1. The simulation is missing the switching delay of "receiving ADPLL -> DCXO output starting to change"
+1. The white noise is used to simulate jitter which may result in higher phase noise
-2. The white noise is used to simulate jitter which may result in higher phase noise

src/both_PLL_example.ipynb

@@ -52,7 +52,7 @@
     "timestep = 1e-10\n",
     "total_steps = 200_000_000\n",
     "sim_mode = \"both\"\n",
-    "adpll_period = 100e-6     # in seconds, the period that pll will trigger, (minimum > the sampling rate of collector)\n",
+    "adpll_period = 200e-6     # in seconds, the period that pll will trigger, (minimum > total DCXO frequency change delay)\n",
     "start_up_delay = 100e-6   # in seconds, the frequency adjustment is DISABLE until time > start_up_delay\n",
     "\n",
     "gtx_freq = 125_001_519\n",

src/helper_PLL_example.ipynb

@@ -52,7 +52,7 @@
     "timestep = 1e-10\n",
     "total_steps = 100_000_000\n",
     "sim_mode = \"helper_pll\"\n",
-    "adpll_period = 100e-6     # in seconds, the period that pll will trigger, (minimum > the sampling rate of collector)\n",
+    "adpll_period = 200e-6     # in seconds, the period that pll will trigger, (minimum > total DCXO frequency change delay)\n",
     "start_up_delay = 100e-6   # in seconds, the frequency adjustment is DISABLE until time > start_up_delay\n",
     "\n",
     "gtx_freq = 125_001_519\n",

src/main_PLL_example.ipynb

@@ -55,7 +55,7 @@
     "timestep = 1e-10\n",
     "total_steps = 100_000_000\n",
     "sim_mode = \"main_pll\"\n",
-    "adpll_period = 100e-6     # in seconds, the period that pll will trigger, (minimum > the sampling rate of collector)\n",
+    "adpll_period = 200e-6     # in seconds, the period that pll will trigger, (minimum > total DCXO frequency change delay)\n",
     "start_up_delay = 100e-6   # in seconds, the frequency adjustment is DISABLE until time > start_up_delay\n",
     "\n",
     "gtx_freq = 125_001_519\n",

src/wrpll_simulation/sim.py

@@ -23,6 +23,7 @@ def simulation_jit(
     N,
     adpll_write_period,
     i2c_comm_delay,
+    dcxo_settling_delay,
     blind_period,
     start_up_delay,
     helper_init_freq=0
@@ -203,11 +204,11 @@ def simulation_jit(
 
             # i2c communication delay
 
-            if h_i2c_active and i >= i2c_comm_delay + h_i2c_active_index:
+            if h_i2c_active and i >= i2c_comm_delay + dcxo_settling_delay + h_i2c_active_index:
                 helper_freq = dcxo_freq * (1 + h_adpll * 0.0001164 / 1_000_000) * ((N-1) / N)
                 h_i2c_active = False
 
-            if m_i2c_active and i >= i2c_comm_delay + m_i2c_active_index:
+            if m_i2c_active and i >= i2c_comm_delay + dcxo_settling_delay + m_i2c_active_index:
                 main_freq = dcxo_freq * (1 + m_adpll * 0.0001164 / 1_000_000)
                 m_i2c_active = False
 

src/wrpll_simulation/wrpll.py

@@ -16,6 +16,7 @@ class WRPLL_simulator():
         adpll_write_period,
         start_up_delay,
         i2c_comm_delay=85.6e-6,
+        dcxo_settling_delay=100e-6,
         gtx_jitter=370e-15,
         dcxo_freq=125_000_000,
         dcxo_jitter=95e-15,
@@ -52,6 +53,7 @@ class WRPLL_simulator():
 
         # sim config
         self.i2c_comm_delay = int(i2c_comm_delay/timestep)
+        self.dcxo_settling_delay = int(dcxo_settling_delay/timestep)
         self.blind_period = blind_period
         self.adpll_write_period = int(adpll_write_period/timestep)
         self.start_up_delay = int(start_up_delay/timestep)
@@ -92,6 +94,7 @@ class WRPLL_simulator():
             self.N,
             self.adpll_write_period,
             self.i2c_comm_delay,
+            self.dcxo_settling_delay,
             self.blind_period,
             self.start_up_delay,
             self.helper_init_freq