From 734e87eede707e516464a10205c721e5cf250c1f Mon Sep 17 00:00:00 2001 From: morgan Date: Wed, 13 Dec 2023 15:53:11 +0800 Subject: [PATCH] =?UTF-8?q?add=20dcxo=20frequency=20change=20settling=20ti?= =?UTF-8?q?me=20wrapper:=20add=20default=20settling=20value=20sim:=20gate?= =?UTF-8?q?=20frequency=20change=20behind=20settling=20time=20example:=20u?= =?UTF-8?q?pdate=20adpll=5Fperiod=20to=20200=CE=BCs=20to=20account=20for?= =?UTF-8?q?=20settling=20delay=20example:=20update=20docs=20for=20adpll=5F?= =?UTF-8?q?period=20minimum=20value=20docs:=20remove=20the=20settling=20ti?= =?UTF-8?q?me=20limitation?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- README.md | 3 +-- src/both_PLL_example.ipynb | 2 +- src/helper_PLL_example.ipynb | 2 +- src/main_PLL_example.ipynb | 2 +- src/wrpll_simulation/sim.py | 5 +++-- src/wrpll_simulation/wrpll.py | 3 +++ 6 files changed, 10 insertions(+), 7 deletions(-) diff --git a/README.md b/README.md index 352b874..3384bf0 100644 --- a/README.md +++ b/README.md @@ -54,5 +54,4 @@ nix develop
## Limitation -1. The simulation is missing the switching delay of "receiving ADPLL -> DCXO output starting to change" -2. The white noise is used to simulate jitter which may result in higher phase noise +1. The white noise is used to simulate jitter which may result in higher phase noise diff --git a/src/both_PLL_example.ipynb b/src/both_PLL_example.ipynb index 31835a5..be3051d 100644 --- a/src/both_PLL_example.ipynb +++ b/src/both_PLL_example.ipynb @@ -52,7 +52,7 @@ "timestep = 1e-10\n", "total_steps = 200_000_000\n", "sim_mode = \"both\"\n", - "adpll_period = 100e-6 # in seconds, the period that pll will trigger, (minimum > the sampling rate of collector)\n", + "adpll_period = 200e-6 # in seconds, the period that pll will trigger, (minimum > total DCXO frequency change delay)\n", "start_up_delay = 100e-6 # in seconds, the frequency adjustment is DISABLE until time > start_up_delay\n", "\n", "gtx_freq = 125_001_519\n", diff --git a/src/helper_PLL_example.ipynb b/src/helper_PLL_example.ipynb index e34ca68..3a4486f 100644 --- a/src/helper_PLL_example.ipynb +++ b/src/helper_PLL_example.ipynb @@ -52,7 +52,7 @@ "timestep = 1e-10\n", "total_steps = 100_000_000\n", "sim_mode = \"helper_pll\"\n", - "adpll_period = 100e-6 # in seconds, the period that pll will trigger, (minimum > the sampling rate of collector)\n", + "adpll_period = 200e-6 # in seconds, the period that pll will trigger, (minimum > total DCXO frequency change delay)\n", "start_up_delay = 100e-6 # in seconds, the frequency adjustment is DISABLE until time > start_up_delay\n", "\n", "gtx_freq = 125_001_519\n", diff --git a/src/main_PLL_example.ipynb b/src/main_PLL_example.ipynb index 3b74ece..262ffa0 100644 --- a/src/main_PLL_example.ipynb +++ b/src/main_PLL_example.ipynb @@ -55,7 +55,7 @@ "timestep = 1e-10\n", "total_steps = 100_000_000\n", "sim_mode = \"main_pll\"\n", - "adpll_period = 100e-6 # in seconds, the period that pll will trigger, (minimum > the sampling rate of collector)\n", + "adpll_period = 200e-6 # in seconds, the period that pll will trigger, (minimum > total DCXO frequency change delay)\n", "start_up_delay = 100e-6 # in seconds, the frequency adjustment is DISABLE until time > start_up_delay\n", "\n", "gtx_freq = 125_001_519\n", diff --git a/src/wrpll_simulation/sim.py b/src/wrpll_simulation/sim.py index e81cdfc..03c012e 100644 --- a/src/wrpll_simulation/sim.py +++ b/src/wrpll_simulation/sim.py @@ -23,6 +23,7 @@ def simulation_jit( N, adpll_write_period, i2c_comm_delay, + dcxo_settling_delay, blind_period, start_up_delay, helper_init_freq=0 @@ -203,11 +204,11 @@ def simulation_jit( # i2c communication delay - if h_i2c_active and i >= i2c_comm_delay + h_i2c_active_index: + if h_i2c_active and i >= i2c_comm_delay + dcxo_settling_delay + h_i2c_active_index: helper_freq = dcxo_freq * (1 + h_adpll * 0.0001164 / 1_000_000) * ((N-1) / N) h_i2c_active = False - if m_i2c_active and i >= i2c_comm_delay + m_i2c_active_index: + if m_i2c_active and i >= i2c_comm_delay + dcxo_settling_delay + m_i2c_active_index: main_freq = dcxo_freq * (1 + m_adpll * 0.0001164 / 1_000_000) m_i2c_active = False diff --git a/src/wrpll_simulation/wrpll.py b/src/wrpll_simulation/wrpll.py index d2b5abd..a0f92c0 100644 --- a/src/wrpll_simulation/wrpll.py +++ b/src/wrpll_simulation/wrpll.py @@ -16,6 +16,7 @@ class WRPLL_simulator(): adpll_write_period, start_up_delay, i2c_comm_delay=85.6e-6, + dcxo_settling_delay=100e-6, gtx_jitter=370e-15, dcxo_freq=125_000_000, dcxo_jitter=95e-15, @@ -52,6 +53,7 @@ class WRPLL_simulator(): # sim config self.i2c_comm_delay = int(i2c_comm_delay/timestep) + self.dcxo_settling_delay = int(dcxo_settling_delay/timestep) self.blind_period = blind_period self.adpll_write_period = int(adpll_write_period/timestep) self.start_up_delay = int(start_up_delay/timestep) @@ -92,6 +94,7 @@ class WRPLL_simulator(): self.N, self.adpll_write_period, self.i2c_comm_delay, + self.dcxo_settling_delay, self.blind_period, self.start_up_delay, self.helper_init_freq