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morgan 734e87eede add dcxo frequency change settling time 
wrapper: add default settling value
sim: gate frequency change behind settling time
example: update adpll_period to 200μs to account for settling delay
example: update docs for adpll_period minimum value
docs: remove the settling time limitation
 		2023-12-13 15:53:11 +08:00
src add dcxo frequency change settling time 2023-12-13 15:53:11 +08:00
.gitignore git: ignore __pycache__ 2023-12-13 15:46:04 +08:00
README.md add dcxo frequency change settling time 2023-12-13 15:53:11 +08:00
flake.lock toolchain: migrate from requirements.txt to poetry 2023-12-13 15:46:04 +08:00
flake.nix toolchain: migrate from requirements.txt to poetry 2023-12-13 15:46:04 +08:00
poetry.lock toolchain: migrate from requirements.txt to poetry 2023-12-13 15:46:04 +08:00
pyproject.toml toolchain: migrate from requirements.txt to poetry 2023-12-13 15:46:04 +08:00

README.md

WRPLL simulation

A time domain simulation for WRPLL

Installation

Poetry:

poetry install
poetry run jupyter lab

Poetry shell:

poetry install
poetry shell

Nix:

nix develop

Quick start

  • Three notebook examples are included

    1. helper_PLL_example.ipynb : helper PLL only
    2. main_PLL_example.ipynb : main PLL only with a user specific helper frequency
    3. both_PLL_example.ipynb : main and helper PLL

  • RAM usage and execution time estimate for simulation ONLY

    1. 100,000,000 time steps: 6GiB RAM and 12 seconds

    2. 200,000,000 time steps: 11GiB RAM and 20 seconds

    3. 300,000,000 time steps: 16GiB RAM and 35 seconds


WRPLL formulas

  • Assume the difference between f_{main}, f_{gtx} is very small

    • Let f_{in} = f_{main} = f_{gtx}

    • f_{helper} = f_{in} * \dfrac{N-1}{N}

    • f_{beat} = f_{in} - f_{helper} = \dfrac{f_{in}}{N}

  • Main and helper Si549 DCXO ADPLL setting

    • ADPLL = \dfrac{\Delta f_{outppm}}{0.0001164}

Limitation

  1. The white noise is used to simulate jitter which may result in higher phase noise