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  • 061579f97e Call external functions when inline-asm is not set Vadim Kaushan 2018-12-23 09:44:08 +0100
  • 41378757c0 Do not require const-fn and asm features Vadim Kaushan 2018-12-22 10:32:52 +0100
  • 3652547073 Simplify #[cfg()] predicate expressions Vadim Kaushan 2018-12-22 09:10:20 +0100
  • 86ac78b4aa Merge #15 bors[bot] 2019-01-22 21:58:06 +0000
  • 52ad774fc1 Remove useless cfg_attr Vadim Kaushan 2018-12-21 23:01:25 +0100
  • 921aa2bbec Refactoring: use new macros for M-mode CSRs Vadim Kaushan 2018-12-21 22:49:23 +0100
  • 8bffbd7291 Merge #12 #14 bors[bot] 2018-12-18 22:25:29 +0000
  • ca737e7a48 Merge #13 bors[bot] 2018-12-18 22:22:42 +0000
  • b790a0e92a Replace no-op with unimplemented!() Vadim Kaushan 2018-12-19 00:01:36 +0300
  • 9550fe0687 Remove ecall and *ret instructions from riscv::asm Vadim Kaushan 2018-12-18 23:58:50 +0300
  • 8776d30d3b add S-Mode registers WangRunji 2018-11-09 22:42:46 +0800
  • 9dc7b40fdd impl sfence_vma & sfence_vma_all WangRunji 2018-11-09 22:27:19 +0800
  • 4e16dd85ed Merge #10 bors[bot] 2018-08-19 17:02:05 +0000
  • 591b7df808 Merge #9 bors[bot] 2018-08-19 11:12:24 +0000
  • 489b88f66b Merge #8 bors[bot] 2018-08-19 08:49:02 +0000
  • 8e0faa9182 these raw instructions are unsafe M Farkas-Dyck 2018-08-18 10:22:05 -0800
  • 5a88960ee0 use `NonZeroUsize` where appropriate M Farkas-Dyck 2018-08-18 10:15:10 -0800
  • ecc69bda00 mepc is word-size M Farkas-Dyck 2018-08-18 10:10:01 -0800
  • 8d530616c9
         Build master branch too. David Craven 2018-08-12 09:11:27 +0200
  • be2a15f34e Bump version and update url. David Craven 2018-08-12 07:50:11 +0200
  • b03aae8850 Update README. David Craven 2018-08-12 08:17:21 +0200
  • 5e55720ad8 Update bare-metal. David Craven 2018-08-12 07:57:55 +0200
  • 34b2ba33cd Add inline-asm feature. David Craven 2018-08-12 07:56:17 +0200
  • 59d46795b2 A unified contributing experience. David Craven 2018-08-11 17:58:32 +0200
  • 6769ac9262 fix target_arch conditionals to match "riscv32" and "riscv64" Dan Callaghan 2018-08-05 12:37:47 +1000
  • 87bcdd8bab
         Bump version. David Craven 2018-04-25 19:42:30 +0200
  • 8597f1c32d Fix typo in register/misa.rs Jakob Weisblat 2018-04-01 19:07:32 -0400
  • 45364b26a8
         Add mepc register. David Craven 2018-03-30 12:14:27 +0200
  • cd5200c5fa
         Fix mstatus register value. David Craven 2018-03-29 15:37:49 +0200
  • 7db0e71060
         New api. David Craven 2018-03-27 20:17:44 +0200
  • 179df42984
         Remove inline(always). David Craven 2018-03-24 19:27:00 +0100
  • 21bfaf49ae
         mcause is read-only. David Craven 2017-11-21 09:52:15 +0100
  • 0d9d6cf334
         Bump version to 0.1.4 David Craven 2017-11-20 14:23:53 +0100
  • bb41b209a6
         Read bits only once. David Craven 2017-11-20 14:14:01 +0100
  • b42411e64a
         Bump version to 0.1.3 David Craven 2017-11-18 14:10:40 +0100
  • 1b98011118
         Killing me softly. David Craven 2017-11-18 14:09:53 +0100
  • fd78d9bffc
         Bump version to 0.1.2 David Craven 2017-11-18 14:05:00 +0100
  • 94c3b5561e
         Update bare-metal to 0.1.1. David Craven 2017-11-18 14:04:19 +0100
  • 6ebb6f9790
         Bump version to 0.1.1 David Craven 2017-11-18 09:45:01 +0100
  • 467327cb15
         Allow compiling on x86_64 for publishing. David Craven 2017-11-18 08:46:19 +0100
  • e864581828
         Initial commit. David Craven 2017-09-19 16:04:12 +0200