5846f57ab1
cargo: bump version to 0.0.2
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This version adds vexriscv-specific registers.
Signed-off-by: Sean Cross <sean@xobs.io>
2020-01-08 17:23:05 +08:00
fd54453416
register: add vexriscv-specific registers
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Vexriscv in its normal configuration has its own registers for things
such as machine interrupts and system interrupts. Add wrappers for
these registers.
Signed-off-by: Sean Cross <sean@xobs.io>
2020-01-08 17:22:16 +08:00
8bc0b06f95
bin: update name of object file
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This minor update simply changes the name of the object file within the
library. It should have no user-facing changes.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-12-28 18:29:06 +08:00
5121f28fde
cargo: remove `vexriscv` category
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Apparently categories are fixed, and vexriscv isn't a category.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-12-28 18:14:52 +08:00
28ded4136a
vexriscv: clone from riscv crate
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Base the vexriscv crate on the riscv crate, but add vexriscv-specific
instructions.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-12-28 18:12:31 +08:00
0259333c75
Merge #34
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34: mip, satp: Allow writing to these privileged registers r=laanwj a=archshift
Per the RISC-V privileged ISA, these registers should be writable.
Co-authored-by: Gui Andrade <gh@archshift.com>
2019-10-10 07:32:26 +00:00
7a9aa062a0
Allow writing directly to satp register
2019-10-08 18:10:38 -07:00
95c52341c4
mip: Add set/clear functions for bits
2019-10-08 17:57:29 -07:00
0eda3c511c
Merge #32
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32: add user trap setup and handling registers r=almindor a=almindor
Adds CSR handlers for user trap setup and handling registers.
Also unifies common shared types.
NOTE: untested, will test on real device ASAP
Co-authored-by: Ales Katona <almindor@gmail.com>
2019-09-13 21:15:02 +00:00
73f45e3dbf
Merge branch 'master' into ustatus
2019-09-13 11:21:44 -06:00
9d68612325
Merge #33
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33: Do not use bare-metal v0.2.5 r=almindor a=Disasm
Co-authored-by: Vadim Kaushan <admin@disasm.info>
2019-09-13 01:06:16 +00:00
b834ae45a5
Do not use bare-metal v0.2.5 (changes MSRV)
2019-09-05 19:53:02 +03:00
8840aee369
ucause only as readable bits
2019-08-31 17:32:43 -06:00
e1232ed680
clean up formatting
2019-08-31 16:12:39 -06:00
cdf6a33665
remove XS and FS from ustatus
2019-08-31 16:10:56 -06:00
13831f7a80
revert scause specific trap/exceptions
2019-08-31 16:09:47 -06:00
f443bcf698
remove invalid comment
2019-08-28 09:26:02 -06:00
30555e4d79
fix typos in asm calls
2019-08-27 09:47:57 -06:00
49446ad869
fix ustatus doc typos
2019-08-27 09:46:14 -06:00
2180ef44d5
add user trap setup and handling registers
2019-08-27 09:40:47 -06:00
4094a32f43
Merge #30
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30: add riscv32i target r=Disasm a=sbourdeauducq
This adds support for the simplest RISC-V processor possible, which is useful e.g. for experimenting with FPGA softcore implementations.
Co-authored-by: Sebastien Bourdeauducq <sb@m-labs.hk>
2019-07-27 12:59:37 +00:00
Sebastien Bourdeauducq
b53e0a5cd2
add riscv32i target
2019-07-26 00:13:38 +08:00
7f1e4a56cf
Merge #31
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31: Add more CSRs r=laanwj a=Disasm
Co-authored-by: Vadim Kaushan <admin@disasm.info>
2019-07-23 17:41:40 +00:00
d3dc245ce4
Bump version (0.5.4)
2019-07-03 01:37:34 +03:00
31f4127702
Add PMP CSRs
2019-06-26 11:25:45 +03:00
f37ab221c8
Implement hpmcounter*[h], mhpmcounter*[h], mhpmevent* CSRs
2019-06-26 00:51:37 +03:00
298a8b6f6e
Provide write() for mepc
2019-06-25 23:48:47 +03:00
7a8d3d1f6c
Implement mscratch and mtval registers
2019-06-25 23:48:27 +03:00
00367d4fd2
Add sections to the registers module
2019-06-25 23:34:47 +03:00
370a654d2c
Regenerate binaries
2019-06-25 23:34:20 +03:00
a659a0cc39
Declare all the CSR registers in asm.S
2019-06-25 23:33:40 +03:00
ac2ac6756b
Derive useful traits for enums
2019-06-25 23:32:51 +03:00
5a1ab837b4
Merge #28
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28: Add marchid, mhartid and mimpid registers r=laanwj a=Disasm
Co-authored-by: Vadim Kaushan <admin@disasm.info>
2019-06-25 19:40:12 +00:00
2965734b7b
Bump version (0.5.3)
2019-04-29 10:45:19 +02:00
2ef11206bd
Regenerate binaries
2019-04-29 10:44:45 +02:00
cf9008492a
Add marchid, mhartid and mimpid registers
2019-04-29 10:43:51 +02:00
1e514648fd
Merge #26
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26: Fix Misa::has_extension() r=dvc94ch a=Disasm
Co-authored-by: Vadim Kaushan <admin@disasm.info>
2019-04-01 19:06:47 +00:00
c3ff23989e
Bump version (0.5.2)
2019-04-01 19:59:10 +03:00
ca797a35d8
Fix Misa::has_extension()
2019-04-01 19:58:40 +03:00
33070435a0
Merge #25
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25: Rename RISCV to RISC-V in documentation r=Disasm a=medusacle
More common name for the CPU architecture 😄 Also update the copyright year.
Probably, if this is merged, you'd want to update the project description as well.
Co-authored-by: mara <vmedea@protonmail.com>
2019-03-28 21:20:43 +00:00
6425cab701
Merge #24
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24: Add FS and XS fields, fix incorrect field setting, bump version r=dvc94ch a=Disasm
Co-authored-by: Vadim Kaushan <admin@disasm.info>
2019-03-28 20:47:36 +00:00
c1a3fe2dd9
Rename RISCV to RISC-V
2019-03-28 18:31:57 +01:00
6bfccad567
Bump version (0.5.1)
2019-03-28 19:06:40 +03:00
7112ef8af2
Regenerate blobs
2019-03-28 18:57:28 +03:00
5baba0cb32
Add write function for sstatus register
2019-03-28 18:56:49 +03:00
9bb3b5803c
Refactoring: use set_bits() in set_fs function
2019-03-28 17:59:07 +03:00
5ef90e3189
Fix set_spp and set_mpp functions
2019-03-28 17:57:40 +03:00
6a2bdbf38d
Refactoring
2019-03-18 18:25:16 +03:00
4fb81f4860
Add FS and XS fields of mstatus
2019-03-18 18:14:00 +03:00
32eba6c1ea
Merge #23
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23: Add fcsr register r=dvc94ch a=Disasm
Co-authored-by: Vadim Kaushan <admin@disasm.info>
2019-03-17 18:47:24 +00:00
Sean Cross
bors[bot]
Gui Andrade
Ales Katona
Vadim Kaushan
Sebastien Bourdeauducq
bors[bot]
mara