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132 Commits

Author SHA1 Message Date
Vadim Kaushan 9550fe0687 Remove ecall and *ret instructions from riscv::asm 2018-12-18 23:58:50 +03:00
WangRunji 8776d30d3b add S-Mode registers 
- use macros to simplify CSR ops
- use crate 'bit_field' to make bits operation clear
 2018-11-09 22:42:46 +08:00
WangRunji 9dc7b40fdd impl sfence_vma & sfence_vma_all 2018-11-09 22:27:19 +08:00
bors[bot] 4e16dd85ed Merge #10 
10: these raw instructions are unsafe r=dvc94ch a=strake

`wfi` is safe, but the rest are not. Let's make them all unsafe until we have a better idea — the return types are wrong anyhow.


Co-authored-by: M Farkas-Dyck <strake888@gmail.com>
 2018-08-19 17:02:05 +00:00
bors[bot] 591b7df808 Merge #9 
9: use `NonZeroUsize` where appropriate r=dvc94ch a=strake



Co-authored-by: M Farkas-Dyck <strake888@gmail.com>
 2018-08-19 11:12:24 +00:00
bors[bot] 489b88f66b Merge #8 
8: mepc is word-size r=dvc94ch a=strake



Co-authored-by: M Farkas-Dyck <strake888@gmail.com>
 2018-08-19 08:49:02 +00:00
M Farkas-Dyck 8e0faa9182 these raw instructions are unsafe 2018-08-18 10:26:59 -08:00
M Farkas-Dyck 5a88960ee0 use `NonZeroUsize` where appropriate 2018-08-18 10:15:10 -08:00
M Farkas-Dyck ecc69bda00 mepc is word-size 2018-08-18 10:10:08 -08:00
David Craven 8d530616c9
Build master branch too. 2018-08-12 09:12:57 +02:00
David Craven be2a15f34e Bump version and update url. 2018-08-12 08:59:12 +02:00
David Craven b03aae8850 Update README. 2018-08-12 08:59:12 +02:00
David Craven 5e55720ad8 Update bare-metal. 2018-08-12 08:59:12 +02:00
David Craven 34b2ba33cd Add inline-asm feature. 2018-08-12 08:59:12 +02:00
David Craven 59d46795b2 A unified contributing experience. 2018-08-12 08:59:12 +02:00
Dan Callaghan 6769ac9262 fix target_arch conditionals to match "riscv32" and "riscv64" 
In the original riscv-rust fork the target arch was simply named
"riscv", but RISC-V support landed in Rust with "riscv32" as the arch
name instead.

Include "riscv64" optimistically for future-proofing.
 2018-08-06 08:41:45 +10:00
David Craven 87bcdd8bab
Bump version. 2018-04-25 19:43:37 +02:00
Jakob Weisblat 8597f1c32d Fix typo in register/misa.rs 2018-04-02 08:17:23 +02:00
David Craven 45364b26a8
Add mepc register. 2018-03-30 12:14:27 +02:00
David Craven cd5200c5fa
Fix mstatus register value. 2018-03-29 15:37:49 +02:00
David Craven 7db0e71060
New api. 2018-03-27 20:17:44 +02:00
David Craven 179df42984
Remove inline(always). 2018-03-24 19:27:00 +01:00
David Craven 21bfaf49ae
mcause is read-only. 2017-11-21 09:52:15 +01:00
David Craven 0d9d6cf334
Bump version to 0.1.4 2017-11-20 14:23:53 +01:00
David Craven bb41b209a6
Read bits only once. 2017-11-20 14:14:01 +01:00
David Craven b42411e64a
Bump version to 0.1.3 2017-11-18 14:10:40 +01:00
David Craven 1b98011118
Killing me softly. 2017-11-18 14:09:53 +01:00
David Craven fd78d9bffc
Bump version to 0.1.2 2017-11-18 14:05:00 +01:00
David Craven 94c3b5561e
Update bare-metal to 0.1.1. 2017-11-18 14:04:19 +01:00
David Craven 6ebb6f9790
Bump version to 0.1.1 2017-11-18 09:45:01 +01:00
David Craven 467327cb15
Allow compiling on x86_64 for publishing. 2017-11-18 08:46:19 +01:00
David Craven e864581828
Initial commit. 2017-09-19 16:23:35 +02:00