vexriscv-rust/Cargo.toml

[package]
name = "riscv"
version = "0.5.3"
repository = "https://github.com/rust-embedded/riscv"
authors = ["The RISC-V Team <risc-v@teams.rust-embedded.org>"]
categories = ["embedded", "hardware-support", "no-std"]
description = "Low level access to RISC-V processors"
keywords = ["riscv", "register", "peripheral"]
license = "ISC"

[dependencies]
bare-metal = "0.2.0"
bit_field = "0.9.0"

[features]
inline-asm = []
Initial commit. 2017-09-19 22:04:12 +08:00			`[package]`
			`name = "riscv"`
Bump version (0.5.3) 2019-04-29 16:45:19 +08:00			`version = "0.5.3"`
Bump version and update url. 2018-08-12 13:50:11 +08:00			`repository = "https://github.com/rust-embedded/riscv"`
Leave just team e-mail in authors 2019-02-08 00:53:22 +08:00			`authors = ["The RISC-V Team <risc-v@teams.rust-embedded.org>"]`
Initial commit. 2017-09-19 22:04:12 +08:00			`categories = ["embedded", "hardware-support", "no-std"]`
Fix RISC-V name https://riscv.org/risc-v-trademark-usage/ 2019-01-24 22:19:32 +08:00			`description = "Low level access to RISC-V processors"`
Initial commit. 2017-09-19 22:04:12 +08:00			`keywords = ["riscv", "register", "peripheral"]`
			`license = "ISC"`

			`[dependencies]`
Update bare-metal. 2018-08-12 13:57:55 +08:00			`bare-metal = "0.2.0"`
add S-Mode registers - use macros to simplify CSR ops - use crate 'bit_field' to make bits operation clear 2018-11-09 22:42:46 +08:00			`bit_field = "0.9.0"`
Add inline-asm feature. 2018-08-12 13:56:17 +08:00
			`[features]`
			`inline-asm = []`