revert "add old version of the system"

master
ciciwu 2021-12-23 16:38:10 +08:00
parent fad4213dab
commit 1e1a956121
2 changed files with 23 additions and 62 deletions

View File

@ -1,50 +0,0 @@
{
"target": "kasli",
"min_artiq_version": "6.0",
"variant": "sias2",
"hw_rev": "v2.0",
"base": "standalone",
"core_addr": "192.168.1.75",
"peripherals": [
{
"type": "dio",
"board": "DIO_SMA",
"ports": [0],
"edge_counter": true,
"bank_direction_low": "input",
"bank_direction_high": "output"
},
{
"type": "dio",
"board": "DIO_SMA",
"ports": [1],
"bank_direction_low": "output",
"bank_direction_high": "output"
},
{
"type": "dio",
"board": "DIO_SMA",
"ports": [2],
"bank_direction_low": "output",
"bank_direction_high": "output"
},
{
"type": "dio",
"board": "DIO_SMA",
"ports": [3],
"bank_direction_low": "output",
"bank_direction_high": "output"
},
{
"type": "fastino",
"ports": [4]
},
{
"type": "suservo",
"sampler_ports": [10, 11],
"urukul0_ports": [6, 7],
"urukul1_ports": [8, 9],
"clk_sel": 2
}
]
}

View File

@ -7,32 +7,43 @@
"peripherals": [ "peripherals": [
{ {
"type": "dio", "type": "dio",
"board": "DIO_SMA",
"ports": [0], "ports": [0],
"edge_counter": true,
"bank_direction_low": "input", "bank_direction_low": "input",
"bank_direction_high": "output" "bank_direction_high": "output"
}, },
{ {
"type": "dio", "type": "dio",
"board": "DIO_SMA",
"ports": [1], "ports": [1],
"bank_direction_low": "output", "bank_direction_low": "output",
"bank_direction_high": "output" "bank_direction_high": "output"
}, },
{ {
"type": "suservo", "type": "dio",
"sampler_ports": [2, 3], "board": "DIO_SMA",
"urukul0_ports": [4, 5], "ports": [2],
"urukul1_ports": [6, 7], "bank_direction_low": "output",
"clk_sel": 2 "bank_direction_high": "output"
}, },
{ {
"type": "urukul", "type": "dio",
"dds": "ad9910", "board": "DIO_SMA",
"ports": [8, 9], "ports": [3],
"clk_sel": 2 "bank_direction_low": "output",
"bank_direction_high": "output"
}, },
{ {
"type": "fastino", "type": "fastino",
"ports": [10] "ports": [4]
},
{
"type": "suservo",
"sampler_ports": [10, 11],
"urukul0_ports": [6, 7],
"urukul1_ports": [8, 9],
"clk_sel": 2
} }
] ]
} }