5 Commits (13a44fc18591c605e89db86c74ea804a3ed8a0d8)

Author	SHA1	Message	Date
Sebastien Bourdeauducq	13a44fc185	dma: work around BRAM->AXI Xilinx insanity	2022-08-30 16:41:45 +08:00
Sebastien Bourdeauducq	ec417eaf1e	dma: fix/improve logic	2022-08-30 16:39:35 +08:00
Sebastien Bourdeauducq	8a93f74c70	clock system with ADC clock	2022-08-29 22:43:51 +08:00
Sebastien Bourdeauducq	bf13e9f7c3	ADC DMA complete, not working for obscure reason	2020-10-25 18:58:33 +08:00
Sebastien Bourdeauducq	2c588992c5	DMA demo	2020-10-25 15:16:03 +08:00