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Formally verified ARTIQ RTIO core in nMigen
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Donald Sebastian Leung f7c1cc23a5 Implement artiq.gateware.rtio.rtlink 2020-09-25 12:49:14 +08:00
artiq Implement artiq.gateware.rtio.rtlink 2020-09-25 12:49:14 +08:00
misoc Add project structure 2020-09-25 12:04:28 +08:00
LICENSE Add README and LICENSE 2020-09-23 17:14:27 +08:00
README.md Implement artiq.gateware.rtio.rtlink 2020-09-25 12:49:14 +08:00
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README.md

rtio-nmigen

Formally verified implementation of the ARTIQ RTIO core in nMigen

Progress

  • Implement the core in nMigen
    • artiq.gateware.rtio.core
    • misoc.interconnect.csr
    • artiq.gateware.rtio.cri
    • artiq.gateware.rtio.rtlink
    • artiq.gateware.rtio.channel
    • artiq.gateware.rtio.sed.core
    • artiq.gateware.rtio.sed.layouts
    • artiq.gateware.rtio.sed.lane_distributor
    • artiq.gateware.rtio.sed.fifos
    • artiq.gateware.rtio.sed.gates
    • artiq.gateware.rtio.sed.output_driver
    • artiq.gateware.rtio.sed.output_network
    • artiq.gateware.rtio.input_collector
  • Add suitable assertions for verification (BMC / unbounded proof?)

License

Copyright (C) 2020 M-Labs Limited.

LGPLv3 or any later version