M-Labs
/
rtio-nmigen
7
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Fix keyword argument issue in rtio.cri

This commit is contained in:
Donald Sebastian Leung 2020-10-14 17:26:38 +08:00
parent ceab41f9da
commit b4ec588630
2 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
README.md
View File

@ -6,7 +6,7 @@ Formally verified implementation of the ARTIQ RTIO core in nMigen
- Devise a suitable migration strategy for `artiq.gateware.rtio` from Migen to nMigen - Devise a suitable migration strategy for `artiq.gateware.rtio` from Migen to nMigen
- [x] Implement the core in nMigen - [x] Implement the core in nMigen
- - [x] `rtio.cri` (`Interface` and `CRIDecoder` only) - - [ ] `rtio.cri` (`Interface` and `CRIDecoder` only)
- - [x] `rtio.rtlink` - - [x] `rtio.rtlink`
- - [x] `rtio.sed.layouts` - - [x] `rtio.sed.layouts`
- - [x] `rtio.sed.output_network` - - [x] `rtio.sed.output_network`

4
rtio/cri.py
View File

@ -84,12 +84,12 @@ class CRIDecoder(Elaboratable):
selected = Signal(slave_bits) selected = Signal(slave_bits)
if enable_routing: if enable_routing:
routing_table = Memory(slave_bits, 256) routing_table = Memory(width=slave_bits, depth=256)
if mode == "async": if mode == "async":
rtp_decoder = routing_table.read_port() rtp_decoder = routing_table.read_port()
elif mode == "sync": elif mode == "sync":
rtp_decoder = routing_table.read_port(clock_domain="rtio") rtp_decoder = routing_table.read_port(clock_domain="rtio") # FIXME
else: else:
raise ValueError raise ValueError
m.submodules += rtp_decoder m.submodules += rtp_decoder