From b4ec588630874fde9b63a436384834ccb15b9275 Mon Sep 17 00:00:00 2001
From: Donald Sebastian Leung <dl@m-labs.hk>
Date: Wed, 14 Oct 2020 17:26:38 +0800
Subject: [PATCH] Fix keyword argument issue in rtio.cri

---
 README.md   | 2 +-
 rtio/cri.py | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/README.md b/README.md
index 7c5f4db..37ce389 100644
--- a/README.md
+++ b/README.md
@@ -6,7 +6,7 @@ Formally verified implementation of the ARTIQ RTIO core in nMigen
 
 - Devise a suitable migration strategy for `artiq.gateware.rtio` from Migen to nMigen
 - [x] Implement the core in nMigen
-- - [x] `rtio.cri` (`Interface` and `CRIDecoder` only)
+- - [ ] `rtio.cri` (`Interface` and `CRIDecoder` only)
 - - [x] `rtio.rtlink`
 - - [x] `rtio.sed.layouts`
 - - [x] `rtio.sed.output_network`
diff --git a/rtio/cri.py b/rtio/cri.py
index 1d6bb0e..0c2cad7 100644
--- a/rtio/cri.py
+++ b/rtio/cri.py
@@ -84,12 +84,12 @@ class CRIDecoder(Elaboratable):
         selected = Signal(slave_bits)
 
         if enable_routing:
-            routing_table = Memory(slave_bits, 256)
+            routing_table = Memory(width=slave_bits, depth=256)
 
             if mode == "async":
                 rtp_decoder = routing_table.read_port()
             elif mode == "sync":
-                rtp_decoder = routing_table.read_port(clock_domain="rtio")
+                rtp_decoder = routing_table.read_port(clock_domain="rtio") # FIXME
             else:
                 raise ValueError
             m.submodules += rtp_decoder