Add uniqueness assertion for case with no replacements
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@ -55,10 +55,10 @@ class OutputNetwork(Elaboratable):
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if fv_mode:
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if fv_mode:
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# Model arbitrary inputs for network nodes
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# Model arbitrary inputs for network nodes
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for i in range(lane_count):
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for i in range(lane_count):
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m.d.comb += self.input[i].valid.eq(AnySeq(1))
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m.d.comb += self.input[i].valid.eq(1)
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m.d.comb += self.input[i].seqn.eq(AnySeq(seqn_width))
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m.d.comb += self.input[i].seqn.eq(AnySeq(seqn_width))
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m.d.comb += self.input[i].replace_occured.eq(AnySeq(1))
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m.d.comb += self.input[i].replace_occured.eq(0)
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m.d.comb += self.input[i].nondata_replace_occured.eq(AnySeq(1))
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m.d.comb += self.input[i].nondata_replace_occured.eq(0)
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for field, width in layout_payload:
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for field, width in layout_payload:
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m.d.comb += getattr(self.input[i].payload, field).eq(AnySeq(width))
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m.d.comb += getattr(self.input[i].payload, field).eq(AnySeq(width))
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@ -119,9 +119,51 @@ class OutputNetwork(Elaboratable):
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f_past_valid = Signal()
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f_past_valid = Signal()
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m.d.sync += f_past_valid.eq(1)
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m.d.sync += f_past_valid.eq(1)
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# Valid nodes always come first in outputs
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# Indicator of when inputs from the first clock cycle make it
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for i in range(lane_count - 1):
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# through the sorting network
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m.d.comb += Assert(self.output[i].valid | ~self.output[i + 1].valid) # TODO: Figure out why this is failing
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network_latency = latency(lane_count)
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counter = Signal(range(network_latency + 1))
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m.d.sync += counter.eq(counter + 1)
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with m.If(counter == network_latency):
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m.d.sync += counter.eq(counter)
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f_output_valid = Signal()
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m.d.comb += f_output_valid.eq(counter == network_latency)
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# If there are no replacements, all input data are unique and they
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# all make it through the sorting network
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with m.If(f_output_valid):
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replacement_occurred = Signal()
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for node in self.output:
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with m.If(node.replace_occured):
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m.d.comb += replacement_occurred.eq(1)
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with m.If(~replacement_occurred):
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nodes_unique = Signal(reset=1)
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for node1 in range(len(self.input)):
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for node2 in range(node1):
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k1 = Cat(Past(self.input[node1].payload.channel, clocks=network_latency), ~Past(self.input[node1].valid, clocks=network_latency))
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k2 = Cat(Past(self.input[node2].payload.channel, clocks=network_latency), ~Past(self.input[node2].valid, clocks=network_latency))
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with m.If(k1 == k2):
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m.d.comb += nodes_unique.eq(0)
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m.d.comb += Assert(nodes_unique)
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# TODO: figure out why the rest is failing
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# appeared = Signal(len(self.input))
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# for input_node in range(len(self.input)):
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# for output_node in self.output:
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# identical = Signal(reset=1)
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# with m.If(Past(self.input[input_node].valid, clocks=network_latency) != output_node.valid):
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# m.d.comb += identical.eq(0)
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# with m.If(Past(self.input[input_node].seqn, clocks=network_latency) != output_node.seqn):
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# m.d.comb += identical.eq(0)
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# with m.If(Past(self.input[input_node].replace_occured, clocks=network_latency) != output_node.replace_occured):
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# m.d.comb += identical.eq(0)
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# with m.If(Past(self.input[input_node].nondata_replace_occured, clocks=network_latency) != output_node.nondata_replace_occured):
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# m.d.comb += identical.eq(0)
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# for field, _ in layout_payload:
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# with m.If(Past(getattr(self.input[input_node].payload, field), clocks=network_latency) != getattr(output_node.payload, field)):
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# m.d.comb += identical.eq(0)
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# m.d.comb += appeared[input_node].eq(identical)
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# for i in range(len(self.input)):
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# m.d.comb += Assert(appeared[i])
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def elaborate(self, platform):
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def elaborate(self, platform):
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return self.m
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return self.m
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