M-Labs
/
rtio-nmigen
7
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Refine assertions for case with replacements in sorting network

pull/1/head
Donald Sebastian Leung 2020-10-22 13:32:12 +08:00
parent 40930878a2
commit 25a8a741bb
1 changed files with 9 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
rtio/sed/output_network.py
View File

@ -170,7 +170,7 @@ class OutputNetwork(Elaboratable):
# Otherwise, if there are replacements: # Otherwise, if there are replacements:
# - Channel numbers are not unique # - Channel numbers are not unique
# - Not all outputs are valid # - Not all outputs are valid
# - All channel numbers in the input appear somewhere as a # - All channel numbers in the input appear exactly once as a
# valid output # valid output
with m.Else(): with m.Else():
m.d.comb += Assert(~channels_unique) m.d.comb += Assert(~channels_unique)
@ -180,11 +180,14 @@ class OutputNetwork(Elaboratable):
m.d.comb += all_valid.eq(0) m.d.comb += all_valid.eq(0)
m.d.comb += Assert(~all_valid) m.d.comb += Assert(~all_valid)
for input_node in self.input: for input_node in self.input:
appeared_valid = Signal() input_channel_valid_once = Const(0)
for output_node in self.output: for node1 in range(len(self.output)):
with m.If((Past(input_node.payload.channel, clocks=network_latency) == output_node.payload.channel) & output_node.valid): accum = (Past(input_node.payload.channel, clocks=network_latency) == self.output[node1].payload.channel) & self.output[node1].valid
m.d.comb += appeared_valid.eq(1) for node2 in range(len(self.output)):
m.d.comb += Assert(appeared_valid) if node1 != node2:
accum = accum & ((Past(input_node.payload.channel, clocks=network_latency) != self.output[node2].payload.channel) | ~self.output[node2].valid)
input_channel_valid_once = input_channel_valid_once | accum
m.d.comb += Assert(input_channel_valid_once)
def elaborate(self, platform): def elaborate(self, platform):
return self.m return self.m