From 1a83778590eb0019eeba08c15039730140ae71fb Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Fri, 25 Sep 2020 15:10:07 +0800 Subject: [PATCH] Remove redundant 'artiq.gateware' from module names --- README.md | 25 +++++++++---------- artiq/gateware/rtio/__init__.py | 0 artiq/gateware/rtio/sed/__init__.py | 0 misoc/__init__.py | 0 misoc/interconnect/__init__.py | 0 misoc/interconnect/csr.py | 0 {artiq => rtio}/__init__.py | 0 {artiq/gateware/rtio => rtio}/channel.py | 2 +- {artiq/gateware/rtio => rtio}/core.py | 0 {artiq/gateware/rtio => rtio}/cri.py | 0 .../gateware/rtio => rtio}/input_collector.py | 0 {artiq/gateware/rtio => rtio}/rtlink.py | 0 {artiq/gateware => rtio/sed}/__init__.py | 0 {artiq/gateware/rtio => rtio}/sed/core.py | 0 {artiq/gateware/rtio => rtio}/sed/fifos.py | 0 {artiq/gateware/rtio => rtio}/sed/gates.py | 0 .../rtio => rtio}/sed/lane_distributor.py | 0 {artiq/gateware/rtio => rtio}/sed/layouts.py | 2 +- .../rtio => rtio}/sed/output_driver.py | 0 .../rtio => rtio}/sed/output_network.py | 0 20 files changed, 14 insertions(+), 15 deletions(-) delete mode 100644 artiq/gateware/rtio/__init__.py delete mode 100644 artiq/gateware/rtio/sed/__init__.py delete mode 100644 misoc/__init__.py delete mode 100644 misoc/interconnect/__init__.py delete mode 100644 misoc/interconnect/csr.py rename {artiq => rtio}/__init__.py (100%) rename {artiq/gateware/rtio => rtio}/channel.py (96%) rename {artiq/gateware/rtio => rtio}/core.py (100%) rename {artiq/gateware/rtio => rtio}/cri.py (100%) rename {artiq/gateware/rtio => rtio}/input_collector.py (100%) rename {artiq/gateware/rtio => rtio}/rtlink.py (100%) rename {artiq/gateware => rtio/sed}/__init__.py (100%) rename {artiq/gateware/rtio => rtio}/sed/core.py (100%) rename {artiq/gateware/rtio => rtio}/sed/fifos.py (100%) rename {artiq/gateware/rtio => rtio}/sed/gates.py (100%) rename {artiq/gateware/rtio => rtio}/sed/lane_distributor.py (100%) rename {artiq/gateware/rtio => rtio}/sed/layouts.py (98%) rename {artiq/gateware/rtio => rtio}/sed/output_driver.py (100%) rename {artiq/gateware/rtio => rtio}/sed/output_network.py (100%) diff --git a/README.md b/README.md index 3e76597..6f66d9e 100644 --- a/README.md +++ b/README.md @@ -5,19 +5,18 @@ Formally verified implementation of the ARTIQ RTIO core in nMigen ## Progress - [ ] Implement the core in nMigen -- - [ ] `artiq.gateware.rtio.core` -- - [ ] `misoc.interconnect.csr` -- - [ ] `artiq.gateware.rtio.cri` -- - [x] `artiq.gateware.rtio.rtlink` -- - [x] `artiq.gateware.rtio.channel` -- - [ ] `artiq.gateware.rtio.sed.core` -- - [x] `artiq.gateware.rtio.sed.layouts` -- - [ ] `artiq.gateware.rtio.sed.lane_distributor` -- - [ ] `artiq.gateware.rtio.sed.fifos` -- - [ ] `artiq.gateware.rtio.sed.gates` -- - [ ] `artiq.gateware.rtio.sed.output_driver` -- - [ ] `artiq.gateware.rtio.sed.output_network` -- - [ ] `artiq.gateware.rtio.input_collector` +- - [ ] `rtio.core` +- - [ ] `rtio.cri` +- - [x] `rtio.rtlink` +- - [x] `rtio.channel` +- - [ ] `rtio.sed.core` +- - [x] `rtio.sed.layouts` +- - [ ] `rtio.sed.lane_distributor` +- - [ ] `rtio.sed.fifos` +- - [ ] `rtio.sed.gates` +- - [ ] `rtio.sed.output_driver` +- - [ ] `rtio.sed.output_network` +- - [ ] `rtio.input_collector` - [ ] Add suitable assertions for verification (BMC / unbounded proof?) ## License diff --git a/artiq/gateware/rtio/__init__.py b/artiq/gateware/rtio/__init__.py deleted file mode 100644 index e69de29..0000000 diff --git a/artiq/gateware/rtio/sed/__init__.py b/artiq/gateware/rtio/sed/__init__.py deleted file mode 100644 index e69de29..0000000 diff --git a/misoc/__init__.py b/misoc/__init__.py deleted file mode 100644 index e69de29..0000000 diff --git a/misoc/interconnect/__init__.py b/misoc/interconnect/__init__.py deleted file mode 100644 index e69de29..0000000 diff --git a/misoc/interconnect/csr.py b/misoc/interconnect/csr.py deleted file mode 100644 index e69de29..0000000 diff --git a/artiq/__init__.py b/rtio/__init__.py similarity index 100% rename from artiq/__init__.py rename to rtio/__init__.py diff --git a/artiq/gateware/rtio/channel.py b/rtio/channel.py similarity index 96% rename from artiq/gateware/rtio/channel.py rename to rtio/channel.py index d7b9a60..6c0c440 100644 --- a/artiq/gateware/rtio/channel.py +++ b/rtio/channel.py @@ -1,6 +1,6 @@ import warnings -from artiq.gateware.rtio import rtlink +from rtio import rtlink class Channel: diff --git a/artiq/gateware/rtio/core.py b/rtio/core.py similarity index 100% rename from artiq/gateware/rtio/core.py rename to rtio/core.py diff --git a/artiq/gateware/rtio/cri.py b/rtio/cri.py similarity index 100% rename from artiq/gateware/rtio/cri.py rename to rtio/cri.py diff --git a/artiq/gateware/rtio/input_collector.py b/rtio/input_collector.py similarity index 100% rename from artiq/gateware/rtio/input_collector.py rename to rtio/input_collector.py diff --git a/artiq/gateware/rtio/rtlink.py b/rtio/rtlink.py similarity index 100% rename from artiq/gateware/rtio/rtlink.py rename to rtio/rtlink.py diff --git a/artiq/gateware/__init__.py b/rtio/sed/__init__.py similarity index 100% rename from artiq/gateware/__init__.py rename to rtio/sed/__init__.py diff --git a/artiq/gateware/rtio/sed/core.py b/rtio/sed/core.py similarity index 100% rename from artiq/gateware/rtio/sed/core.py rename to rtio/sed/core.py diff --git a/artiq/gateware/rtio/sed/fifos.py b/rtio/sed/fifos.py similarity index 100% rename from artiq/gateware/rtio/sed/fifos.py rename to rtio/sed/fifos.py diff --git a/artiq/gateware/rtio/sed/gates.py b/rtio/sed/gates.py similarity index 100% rename from artiq/gateware/rtio/sed/gates.py rename to rtio/sed/gates.py diff --git a/artiq/gateware/rtio/sed/lane_distributor.py b/rtio/sed/lane_distributor.py similarity index 100% rename from artiq/gateware/rtio/sed/lane_distributor.py rename to rtio/sed/lane_distributor.py diff --git a/artiq/gateware/rtio/sed/layouts.py b/rtio/sed/layouts.py similarity index 98% rename from artiq/gateware/rtio/sed/layouts.py rename to rtio/sed/layouts.py index 4930af6..c731e4c 100644 --- a/artiq/gateware/rtio/sed/layouts.py +++ b/rtio/sed/layouts.py @@ -2,7 +2,7 @@ from nmigen import * from nmigen.utils import * from nmigen.hdl.rec import * -from artiq.gateware.rtio import rtlink +from rtio import rtlink def fifo_payload(channels): diff --git a/artiq/gateware/rtio/sed/output_driver.py b/rtio/sed/output_driver.py similarity index 100% rename from artiq/gateware/rtio/sed/output_driver.py rename to rtio/sed/output_driver.py diff --git a/artiq/gateware/rtio/sed/output_network.py b/rtio/sed/output_network.py similarity index 100% rename from artiq/gateware/rtio/sed/output_network.py rename to rtio/sed/output_network.py