138 lines
5.4 KiB
Markdown
138 lines
5.4 KiB
Markdown
# RISC-V Instructions
|
|
|
|
## Instructions
|
|
|
|
Below is a table of RISC-V instructions supported by the original riscv-formal framework at the time of writing, categorized by instruction type.
|
|
|
|
| Instruction type | Instructions |
|
|
| --- | --- |
|
|
| R-type | ADD, ADDW, AND, DIV, DIVU, DIVUW, DIVW, MUL, MULH, MULHSU, MULHU, MULW, OR, REM, REMU, REMUW, REMW, SLL, SLLW, SLT, SLTU, SRA, SRAW, SRL, SRLW, SUB, SUBW, XOR |
|
|
| I-type | ADDI, ADDIW, ANDI, JALR, LB, LBU, LD, LH, LHU, LW, LWU, ORI, SLTI, SLTIU, XORI |
|
|
| I-type (shift variation) | SLLI, SLLIW, SRAI, SRAIW, SRLI, SRLIW |
|
|
| S-type | SB, SD, SH, SW |
|
|
| SB-type | BEQ, BGE, BGEU, BLT, BLTU, BNE |
|
|
| U-type | AUIPC, LUI |
|
|
| UJ-type | JAL |
|
|
| CI-type | C\_ADD, C\_ADDI, C\_ADDIW, C\_JALR, C\_JR, C\_LI, C\_MV |
|
|
| CI-type (SP variation) | C\_ADDI16SP |
|
|
| CI-type (ANDI variation) | C\_ANDI |
|
|
| CI-type (LSP variation, 32 bit version) | C\_LWSP |
|
|
| CI-type (LSP variation, 64 bit version) | C\_LDSP |
|
|
| CI-type (LUI variation) | C\_LUI |
|
|
| CI-type (SLI variation) | C\_SLLI |
|
|
| CI-type (SRI variation) | C\_SRAI, C\_SRLI |
|
|
| CIW-type | C\_ADDI4SPN |
|
|
| CS-type (ALU version) | C\_ADDW, C\_AND, C\_OR, C\_SUB, C\_SUBW, C\_XOR |
|
|
| CS-type (32 bit version) | C\_SW |
|
|
| CS-type (64 bit version) | C\_SD |
|
|
| CSS-type (32 bit version) | C\_SWSP |
|
|
| CSS-type (64 bit version) | C\_SDSP |
|
|
| CB-type | C\_BEQZ, C\_BNEZ |
|
|
| CJ-type | C\_J, C\_JAL |
|
|
| CL-type (32 bit version) | C\_LW |
|
|
| CL-type (64 bit version) | C\_LD |
|
|
|
|
## Class Synopsis
|
|
|
|
### Instructions
|
|
|
|
Below is a list of instructions currently supported by this port of the riscv-formal framework and is expected to grow over time. The instructions are roughly grouped by instruction type but sometimes with further specializations - the hierarchy of the lists reflects the hierarchy of inheritance in the classes used to represent various instructions.
|
|
|
|
- `Insn`: General RISC-V instruction
|
|
- `InsnRV32IRType`: RV32I R-Type Instruction
|
|
- `InsnAdd`: ADD instruction
|
|
- `InsnSub`: SUB instruction
|
|
- `InsnSll`: SLL instruction
|
|
- `InsnSlt`: SLT instruction
|
|
- `InsnSltu`: SLTU instruction
|
|
- `InsnXor`: XOR instruction
|
|
- `InsnSrl`: SRL instruction
|
|
- `InsnSra`: SRA instruction
|
|
- `InsnOr`: OR instruction
|
|
- `InsnAnd`: AND instruction
|
|
- `InsnRV32IITypeShift`: RV32I I-Type Instruction (Shift Variation)
|
|
- `InsnSlli`: SLLI instruction
|
|
- `InsnSrli`: SRLI instruction
|
|
- `InsnSrai`: SRAI instruction
|
|
- `InsnRV32IIType`: RV32I I-Type Instruction
|
|
- `InsnJalr`: JALR instruction
|
|
- `InsnRV32IITypeLoad`: RV32I I-Type Instruction (Load Variation)
|
|
- `InsnLb`: LB instruction
|
|
- `InsnLh`: LH instruction
|
|
- `InsnLw`: LW instruction
|
|
- `InsnLbu`: LBU instruction
|
|
- `InsnLhu`: LHU instruction
|
|
- `InsnRV32IITypeArith`: RV32I I-Type Instruction (Arithmetic Variation)
|
|
- `InsnAddi`: ADDI instruction
|
|
- `InsnSlti`: SLTI instruction
|
|
- `InsnSltiu`: SLTIU instruction
|
|
- `InsnXori`: XORI instruction
|
|
- `InsnOri`: ORI instruction
|
|
- `InsnAndi`: ANDI instruction
|
|
- `InsnRV32ISType`: RV32I S-Type Instruction
|
|
- `InsnSb`: SB instruction
|
|
- `InsnSh`: SH instruction
|
|
- `InsnSw`: SW instruction
|
|
- `InsnRV32ISBType`: RV32I SB-Type Instruction
|
|
- `InsnBeq`: BEQ instruction
|
|
- `InsnBne`: BNE instruction
|
|
- `InsnBlt`: BLT instruction
|
|
- `InsnBge`: BGE instruction
|
|
- `InsnBltu`: BLTU instruction
|
|
- `InsnBgeu`: BGEU instruction
|
|
- `InsnJal`: JAL instruction
|
|
- `InsnRV32IUType`: RV32I U-Type Instruction
|
|
- `InsnLui`: LUI instruction
|
|
- `InsnAuipc`: AUIPC instruction
|
|
- `InsnRV32MRType`: RV32M R-Type Instruction
|
|
- `InsnMul`: MUL instruction
|
|
- `InsnMulh`: MULH instruction
|
|
- `InsnMulhsu`: MULHSU instruction
|
|
- `InsnMulhu`: MULHU instruction
|
|
- `InsnDiv`: DIV instruction
|
|
- `InsnDivu`: DIVU instruction
|
|
- `InsnRem`: REM instruction
|
|
- `InsnRemu`: REMU instruction
|
|
- `InsnRV64IIType`: RV64I I-Type Instruction
|
|
- `InsnRV64IITypeLoad`: RV64I I-Type Instruction (Load Variation)
|
|
- `InsnLwu`: LWU instruction
|
|
- `InsnLd`: LD instruction
|
|
- `InsnAddiw`: ADDIW instruction
|
|
- `InsnRV64IITypeShift`: RV64I I-Type Instruction (Shift Variation)
|
|
- `InsnSlliw`: SLLIW instruction
|
|
- `InsnSrliw`: SRLIW instruction
|
|
- `InsnSraiw`: SRAIW instruction
|
|
- `InsnRV64IRType`: RV64I R-Type Instruction
|
|
- `InsnAddw`: ADDW instruction
|
|
- `InsnSubw`: SUBW instruction
|
|
- `InsnSllw`: SLLW instruction
|
|
- `InsnSrlw`: SRLW instruction
|
|
- `InsnSraw`: SRAW instruction
|
|
- `InsnSd`: SD instruction
|
|
- `InsnRV64MRType`: RV64M R-Type Instruction
|
|
- `InsnMulw`: MULW instruction
|
|
- `InsnDivw`: DIVW instruction
|
|
- `InsnDivuw`: DIVUW instruction
|
|
- `InsnRemw`: REMW instruction
|
|
- `InsnRemuw`: REMUW instruction
|
|
|
|
### ISAs
|
|
|
|
- `IsaRV32I`: RV32I Base ISA
|
|
- `IsaRV32M`: RV32M Standard Extension
|
|
- `IsaRV64I`: RV64I Base ISA
|
|
- `IsaRV64M`: RV64M Standard Extension
|
|
|
|
## Core-specific parameters
|
|
|
|
The following core-specific parameters are currently supported:
|
|
|
|
| Parameter | Description | Valid value(s) |
|
|
| --- | --- | --- |
|
|
| `params.ilen` | Max length of instruction retired by core | `32`, `64` |
|
|
| `params.xlen` | Width of integer registers | `32`, `64` |
|
|
| `params.csr_misa` | Support for MISA CSRs enabled | `True`, `False` |
|
|
| `params.compressed` | Support for compressed instructions | `True`, `False` |
|
|
| `params.aligned_mem` | Require aligned memory accesses | `True`, `False` |
|
|
| `params.altops` | Use alternative operations for multiplication/division | `True`, `False` |
|