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riscv-formal-nmigen/rvfi/insns/README.md

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RISC-V Instructions

Instructions

Below is a table of RISC-V instructions supported by the original riscv-formal framework at the time of writing, categorized by instruction type.

Instruction type Instructions
R-type ADD, ADDW, AND, DIV, DIVU, DIVUW, DIVW, MUL, MULH, MULHSU, MULHU, MULW, OR, REM, REMU, REMUW, REMW, SLL, SLLW, SLT, SLTU, SRA, SRAW, SRL, SRLW, SUB, SUBW, XOR
I-type ADDI, ADDIW, ANDI, JALR, LB, LBU, LD, LH, LHU, LW, LWU, ORI, SLTI, SLTIU, XORI
I-type (shift variation) SLLI, SLLIW, SRAI, SRAIW, SRLI, SRLIW
S-type SB, SD, SH, SW
SB-type BEQ, BGE, BGEU, BLT, BLTU, BNE
U-type AUIPC, LUI
UJ-type JAL
CI-type C_ADD, C_ADDI, C_ADDIW, C_JALR, C_JR, C_LI, C_MV
CI-type (SP variation) C_ADDI16SP
CI-type (ANDI variation) C_ANDI
CI-type (LSP variation, 32 bit version) C_LWSP
CI-type (LSP variation, 64 bit version) C_LDSP
CI-type (LUI variation) C_LUI
CI-type (SLI variation) C_SLLI
CI-type (SRI variation) C_SRAI, C_SRLI
CIW-type C_ADDI4SPN
CS-type (ALU version) C_ADDW, C_AND, C_OR, C_SUB, C_SUBW, C_XOR
CS-type (32 bit version) C_SW
CS-type (64 bit version) C_SD
CSS-type (32 bit version) C_SWSP
CSS-type (64 bit version) C_SDSP
CB-type C_BEQZ, C_BNEZ
CJ-type C_J, C_JAL
CL-type (32 bit version) C_LW
CL-type (64 bit version) C_LD

Class Synopsis

Instructions

Below is a list of instructions currently supported by this port of the riscv-formal framework and is expected to grow over time. The instructions are roughly grouped by instruction type but sometimes with further specializations - the hierarchy of the lists reflects the hierarchy of inheritance in the classes used to represent various instructions.

  • Insn: General RISC-V instruction
    • InsnRV32IRType: RV32I R-Type Instruction
      • InsnAdd: ADD instruction
      • InsnSub: SUB instruction
      • InsnSll: SLL instruction
      • InsnSlt: SLT instruction
      • InsnSltu: SLTU instruction
      • InsnXor: XOR instruction
      • InsnSrl: SRL instruction
      • InsnSra: SRA instruction
      • InsnOr: OR instruction
      • InsnAnd: AND instruction
    • InsnRV32IITypeShift: RV32I I-Type Instruction (Shift Variation)
      • InsnSlli: SLLI instruction
      • InsnSrli: SRLI instruction
      • InsnSrai: SRAI instruction
    • InsnRV32IIType: RV32I I-Type Instruction
      • InsnJalr: JALR instruction
      • InsnRV32IITypeLoad: RV32I I-Type Instruction (Load Variation)
        • InsnLb: LB instruction
        • InsnLh: LH instruction
        • InsnLw: LW instruction
        • InsnLbu: LBU instruction
        • InsnLhu: LHU instruction
      • InsnRV32IITypeArith: RV32I I-Type Instruction (Arithmetic Variation)
        • InsnAddi: ADDI instruction
        • InsnSlti: SLTI instruction
        • InsnSltiu: SLTIU instruction
        • InsnXori: XORI instruction
        • InsnOri: ORI instruction
        • InsnAndi: ANDI instruction
    • InsnRV32ISType: RV32I S-Type Instruction
      • InsnSb: SB instruction
      • InsnSh: SH instruction
      • InsnSw: SW instruction
    • InsnRV32ISBType: RV32I SB-Type Instruction
      • InsnBeq: BEQ instruction
      • InsnBne: BNE instruction
      • InsnBlt: BLT instruction
      • InsnBge: BGE instruction
      • InsnBltu: BLTU instruction
      • InsnBgeu: BGEU instruction
    • InsnJal: JAL instruction
    • InsnRV32IUType: RV32I U-Type Instruction
      • InsnLui: LUI instruction
      • InsnAuipc: AUIPC instruction

ISAs

  • IsaRV32I: RV32I Base ISA

Core-specific parameters

The following core-specific parameters are currently supported:

Parameter Description Valid value(s)
params.ilen Max length of instruction retired by core 32
params.xlen Width of integer registers 32
params.csr_misa Support for MISA CSRs enabled True, False
params.compressed Support for compressed instructions True, False
params.aligned_mem Require aligned memory accesses True, False