44 lines
1.9 KiB
Markdown
44 lines
1.9 KiB
Markdown
# riscv-formal-nmigen
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A port of [riscv-formal](https://github.com/SymbioticEDA/riscv-formal) to nMigen
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## Breakdown
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| File/Directory | Description |
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| --- | --- |
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| `shell.nix` | [nix-shell](https://nixos.wiki/wiki/Development_environment_with_nix-shell) configuration file |
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| `rvfi` | RISC-V Formal Verification Framework (nMigen port) |
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| `rvfi/insns` | Supported RISC-V instructions and ISAs |
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| `rvfi/checks` | Checks for RISC-V compliant cores |
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| `rvfi/cores` | Cores currently tested against this port of riscv-formal |
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| `rvfi/cores/minerva/verify.py` | Verification tasks for the Minerva core |
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## Running the Verification
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First make sure you have [Nix](https://nixos.org/download.html) installed. Then `cd` to the root directory of this repo and run:
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```bash
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$ nix-shell
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```
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This should run the tests (cache, multiplier, divider) provided by Minerva itself and give you an environment with all the dependencies required for this project. Then, to run the main verification tasks for Minerva provided in this repo:
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```bash
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$ python -m rvfi.cores.minerva.verify
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```
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This should run in the order of a few minutes.
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## Scope
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The RV32I, RV32M, RV64I and RV64M ISAs are currently implemented but yet to be fully tested. Support for compressed instructions may be added in the future as time permits.
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## Known Issues
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- 21/08/2020: Verification passes unconditionally, even in the presence of obvious bugs. This is due to the `rvfi.valid` signal from the CPU being held at constant 0. Suitable instruction and data buses as well as interrupt signals have not been wired to Minerva which is likely preventing the core and verification from functioning properly
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- 25/08/2020: Interrupts have been hardwired to zero and instruction/data buses attached to the Minerva core; however, running the verification quickly exhausts available memory on a machine with 32G RAM. Possible culprit: huge number of `Assume` statements on memory values
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## License
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See [LICENSE](./LICENSE)
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