51 lines
1.8 KiB
Python
51 lines
1.8 KiB
Python
from nmigen import *
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class rvfi_insn_general(Elaboratable):
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def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
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self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
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self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
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self.rvfi_valid = Signal(1)
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self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
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self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
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self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
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self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
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self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
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self.spec_valid = Signal(1)
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self.spec_trap = Signal(1)
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self.spec_rs1_addr = Signal(5)
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self.spec_rs2_addr = Signal(5)
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self.spec_rd_addr = Signal(5)
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self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
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self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
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self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
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self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
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self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
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self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
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def ports(self):
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input_ports = [
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self.rvfi_valid,
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self.rvfi_insn,
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self.rvfi_pc_rdata,
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self.rvfi_rs1_rdata,
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self.rvfi_rs2_rdata,
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self.rvfi_mem_rdata
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]
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output_ports = [
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self.spec_valid,
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self.spec_trap,
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self.spec_rs1_addr,
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self.spec_rs2_addr,
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self.spec_rd_addr,
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self.spec_rd_wdata,
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self.spec_pc_wdata,
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self.spec_mem_addr,
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self.spec_mem_rmask,
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self.spec_mem_wmask,
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self.spec_mem_wdata
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]
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return input_ports + output_ports
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def elaborate(self, platform):
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m = Module()
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return m
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