26 lines
894 B
Python
26 lines
894 B
Python
from nmigen import *
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from nmigen.test.utils import *
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from ..core import *
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from ....checks.pc_fwd_check import *
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class PcFwdSpec(Elaboratable):
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def elaborate(self, platform):
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m = Module()
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m.submodules.cpu = cpu = Minerva(with_rvfi=True)
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m.submodules.pc_fwd_spec = pc_fwd_spec = PcFwdCheck(RISCV_FORMAL_XLEN=32, rvformal_addr_valid=lambda x:Const(1))
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m.d.comb += pc_fwd_spec.reset.eq(0)
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m.d.comb += pc_fwd_spec.check.eq(1)
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m.d.comb += pc_fwd_spec.rvfi_valid.eq(cpu.rvfi.valid)
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m.d.comb += pc_fwd_spec.rvfi_order.eq(cpu.rvfi.order)
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m.d.comb += pc_fwd_spec.rvfi_pc_rdata.eq(cpu.rvfi.pc_rdata)
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m.d.comb += pc_fwd_spec.rvfi_pc_wdata.eq(cpu.rvfi.pc_wdata)
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return m
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class PcFwdTestCase(FHDLTestCase):
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def verify(self):
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self.assertFormal(PcFwdSpec(), mode="bmc", depth=12, engine="smtbmc --nopresat")
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