1670 lines
75 KiB
Python
1670 lines
75 KiB
Python
from nmigen import *
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from nmigen.test.utils import *
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from ..core import *
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from ....checks.insn_check import *
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from ....insns.insn_lui import *
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from ....insns.insn_auipc import *
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from ....insns.insn_jal import *
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from ....insns.insn_jalr import *
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from ....insns.insn_beq import *
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from ....insns.insn_bne import *
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from ....insns.insn_blt import *
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from ....insns.insn_bge import *
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from ....insns.insn_bltu import *
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from ....insns.insn_bgeu import *
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from ....insns.insn_lb import *
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from ....insns.insn_lh import *
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from ....insns.insn_lw import *
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from ....insns.insn_lbu import *
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from ....insns.insn_lhu import *
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from ....insns.insn_sb import *
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from ....insns.insn_sh import *
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from ....insns.insn_sw import *
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from ....insns.insn_addi import *
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from ....insns.insn_slti import *
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from ....insns.insn_sltiu import *
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from ....insns.insn_xori import *
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from ....insns.insn_ori import *
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from ....insns.insn_andi import *
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from ....insns.insn_slli import *
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from ....insns.insn_srli import *
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from ....insns.insn_srai import *
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from ....insns.insn_add import *
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from ....insns.insn_sub import *
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from ....insns.insn_sll import *
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from ....insns.insn_slt import *
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from ....insns.insn_sltu import *
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from ....insns.insn_xor import *
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from ....insns.insn_srl import *
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from ....insns.insn_sra import *
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from ....insns.insn_or import *
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from ....insns.insn_and import *
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class LuiSpec(Elaboratable):
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def elaborate(self, platform):
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m = Module()
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m.submodules.cpu = cpu = Minerva(with_rvfi=True)
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m.submodules.insn_spec = insn_spec = InsnCheck(RISCV_FORMAL_ILEN=32,
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RISCV_FORMAL_XLEN=32,
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RISCV_FORMAL_CSR_MISA=False,
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RISCV_FORMAL_COMPRESSED=False,
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RISCV_FORMAL_ALIGNED_MEM=False,
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insn_model=InsnLui,
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rvformal_addr_valid=lambda x:Const(1))
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m.d.comb += insn_spec.reset.eq(0)
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m.d.comb += insn_spec.check.eq(1)
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m.d.comb += insn_spec.rvfi_valid.eq(cpu.rvfi.valid)
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m.d.comb += insn_spec.rvfi_order.eq(cpu.rvfi.order)
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m.d.comb += insn_spec.rvfi_insn.eq(cpu.rvfi.insn)
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m.d.comb += insn_spec.rvfi_trap.eq(cpu.rvfi.trap)
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m.d.comb += insn_spec.rvfi_halt.eq(cpu.rvfi.halt)
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m.d.comb += insn_spec.rvfi_intr.eq(cpu.rvfi.intr)
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m.d.comb += insn_spec.rvfi_mode.eq(cpu.rvfi.mode)
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m.d.comb += insn_spec.rvfi_ixl.eq(cpu.rvfi.ixl)
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m.d.comb += insn_spec.rvfi_rs1_addr.eq(cpu.rvfi.rs1_addr)
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m.d.comb += insn_spec.rvfi_rs2_addr.eq(cpu.rvfi.rs2_addr)
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m.d.comb += insn_spec.rvfi_rs1_rdata.eq(cpu.rvfi.rs1_rdata)
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m.d.comb += insn_spec.rvfi_rs2_rdata.eq(cpu.rvfi.rs2_rdata)
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m.d.comb += insn_spec.rvfi_rd_addr.eq(cpu.rvfi.rd_addr)
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m.d.comb += insn_spec.rvfi_rd_wdata.eq(cpu.rvfi.rd_wdata)
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m.d.comb += insn_spec.rvfi_pc_rdata.eq(cpu.rvfi.pc_rdata)
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m.d.comb += insn_spec.rvfi_pc_wdata.eq(cpu.rvfi.pc_wdata)
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m.d.comb += insn_spec.rvfi_mem_addr.eq(cpu.rvfi.mem_addr)
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m.d.comb += insn_spec.rvfi_mem_rmask.eq(cpu.rvfi.mem_rmask)
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m.d.comb += insn_spec.rvfi_mem_wmask.eq(cpu.rvfi.mem_wmask)
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m.d.comb += insn_spec.rvfi_mem_rdata.eq(cpu.rvfi.mem_rdata)
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m.d.comb += insn_spec.rvfi_mem_wdata.eq(cpu.rvfi.mem_wdata)
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return m
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class LuiTestCase(FHDLTestCase):
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def verify(self):
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self.assertFormal(LuiSpec(), mode="bmc", depth=12, engine="smtbmc --nopresat")
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class AuipcSpec(Elaboratable):
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def elaborate(self, platform):
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m = Module()
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m.submodules.cpu = cpu = Minerva(with_rvfi=True)
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m.submodules.insn_spec = insn_spec = InsnCheck(RISCV_FORMAL_ILEN=32,
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RISCV_FORMAL_XLEN=32,
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RISCV_FORMAL_CSR_MISA=False,
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RISCV_FORMAL_COMPRESSED=False,
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RISCV_FORMAL_ALIGNED_MEM=False,
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insn_model=InsnAuipc,
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rvformal_addr_valid=lambda x:Const(1))
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m.d.comb += insn_spec.reset.eq(0)
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m.d.comb += insn_spec.check.eq(1)
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m.d.comb += insn_spec.rvfi_valid.eq(cpu.rvfi.valid)
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m.d.comb += insn_spec.rvfi_order.eq(cpu.rvfi.order)
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m.d.comb += insn_spec.rvfi_insn.eq(cpu.rvfi.insn)
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m.d.comb += insn_spec.rvfi_trap.eq(cpu.rvfi.trap)
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m.d.comb += insn_spec.rvfi_halt.eq(cpu.rvfi.halt)
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m.d.comb += insn_spec.rvfi_intr.eq(cpu.rvfi.intr)
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m.d.comb += insn_spec.rvfi_mode.eq(cpu.rvfi.mode)
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m.d.comb += insn_spec.rvfi_ixl.eq(cpu.rvfi.ixl)
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m.d.comb += insn_spec.rvfi_rs1_addr.eq(cpu.rvfi.rs1_addr)
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m.d.comb += insn_spec.rvfi_rs2_addr.eq(cpu.rvfi.rs2_addr)
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m.d.comb += insn_spec.rvfi_rs1_rdata.eq(cpu.rvfi.rs1_rdata)
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m.d.comb += insn_spec.rvfi_rs2_rdata.eq(cpu.rvfi.rs2_rdata)
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m.d.comb += insn_spec.rvfi_rd_addr.eq(cpu.rvfi.rd_addr)
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m.d.comb += insn_spec.rvfi_rd_wdata.eq(cpu.rvfi.rd_wdata)
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m.d.comb += insn_spec.rvfi_pc_rdata.eq(cpu.rvfi.pc_rdata)
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m.d.comb += insn_spec.rvfi_pc_wdata.eq(cpu.rvfi.pc_wdata)
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m.d.comb += insn_spec.rvfi_mem_addr.eq(cpu.rvfi.mem_addr)
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m.d.comb += insn_spec.rvfi_mem_rmask.eq(cpu.rvfi.mem_rmask)
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m.d.comb += insn_spec.rvfi_mem_wmask.eq(cpu.rvfi.mem_wmask)
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m.d.comb += insn_spec.rvfi_mem_rdata.eq(cpu.rvfi.mem_rdata)
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m.d.comb += insn_spec.rvfi_mem_wdata.eq(cpu.rvfi.mem_wdata)
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return m
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class AuipcTestCase(FHDLTestCase):
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def verify(self):
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self.assertFormal(AuipcSpec(), mode="bmc", depth=12, engine="smtbmc --nopresat")
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class JalSpec(Elaboratable):
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def elaborate(self, platform):
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m = Module()
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m.submodules.cpu = cpu = Minerva(with_rvfi=True)
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m.submodules.insn_spec = insn_spec = InsnCheck(RISCV_FORMAL_ILEN=32,
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RISCV_FORMAL_XLEN=32,
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RISCV_FORMAL_CSR_MISA=False,
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RISCV_FORMAL_COMPRESSED=False,
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RISCV_FORMAL_ALIGNED_MEM=False,
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insn_model=InsnJal,
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rvformal_addr_valid=lambda x:Const(1))
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m.d.comb += insn_spec.reset.eq(0)
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m.d.comb += insn_spec.check.eq(1)
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m.d.comb += insn_spec.rvfi_valid.eq(cpu.rvfi.valid)
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m.d.comb += insn_spec.rvfi_order.eq(cpu.rvfi.order)
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m.d.comb += insn_spec.rvfi_insn.eq(cpu.rvfi.insn)
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m.d.comb += insn_spec.rvfi_trap.eq(cpu.rvfi.trap)
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m.d.comb += insn_spec.rvfi_halt.eq(cpu.rvfi.halt)
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m.d.comb += insn_spec.rvfi_intr.eq(cpu.rvfi.intr)
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m.d.comb += insn_spec.rvfi_mode.eq(cpu.rvfi.mode)
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m.d.comb += insn_spec.rvfi_ixl.eq(cpu.rvfi.ixl)
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m.d.comb += insn_spec.rvfi_rs1_addr.eq(cpu.rvfi.rs1_addr)
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m.d.comb += insn_spec.rvfi_rs2_addr.eq(cpu.rvfi.rs2_addr)
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m.d.comb += insn_spec.rvfi_rs1_rdata.eq(cpu.rvfi.rs1_rdata)
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m.d.comb += insn_spec.rvfi_rs2_rdata.eq(cpu.rvfi.rs2_rdata)
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m.d.comb += insn_spec.rvfi_rd_addr.eq(cpu.rvfi.rd_addr)
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m.d.comb += insn_spec.rvfi_rd_wdata.eq(cpu.rvfi.rd_wdata)
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m.d.comb += insn_spec.rvfi_pc_rdata.eq(cpu.rvfi.pc_rdata)
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m.d.comb += insn_spec.rvfi_pc_wdata.eq(cpu.rvfi.pc_wdata)
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m.d.comb += insn_spec.rvfi_mem_addr.eq(cpu.rvfi.mem_addr)
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m.d.comb += insn_spec.rvfi_mem_rmask.eq(cpu.rvfi.mem_rmask)
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m.d.comb += insn_spec.rvfi_mem_wmask.eq(cpu.rvfi.mem_wmask)
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m.d.comb += insn_spec.rvfi_mem_rdata.eq(cpu.rvfi.mem_rdata)
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m.d.comb += insn_spec.rvfi_mem_wdata.eq(cpu.rvfi.mem_wdata)
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return m
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class JalTestCase(FHDLTestCase):
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def verify(self):
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self.assertFormal(JalSpec(), mode="bmc", depth=12, engine="smtbmc --nopresat")
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class JalrSpec(Elaboratable):
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def elaborate(self, platform):
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m = Module()
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m.submodules.cpu = cpu = Minerva(with_rvfi=True)
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m.submodules.insn_spec = insn_spec = InsnCheck(RISCV_FORMAL_ILEN=32,
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RISCV_FORMAL_XLEN=32,
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RISCV_FORMAL_CSR_MISA=False,
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RISCV_FORMAL_COMPRESSED=False,
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RISCV_FORMAL_ALIGNED_MEM=False,
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insn_model=InsnJalr,
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rvformal_addr_valid=lambda x:Const(1))
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m.d.comb += insn_spec.reset.eq(0)
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m.d.comb += insn_spec.check.eq(1)
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m.d.comb += insn_spec.rvfi_valid.eq(cpu.rvfi.valid)
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m.d.comb += insn_spec.rvfi_order.eq(cpu.rvfi.order)
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m.d.comb += insn_spec.rvfi_insn.eq(cpu.rvfi.insn)
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m.d.comb += insn_spec.rvfi_trap.eq(cpu.rvfi.trap)
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m.d.comb += insn_spec.rvfi_halt.eq(cpu.rvfi.halt)
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m.d.comb += insn_spec.rvfi_intr.eq(cpu.rvfi.intr)
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m.d.comb += insn_spec.rvfi_mode.eq(cpu.rvfi.mode)
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m.d.comb += insn_spec.rvfi_ixl.eq(cpu.rvfi.ixl)
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m.d.comb += insn_spec.rvfi_rs1_addr.eq(cpu.rvfi.rs1_addr)
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m.d.comb += insn_spec.rvfi_rs2_addr.eq(cpu.rvfi.rs2_addr)
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m.d.comb += insn_spec.rvfi_rs1_rdata.eq(cpu.rvfi.rs1_rdata)
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m.d.comb += insn_spec.rvfi_rs2_rdata.eq(cpu.rvfi.rs2_rdata)
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m.d.comb += insn_spec.rvfi_rd_addr.eq(cpu.rvfi.rd_addr)
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m.d.comb += insn_spec.rvfi_rd_wdata.eq(cpu.rvfi.rd_wdata)
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m.d.comb += insn_spec.rvfi_pc_rdata.eq(cpu.rvfi.pc_rdata)
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m.d.comb += insn_spec.rvfi_pc_wdata.eq(cpu.rvfi.pc_wdata)
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m.d.comb += insn_spec.rvfi_mem_addr.eq(cpu.rvfi.mem_addr)
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m.d.comb += insn_spec.rvfi_mem_rmask.eq(cpu.rvfi.mem_rmask)
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m.d.comb += insn_spec.rvfi_mem_wmask.eq(cpu.rvfi.mem_wmask)
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m.d.comb += insn_spec.rvfi_mem_rdata.eq(cpu.rvfi.mem_rdata)
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m.d.comb += insn_spec.rvfi_mem_wdata.eq(cpu.rvfi.mem_wdata)
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return m
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class JalrTestCase(FHDLTestCase):
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def verify(self):
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self.assertFormal(JalrSpec(), mode="bmc", depth=12, engine="smtbmc --nopresat")
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class BeqSpec(Elaboratable):
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def elaborate(self, platform):
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m = Module()
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m.submodules.cpu = cpu = Minerva(with_rvfi=True)
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m.submodules.insn_spec = insn_spec = InsnCheck(RISCV_FORMAL_ILEN=32,
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RISCV_FORMAL_XLEN=32,
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RISCV_FORMAL_CSR_MISA=False,
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RISCV_FORMAL_COMPRESSED=False,
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RISCV_FORMAL_ALIGNED_MEM=False,
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insn_model=InsnBeq,
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rvformal_addr_valid=lambda x:Const(1))
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m.d.comb += insn_spec.reset.eq(0)
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m.d.comb += insn_spec.check.eq(1)
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m.d.comb += insn_spec.rvfi_valid.eq(cpu.rvfi.valid)
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m.d.comb += insn_spec.rvfi_order.eq(cpu.rvfi.order)
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m.d.comb += insn_spec.rvfi_insn.eq(cpu.rvfi.insn)
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m.d.comb += insn_spec.rvfi_trap.eq(cpu.rvfi.trap)
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m.d.comb += insn_spec.rvfi_halt.eq(cpu.rvfi.halt)
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m.d.comb += insn_spec.rvfi_intr.eq(cpu.rvfi.intr)
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m.d.comb += insn_spec.rvfi_mode.eq(cpu.rvfi.mode)
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m.d.comb += insn_spec.rvfi_ixl.eq(cpu.rvfi.ixl)
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m.d.comb += insn_spec.rvfi_rs1_addr.eq(cpu.rvfi.rs1_addr)
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m.d.comb += insn_spec.rvfi_rs2_addr.eq(cpu.rvfi.rs2_addr)
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m.d.comb += insn_spec.rvfi_rs1_rdata.eq(cpu.rvfi.rs1_rdata)
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m.d.comb += insn_spec.rvfi_rs2_rdata.eq(cpu.rvfi.rs2_rdata)
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m.d.comb += insn_spec.rvfi_rd_addr.eq(cpu.rvfi.rd_addr)
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m.d.comb += insn_spec.rvfi_rd_wdata.eq(cpu.rvfi.rd_wdata)
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m.d.comb += insn_spec.rvfi_pc_rdata.eq(cpu.rvfi.pc_rdata)
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m.d.comb += insn_spec.rvfi_pc_wdata.eq(cpu.rvfi.pc_wdata)
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m.d.comb += insn_spec.rvfi_mem_addr.eq(cpu.rvfi.mem_addr)
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m.d.comb += insn_spec.rvfi_mem_rmask.eq(cpu.rvfi.mem_rmask)
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m.d.comb += insn_spec.rvfi_mem_wmask.eq(cpu.rvfi.mem_wmask)
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m.d.comb += insn_spec.rvfi_mem_rdata.eq(cpu.rvfi.mem_rdata)
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m.d.comb += insn_spec.rvfi_mem_wdata.eq(cpu.rvfi.mem_wdata)
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return m
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class BeqTestCase(FHDLTestCase):
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def verify(self):
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self.assertFormal(BeqSpec(), mode="bmc", depth=12, engine="smtbmc --nopresat")
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class BneSpec(Elaboratable):
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def elaborate(self, platform):
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m = Module()
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m.submodules.cpu = cpu = Minerva(with_rvfi=True)
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m.submodules.insn_spec = insn_spec = InsnCheck(RISCV_FORMAL_ILEN=32,
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RISCV_FORMAL_XLEN=32,
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RISCV_FORMAL_CSR_MISA=False,
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RISCV_FORMAL_COMPRESSED=False,
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RISCV_FORMAL_ALIGNED_MEM=False,
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insn_model=InsnBne,
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rvformal_addr_valid=lambda x:Const(1))
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m.d.comb += insn_spec.reset.eq(0)
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m.d.comb += insn_spec.check.eq(1)
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m.d.comb += insn_spec.rvfi_valid.eq(cpu.rvfi.valid)
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m.d.comb += insn_spec.rvfi_order.eq(cpu.rvfi.order)
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m.d.comb += insn_spec.rvfi_insn.eq(cpu.rvfi.insn)
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m.d.comb += insn_spec.rvfi_trap.eq(cpu.rvfi.trap)
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m.d.comb += insn_spec.rvfi_halt.eq(cpu.rvfi.halt)
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m.d.comb += insn_spec.rvfi_intr.eq(cpu.rvfi.intr)
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m.d.comb += insn_spec.rvfi_mode.eq(cpu.rvfi.mode)
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m.d.comb += insn_spec.rvfi_ixl.eq(cpu.rvfi.ixl)
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m.d.comb += insn_spec.rvfi_rs1_addr.eq(cpu.rvfi.rs1_addr)
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m.d.comb += insn_spec.rvfi_rs2_addr.eq(cpu.rvfi.rs2_addr)
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m.d.comb += insn_spec.rvfi_rs1_rdata.eq(cpu.rvfi.rs1_rdata)
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m.d.comb += insn_spec.rvfi_rs2_rdata.eq(cpu.rvfi.rs2_rdata)
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m.d.comb += insn_spec.rvfi_rd_addr.eq(cpu.rvfi.rd_addr)
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m.d.comb += insn_spec.rvfi_rd_wdata.eq(cpu.rvfi.rd_wdata)
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m.d.comb += insn_spec.rvfi_pc_rdata.eq(cpu.rvfi.pc_rdata)
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m.d.comb += insn_spec.rvfi_pc_wdata.eq(cpu.rvfi.pc_wdata)
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m.d.comb += insn_spec.rvfi_mem_addr.eq(cpu.rvfi.mem_addr)
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m.d.comb += insn_spec.rvfi_mem_rmask.eq(cpu.rvfi.mem_rmask)
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m.d.comb += insn_spec.rvfi_mem_wmask.eq(cpu.rvfi.mem_wmask)
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m.d.comb += insn_spec.rvfi_mem_rdata.eq(cpu.rvfi.mem_rdata)
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m.d.comb += insn_spec.rvfi_mem_wdata.eq(cpu.rvfi.mem_wdata)
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return m
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class BneTestCase(FHDLTestCase):
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def verify(self):
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self.assertFormal(BneSpec(), mode="bmc", depth=12, engine="smtbmc --nopresat")
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class BltSpec(Elaboratable):
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def elaborate(self, platform):
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m = Module()
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m.submodules.cpu = cpu = Minerva(with_rvfi=True)
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m.submodules.insn_spec = insn_spec = InsnCheck(RISCV_FORMAL_ILEN=32,
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RISCV_FORMAL_XLEN=32,
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RISCV_FORMAL_CSR_MISA=False,
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RISCV_FORMAL_COMPRESSED=False,
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RISCV_FORMAL_ALIGNED_MEM=False,
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insn_model=InsnBlt,
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rvformal_addr_valid=lambda x:Const(1))
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m.d.comb += insn_spec.reset.eq(0)
|
|
m.d.comb += insn_spec.check.eq(1)
|
|
|
|
m.d.comb += insn_spec.rvfi_valid.eq(cpu.rvfi.valid)
|
|
m.d.comb += insn_spec.rvfi_order.eq(cpu.rvfi.order)
|
|
m.d.comb += insn_spec.rvfi_insn.eq(cpu.rvfi.insn)
|
|
m.d.comb += insn_spec.rvfi_trap.eq(cpu.rvfi.trap)
|
|
m.d.comb += insn_spec.rvfi_halt.eq(cpu.rvfi.halt)
|
|
m.d.comb += insn_spec.rvfi_intr.eq(cpu.rvfi.intr)
|
|
m.d.comb += insn_spec.rvfi_mode.eq(cpu.rvfi.mode)
|
|
m.d.comb += insn_spec.rvfi_ixl.eq(cpu.rvfi.ixl)
|
|
m.d.comb += insn_spec.rvfi_rs1_addr.eq(cpu.rvfi.rs1_addr)
|
|
m.d.comb += insn_spec.rvfi_rs2_addr.eq(cpu.rvfi.rs2_addr)
|
|
m.d.comb += insn_spec.rvfi_rs1_rdata.eq(cpu.rvfi.rs1_rdata)
|
|
m.d.comb += insn_spec.rvfi_rs2_rdata.eq(cpu.rvfi.rs2_rdata)
|
|
m.d.comb += insn_spec.rvfi_rd_addr.eq(cpu.rvfi.rd_addr)
|
|
m.d.comb += insn_spec.rvfi_rd_wdata.eq(cpu.rvfi.rd_wdata)
|
|
m.d.comb += insn_spec.rvfi_pc_rdata.eq(cpu.rvfi.pc_rdata)
|
|
m.d.comb += insn_spec.rvfi_pc_wdata.eq(cpu.rvfi.pc_wdata)
|
|
m.d.comb += insn_spec.rvfi_mem_addr.eq(cpu.rvfi.mem_addr)
|
|
m.d.comb += insn_spec.rvfi_mem_rmask.eq(cpu.rvfi.mem_rmask)
|
|
m.d.comb += insn_spec.rvfi_mem_wmask.eq(cpu.rvfi.mem_wmask)
|
|
m.d.comb += insn_spec.rvfi_mem_rdata.eq(cpu.rvfi.mem_rdata)
|
|
m.d.comb += insn_spec.rvfi_mem_wdata.eq(cpu.rvfi.mem_wdata)
|
|
|
|
return m
|
|
|
|
class BltTestCase(FHDLTestCase):
|
|
def verify(self):
|
|
self.assertFormal(BltSpec(), mode="bmc", depth=12, engine="smtbmc --nopresat")
|
|
|
|
class BgeSpec(Elaboratable):
|
|
def elaborate(self, platform):
|
|
m = Module()
|
|
|
|
m.submodules.cpu = cpu = Minerva(with_rvfi=True)
|
|
m.submodules.insn_spec = insn_spec = InsnCheck(RISCV_FORMAL_ILEN=32,
|
|
RISCV_FORMAL_XLEN=32,
|
|
RISCV_FORMAL_CSR_MISA=False,
|
|
RISCV_FORMAL_COMPRESSED=False,
|
|
RISCV_FORMAL_ALIGNED_MEM=False,
|
|
insn_model=InsnBge,
|
|
rvformal_addr_valid=lambda x:Const(1))
|
|
|
|
m.d.comb += insn_spec.reset.eq(0)
|
|
m.d.comb += insn_spec.check.eq(1)
|
|
|
|
m.d.comb += insn_spec.rvfi_valid.eq(cpu.rvfi.valid)
|
|
m.d.comb += insn_spec.rvfi_order.eq(cpu.rvfi.order)
|
|
m.d.comb += insn_spec.rvfi_insn.eq(cpu.rvfi.insn)
|
|
m.d.comb += insn_spec.rvfi_trap.eq(cpu.rvfi.trap)
|
|
m.d.comb += insn_spec.rvfi_halt.eq(cpu.rvfi.halt)
|
|
m.d.comb += insn_spec.rvfi_intr.eq(cpu.rvfi.intr)
|
|
m.d.comb += insn_spec.rvfi_mode.eq(cpu.rvfi.mode)
|
|
m.d.comb += insn_spec.rvfi_ixl.eq(cpu.rvfi.ixl)
|
|
m.d.comb += insn_spec.rvfi_rs1_addr.eq(cpu.rvfi.rs1_addr)
|
|
m.d.comb += insn_spec.rvfi_rs2_addr.eq(cpu.rvfi.rs2_addr)
|
|
m.d.comb += insn_spec.rvfi_rs1_rdata.eq(cpu.rvfi.rs1_rdata)
|
|
m.d.comb += insn_spec.rvfi_rs2_rdata.eq(cpu.rvfi.rs2_rdata)
|
|
m.d.comb += insn_spec.rvfi_rd_addr.eq(cpu.rvfi.rd_addr)
|
|
m.d.comb += insn_spec.rvfi_rd_wdata.eq(cpu.rvfi.rd_wdata)
|
|
m.d.comb += insn_spec.rvfi_pc_rdata.eq(cpu.rvfi.pc_rdata)
|
|
m.d.comb += insn_spec.rvfi_pc_wdata.eq(cpu.rvfi.pc_wdata)
|
|
m.d.comb += insn_spec.rvfi_mem_addr.eq(cpu.rvfi.mem_addr)
|
|
m.d.comb += insn_spec.rvfi_mem_rmask.eq(cpu.rvfi.mem_rmask)
|
|
m.d.comb += insn_spec.rvfi_mem_wmask.eq(cpu.rvfi.mem_wmask)
|
|
m.d.comb += insn_spec.rvfi_mem_rdata.eq(cpu.rvfi.mem_rdata)
|
|
m.d.comb += insn_spec.rvfi_mem_wdata.eq(cpu.rvfi.mem_wdata)
|
|
|
|
return m
|
|
|
|
class BgeTestCase(FHDLTestCase):
|
|
def verify(self):
|
|
self.assertFormal(BgeSpec(), mode="bmc", depth=12, engine="smtbmc --nopresat")
|
|
|
|
class BltuSpec(Elaboratable):
|
|
def elaborate(self, platform):
|
|
m = Module()
|
|
|
|
m.submodules.cpu = cpu = Minerva(with_rvfi=True)
|
|
m.submodules.insn_spec = insn_spec = InsnCheck(RISCV_FORMAL_ILEN=32,
|
|
RISCV_FORMAL_XLEN=32,
|
|
RISCV_FORMAL_CSR_MISA=False,
|
|
RISCV_FORMAL_COMPRESSED=False,
|
|
RISCV_FORMAL_ALIGNED_MEM=False,
|
|
insn_model=InsnBltu,
|
|
rvformal_addr_valid=lambda x:Const(1))
|
|
|
|
m.d.comb += insn_spec.reset.eq(0)
|
|
m.d.comb += insn_spec.check.eq(1)
|
|
|
|
m.d.comb += insn_spec.rvfi_valid.eq(cpu.rvfi.valid)
|
|
m.d.comb += insn_spec.rvfi_order.eq(cpu.rvfi.order)
|
|
m.d.comb += insn_spec.rvfi_insn.eq(cpu.rvfi.insn)
|
|
m.d.comb += insn_spec.rvfi_trap.eq(cpu.rvfi.trap)
|
|
m.d.comb += insn_spec.rvfi_halt.eq(cpu.rvfi.halt)
|
|
m.d.comb += insn_spec.rvfi_intr.eq(cpu.rvfi.intr)
|
|
m.d.comb += insn_spec.rvfi_mode.eq(cpu.rvfi.mode)
|
|
m.d.comb += insn_spec.rvfi_ixl.eq(cpu.rvfi.ixl)
|
|
m.d.comb += insn_spec.rvfi_rs1_addr.eq(cpu.rvfi.rs1_addr)
|
|
m.d.comb += insn_spec.rvfi_rs2_addr.eq(cpu.rvfi.rs2_addr)
|
|
m.d.comb += insn_spec.rvfi_rs1_rdata.eq(cpu.rvfi.rs1_rdata)
|
|
m.d.comb += insn_spec.rvfi_rs2_rdata.eq(cpu.rvfi.rs2_rdata)
|
|
m.d.comb += insn_spec.rvfi_rd_addr.eq(cpu.rvfi.rd_addr)
|
|
m.d.comb += insn_spec.rvfi_rd_wdata.eq(cpu.rvfi.rd_wdata)
|
|
m.d.comb += insn_spec.rvfi_pc_rdata.eq(cpu.rvfi.pc_rdata)
|
|
m.d.comb += insn_spec.rvfi_pc_wdata.eq(cpu.rvfi.pc_wdata)
|
|
m.d.comb += insn_spec.rvfi_mem_addr.eq(cpu.rvfi.mem_addr)
|
|
m.d.comb += insn_spec.rvfi_mem_rmask.eq(cpu.rvfi.mem_rmask)
|
|
m.d.comb += insn_spec.rvfi_mem_wmask.eq(cpu.rvfi.mem_wmask)
|
|
m.d.comb += insn_spec.rvfi_mem_rdata.eq(cpu.rvfi.mem_rdata)
|
|
m.d.comb += insn_spec.rvfi_mem_wdata.eq(cpu.rvfi.mem_wdata)
|
|
|
|
return m
|
|
|
|
class BltuTestCase(FHDLTestCase):
|
|
def verify(self):
|
|
self.assertFormal(BltuSpec(), mode="bmc", depth=12, engine="smtbmc --nopresat")
|
|
|
|
class BgeuSpec(Elaboratable):
|
|
def elaborate(self, platform):
|
|
m = Module()
|
|
|
|
m.submodules.cpu = cpu = Minerva(with_rvfi=True)
|
|
m.submodules.insn_spec = insn_spec = InsnCheck(RISCV_FORMAL_ILEN=32,
|
|
RISCV_FORMAL_XLEN=32,
|
|
RISCV_FORMAL_CSR_MISA=False,
|
|
RISCV_FORMAL_COMPRESSED=False,
|
|
RISCV_FORMAL_ALIGNED_MEM=False,
|
|
insn_model=InsnBgeu,
|
|
rvformal_addr_valid=lambda x:Const(1))
|
|
|
|
m.d.comb += insn_spec.reset.eq(0)
|
|
m.d.comb += insn_spec.check.eq(1)
|
|
|
|
m.d.comb += insn_spec.rvfi_valid.eq(cpu.rvfi.valid)
|
|
m.d.comb += insn_spec.rvfi_order.eq(cpu.rvfi.order)
|
|
m.d.comb += insn_spec.rvfi_insn.eq(cpu.rvfi.insn)
|
|
m.d.comb += insn_spec.rvfi_trap.eq(cpu.rvfi.trap)
|
|
m.d.comb += insn_spec.rvfi_halt.eq(cpu.rvfi.halt)
|
|
m.d.comb += insn_spec.rvfi_intr.eq(cpu.rvfi.intr)
|
|
m.d.comb += insn_spec.rvfi_mode.eq(cpu.rvfi.mode)
|
|
m.d.comb += insn_spec.rvfi_ixl.eq(cpu.rvfi.ixl)
|
|
m.d.comb += insn_spec.rvfi_rs1_addr.eq(cpu.rvfi.rs1_addr)
|
|
m.d.comb += insn_spec.rvfi_rs2_addr.eq(cpu.rvfi.rs2_addr)
|
|
m.d.comb += insn_spec.rvfi_rs1_rdata.eq(cpu.rvfi.rs1_rdata)
|
|
m.d.comb += insn_spec.rvfi_rs2_rdata.eq(cpu.rvfi.rs2_rdata)
|
|
m.d.comb += insn_spec.rvfi_rd_addr.eq(cpu.rvfi.rd_addr)
|
|
m.d.comb += insn_spec.rvfi_rd_wdata.eq(cpu.rvfi.rd_wdata)
|
|
m.d.comb += insn_spec.rvfi_pc_rdata.eq(cpu.rvfi.pc_rdata)
|
|
m.d.comb += insn_spec.rvfi_pc_wdata.eq(cpu.rvfi.pc_wdata)
|
|
m.d.comb += insn_spec.rvfi_mem_addr.eq(cpu.rvfi.mem_addr)
|
|
m.d.comb += insn_spec.rvfi_mem_rmask.eq(cpu.rvfi.mem_rmask)
|
|
m.d.comb += insn_spec.rvfi_mem_wmask.eq(cpu.rvfi.mem_wmask)
|
|
m.d.comb += insn_spec.rvfi_mem_rdata.eq(cpu.rvfi.mem_rdata)
|
|
m.d.comb += insn_spec.rvfi_mem_wdata.eq(cpu.rvfi.mem_wdata)
|
|
|
|
return m
|
|
|
|
class BgeuTestCase(FHDLTestCase):
|
|
def verify(self):
|
|
self.assertFormal(BgeuSpec(), mode="bmc", depth=12, engine="smtbmc --nopresat")
|
|
|
|
class LbSpec(Elaboratable):
|
|
def elaborate(self, platform):
|
|
m = Module()
|
|
|
|
m.submodules.cpu = cpu = Minerva(with_rvfi=True)
|
|
m.submodules.insn_spec = insn_spec = InsnCheck(RISCV_FORMAL_ILEN=32,
|
|
RISCV_FORMAL_XLEN=32,
|
|
RISCV_FORMAL_CSR_MISA=False,
|
|
RISCV_FORMAL_COMPRESSED=False,
|
|
RISCV_FORMAL_ALIGNED_MEM=False,
|
|
insn_model=InsnLb,
|
|
rvformal_addr_valid=lambda x:Const(1))
|
|
|
|
m.d.comb += insn_spec.reset.eq(0)
|
|
m.d.comb += insn_spec.check.eq(1)
|
|
|
|
m.d.comb += insn_spec.rvfi_valid.eq(cpu.rvfi.valid)
|
|
m.d.comb += insn_spec.rvfi_order.eq(cpu.rvfi.order)
|
|
m.d.comb += insn_spec.rvfi_insn.eq(cpu.rvfi.insn)
|
|
m.d.comb += insn_spec.rvfi_trap.eq(cpu.rvfi.trap)
|
|
m.d.comb += insn_spec.rvfi_halt.eq(cpu.rvfi.halt)
|
|
m.d.comb += insn_spec.rvfi_intr.eq(cpu.rvfi.intr)
|
|
m.d.comb += insn_spec.rvfi_mode.eq(cpu.rvfi.mode)
|
|
m.d.comb += insn_spec.rvfi_ixl.eq(cpu.rvfi.ixl)
|
|
m.d.comb += insn_spec.rvfi_rs1_addr.eq(cpu.rvfi.rs1_addr)
|
|
m.d.comb += insn_spec.rvfi_rs2_addr.eq(cpu.rvfi.rs2_addr)
|
|
m.d.comb += insn_spec.rvfi_rs1_rdata.eq(cpu.rvfi.rs1_rdata)
|
|
m.d.comb += insn_spec.rvfi_rs2_rdata.eq(cpu.rvfi.rs2_rdata)
|
|
m.d.comb += insn_spec.rvfi_rd_addr.eq(cpu.rvfi.rd_addr)
|
|
m.d.comb += insn_spec.rvfi_rd_wdata.eq(cpu.rvfi.rd_wdata)
|
|
m.d.comb += insn_spec.rvfi_pc_rdata.eq(cpu.rvfi.pc_rdata)
|
|
m.d.comb += insn_spec.rvfi_pc_wdata.eq(cpu.rvfi.pc_wdata)
|
|
m.d.comb += insn_spec.rvfi_mem_addr.eq(cpu.rvfi.mem_addr)
|
|
m.d.comb += insn_spec.rvfi_mem_rmask.eq(cpu.rvfi.mem_rmask)
|
|
m.d.comb += insn_spec.rvfi_mem_wmask.eq(cpu.rvfi.mem_wmask)
|
|
m.d.comb += insn_spec.rvfi_mem_rdata.eq(cpu.rvfi.mem_rdata)
|
|
m.d.comb += insn_spec.rvfi_mem_wdata.eq(cpu.rvfi.mem_wdata)
|
|
|
|
return m
|
|
|
|
class LbTestCase(FHDLTestCase):
|
|
def verify(self):
|
|
self.assertFormal(LbSpec(), mode="bmc", depth=12, engine="smtbmc --nopresat")
|
|
|
|
class LhSpec(Elaboratable):
|
|
def elaborate(self, platform):
|
|
m = Module()
|
|
|
|
m.submodules.cpu = cpu = Minerva(with_rvfi=True)
|
|
m.submodules.insn_spec = insn_spec = InsnCheck(RISCV_FORMAL_ILEN=32,
|
|
RISCV_FORMAL_XLEN=32,
|
|
RISCV_FORMAL_CSR_MISA=False,
|
|
RISCV_FORMAL_COMPRESSED=False,
|
|
RISCV_FORMAL_ALIGNED_MEM=False,
|
|
insn_model=InsnLh,
|
|
rvformal_addr_valid=lambda x:Const(1))
|
|
|
|
m.d.comb += insn_spec.reset.eq(0)
|
|
m.d.comb += insn_spec.check.eq(1)
|
|
|
|
m.d.comb += insn_spec.rvfi_valid.eq(cpu.rvfi.valid)
|
|
m.d.comb += insn_spec.rvfi_order.eq(cpu.rvfi.order)
|
|
m.d.comb += insn_spec.rvfi_insn.eq(cpu.rvfi.insn)
|
|
m.d.comb += insn_spec.rvfi_trap.eq(cpu.rvfi.trap)
|
|
m.d.comb += insn_spec.rvfi_halt.eq(cpu.rvfi.halt)
|
|
m.d.comb += insn_spec.rvfi_intr.eq(cpu.rvfi.intr)
|
|
m.d.comb += insn_spec.rvfi_mode.eq(cpu.rvfi.mode)
|
|
m.d.comb += insn_spec.rvfi_ixl.eq(cpu.rvfi.ixl)
|
|
m.d.comb += insn_spec.rvfi_rs1_addr.eq(cpu.rvfi.rs1_addr)
|
|
m.d.comb += insn_spec.rvfi_rs2_addr.eq(cpu.rvfi.rs2_addr)
|
|
m.d.comb += insn_spec.rvfi_rs1_rdata.eq(cpu.rvfi.rs1_rdata)
|
|
m.d.comb += insn_spec.rvfi_rs2_rdata.eq(cpu.rvfi.rs2_rdata)
|
|
m.d.comb += insn_spec.rvfi_rd_addr.eq(cpu.rvfi.rd_addr)
|
|
m.d.comb += insn_spec.rvfi_rd_wdata.eq(cpu.rvfi.rd_wdata)
|
|
m.d.comb += insn_spec.rvfi_pc_rdata.eq(cpu.rvfi.pc_rdata)
|
|
m.d.comb += insn_spec.rvfi_pc_wdata.eq(cpu.rvfi.pc_wdata)
|
|
m.d.comb += insn_spec.rvfi_mem_addr.eq(cpu.rvfi.mem_addr)
|
|
m.d.comb += insn_spec.rvfi_mem_rmask.eq(cpu.rvfi.mem_rmask)
|
|
m.d.comb += insn_spec.rvfi_mem_wmask.eq(cpu.rvfi.mem_wmask)
|
|
m.d.comb += insn_spec.rvfi_mem_rdata.eq(cpu.rvfi.mem_rdata)
|
|
m.d.comb += insn_spec.rvfi_mem_wdata.eq(cpu.rvfi.mem_wdata)
|
|
|
|
return m
|
|
|
|
class LhTestCase(FHDLTestCase):
|
|
def verify(self):
|
|
self.assertFormal(LhSpec(), mode="bmc", depth=12, engine="smtbmc --nopresat")
|
|
|
|
class LwSpec(Elaboratable):
|
|
def elaborate(self, platform):
|
|
m = Module()
|
|
|
|
m.submodules.cpu = cpu = Minerva(with_rvfi=True)
|
|
m.submodules.insn_spec = insn_spec = InsnCheck(RISCV_FORMAL_ILEN=32,
|
|
RISCV_FORMAL_XLEN=32,
|
|
RISCV_FORMAL_CSR_MISA=False,
|
|
RISCV_FORMAL_COMPRESSED=False,
|
|
RISCV_FORMAL_ALIGNED_MEM=False,
|
|
insn_model=InsnLw,
|
|
rvformal_addr_valid=lambda x:Const(1))
|
|
|
|
m.d.comb += insn_spec.reset.eq(0)
|
|
m.d.comb += insn_spec.check.eq(1)
|
|
|
|
m.d.comb += insn_spec.rvfi_valid.eq(cpu.rvfi.valid)
|
|
m.d.comb += insn_spec.rvfi_order.eq(cpu.rvfi.order)
|
|
m.d.comb += insn_spec.rvfi_insn.eq(cpu.rvfi.insn)
|
|
m.d.comb += insn_spec.rvfi_trap.eq(cpu.rvfi.trap)
|
|
m.d.comb += insn_spec.rvfi_halt.eq(cpu.rvfi.halt)
|
|
m.d.comb += insn_spec.rvfi_intr.eq(cpu.rvfi.intr)
|
|
m.d.comb += insn_spec.rvfi_mode.eq(cpu.rvfi.mode)
|
|
m.d.comb += insn_spec.rvfi_ixl.eq(cpu.rvfi.ixl)
|
|
m.d.comb += insn_spec.rvfi_rs1_addr.eq(cpu.rvfi.rs1_addr)
|
|
m.d.comb += insn_spec.rvfi_rs2_addr.eq(cpu.rvfi.rs2_addr)
|
|
m.d.comb += insn_spec.rvfi_rs1_rdata.eq(cpu.rvfi.rs1_rdata)
|
|
m.d.comb += insn_spec.rvfi_rs2_rdata.eq(cpu.rvfi.rs2_rdata)
|
|
m.d.comb += insn_spec.rvfi_rd_addr.eq(cpu.rvfi.rd_addr)
|
|
m.d.comb += insn_spec.rvfi_rd_wdata.eq(cpu.rvfi.rd_wdata)
|
|
m.d.comb += insn_spec.rvfi_pc_rdata.eq(cpu.rvfi.pc_rdata)
|
|
m.d.comb += insn_spec.rvfi_pc_wdata.eq(cpu.rvfi.pc_wdata)
|
|
m.d.comb += insn_spec.rvfi_mem_addr.eq(cpu.rvfi.mem_addr)
|
|
m.d.comb += insn_spec.rvfi_mem_rmask.eq(cpu.rvfi.mem_rmask)
|
|
m.d.comb += insn_spec.rvfi_mem_wmask.eq(cpu.rvfi.mem_wmask)
|
|
m.d.comb += insn_spec.rvfi_mem_rdata.eq(cpu.rvfi.mem_rdata)
|
|
m.d.comb += insn_spec.rvfi_mem_wdata.eq(cpu.rvfi.mem_wdata)
|
|
|
|
return m
|
|
|
|
class LwTestCase(FHDLTestCase):
|
|
def verify(self):
|
|
self.assertFormal(LwSpec(), mode="bmc", depth=12, engine="smtbmc --nopresat")
|
|
|
|
class LbuSpec(Elaboratable):
|
|
def elaborate(self, platform):
|
|
m = Module()
|
|
|
|
m.submodules.cpu = cpu = Minerva(with_rvfi=True)
|
|
m.submodules.insn_spec = insn_spec = InsnCheck(RISCV_FORMAL_ILEN=32,
|
|
RISCV_FORMAL_XLEN=32,
|
|
RISCV_FORMAL_CSR_MISA=False,
|
|
RISCV_FORMAL_COMPRESSED=False,
|
|
RISCV_FORMAL_ALIGNED_MEM=False,
|
|
insn_model=InsnLbu,
|
|
rvformal_addr_valid=lambda x:Const(1))
|
|
|
|
m.d.comb += insn_spec.reset.eq(0)
|
|
m.d.comb += insn_spec.check.eq(1)
|
|
|
|
m.d.comb += insn_spec.rvfi_valid.eq(cpu.rvfi.valid)
|
|
m.d.comb += insn_spec.rvfi_order.eq(cpu.rvfi.order)
|
|
m.d.comb += insn_spec.rvfi_insn.eq(cpu.rvfi.insn)
|
|
m.d.comb += insn_spec.rvfi_trap.eq(cpu.rvfi.trap)
|
|
m.d.comb += insn_spec.rvfi_halt.eq(cpu.rvfi.halt)
|
|
m.d.comb += insn_spec.rvfi_intr.eq(cpu.rvfi.intr)
|
|
m.d.comb += insn_spec.rvfi_mode.eq(cpu.rvfi.mode)
|
|
m.d.comb += insn_spec.rvfi_ixl.eq(cpu.rvfi.ixl)
|
|
m.d.comb += insn_spec.rvfi_rs1_addr.eq(cpu.rvfi.rs1_addr)
|
|
m.d.comb += insn_spec.rvfi_rs2_addr.eq(cpu.rvfi.rs2_addr)
|
|
m.d.comb += insn_spec.rvfi_rs1_rdata.eq(cpu.rvfi.rs1_rdata)
|
|
m.d.comb += insn_spec.rvfi_rs2_rdata.eq(cpu.rvfi.rs2_rdata)
|
|
m.d.comb += insn_spec.rvfi_rd_addr.eq(cpu.rvfi.rd_addr)
|
|
m.d.comb += insn_spec.rvfi_rd_wdata.eq(cpu.rvfi.rd_wdata)
|
|
m.d.comb += insn_spec.rvfi_pc_rdata.eq(cpu.rvfi.pc_rdata)
|
|
m.d.comb += insn_spec.rvfi_pc_wdata.eq(cpu.rvfi.pc_wdata)
|
|
m.d.comb += insn_spec.rvfi_mem_addr.eq(cpu.rvfi.mem_addr)
|
|
m.d.comb += insn_spec.rvfi_mem_rmask.eq(cpu.rvfi.mem_rmask)
|
|
m.d.comb += insn_spec.rvfi_mem_wmask.eq(cpu.rvfi.mem_wmask)
|
|
m.d.comb += insn_spec.rvfi_mem_rdata.eq(cpu.rvfi.mem_rdata)
|
|
m.d.comb += insn_spec.rvfi_mem_wdata.eq(cpu.rvfi.mem_wdata)
|
|
|
|
return m
|
|
|
|
class LbuTestCase(FHDLTestCase):
|
|
def verify(self):
|
|
self.assertFormal(LbuSpec(), mode="bmc", depth=12, engine="smtbmc --nopresat")
|
|
|
|
class LhuSpec(Elaboratable):
|
|
def elaborate(self, platform):
|
|
m = Module()
|
|
|
|
m.submodules.cpu = cpu = Minerva(with_rvfi=True)
|
|
m.submodules.insn_spec = insn_spec = InsnCheck(RISCV_FORMAL_ILEN=32,
|
|
RISCV_FORMAL_XLEN=32,
|
|
RISCV_FORMAL_CSR_MISA=False,
|
|
RISCV_FORMAL_COMPRESSED=False,
|
|
RISCV_FORMAL_ALIGNED_MEM=False,
|
|
insn_model=InsnLhu,
|
|
rvformal_addr_valid=lambda x:Const(1))
|
|
|
|
m.d.comb += insn_spec.reset.eq(0)
|
|
m.d.comb += insn_spec.check.eq(1)
|
|
|
|
m.d.comb += insn_spec.rvfi_valid.eq(cpu.rvfi.valid)
|
|
m.d.comb += insn_spec.rvfi_order.eq(cpu.rvfi.order)
|
|
m.d.comb += insn_spec.rvfi_insn.eq(cpu.rvfi.insn)
|
|
m.d.comb += insn_spec.rvfi_trap.eq(cpu.rvfi.trap)
|
|
m.d.comb += insn_spec.rvfi_halt.eq(cpu.rvfi.halt)
|
|
m.d.comb += insn_spec.rvfi_intr.eq(cpu.rvfi.intr)
|
|
m.d.comb += insn_spec.rvfi_mode.eq(cpu.rvfi.mode)
|
|
m.d.comb += insn_spec.rvfi_ixl.eq(cpu.rvfi.ixl)
|
|
m.d.comb += insn_spec.rvfi_rs1_addr.eq(cpu.rvfi.rs1_addr)
|
|
m.d.comb += insn_spec.rvfi_rs2_addr.eq(cpu.rvfi.rs2_addr)
|
|
m.d.comb += insn_spec.rvfi_rs1_rdata.eq(cpu.rvfi.rs1_rdata)
|
|
m.d.comb += insn_spec.rvfi_rs2_rdata.eq(cpu.rvfi.rs2_rdata)
|
|
m.d.comb += insn_spec.rvfi_rd_addr.eq(cpu.rvfi.rd_addr)
|
|
m.d.comb += insn_spec.rvfi_rd_wdata.eq(cpu.rvfi.rd_wdata)
|
|
m.d.comb += insn_spec.rvfi_pc_rdata.eq(cpu.rvfi.pc_rdata)
|
|
m.d.comb += insn_spec.rvfi_pc_wdata.eq(cpu.rvfi.pc_wdata)
|
|
m.d.comb += insn_spec.rvfi_mem_addr.eq(cpu.rvfi.mem_addr)
|
|
m.d.comb += insn_spec.rvfi_mem_rmask.eq(cpu.rvfi.mem_rmask)
|
|
m.d.comb += insn_spec.rvfi_mem_wmask.eq(cpu.rvfi.mem_wmask)
|
|
m.d.comb += insn_spec.rvfi_mem_rdata.eq(cpu.rvfi.mem_rdata)
|
|
m.d.comb += insn_spec.rvfi_mem_wdata.eq(cpu.rvfi.mem_wdata)
|
|
|
|
return m
|
|
|
|
class LhuTestCase(FHDLTestCase):
|
|
def verify(self):
|
|
self.assertFormal(LhuSpec(), mode="bmc", depth=12, engine="smtbmc --nopresat")
|
|
|
|
class SbSpec(Elaboratable):
|
|
def elaborate(self, platform):
|
|
m = Module()
|
|
|
|
m.submodules.cpu = cpu = Minerva(with_rvfi=True)
|
|
m.submodules.insn_spec = insn_spec = InsnCheck(RISCV_FORMAL_ILEN=32,
|
|
RISCV_FORMAL_XLEN=32,
|
|
RISCV_FORMAL_CSR_MISA=False,
|
|
RISCV_FORMAL_COMPRESSED=False,
|
|
RISCV_FORMAL_ALIGNED_MEM=False,
|
|
insn_model=InsnSb,
|
|
rvformal_addr_valid=lambda x:Const(1))
|
|
|
|
m.d.comb += insn_spec.reset.eq(0)
|
|
m.d.comb += insn_spec.check.eq(1)
|
|
|
|
m.d.comb += insn_spec.rvfi_valid.eq(cpu.rvfi.valid)
|
|
m.d.comb += insn_spec.rvfi_order.eq(cpu.rvfi.order)
|
|
m.d.comb += insn_spec.rvfi_insn.eq(cpu.rvfi.insn)
|
|
m.d.comb += insn_spec.rvfi_trap.eq(cpu.rvfi.trap)
|
|
m.d.comb += insn_spec.rvfi_halt.eq(cpu.rvfi.halt)
|
|
m.d.comb += insn_spec.rvfi_intr.eq(cpu.rvfi.intr)
|
|
m.d.comb += insn_spec.rvfi_mode.eq(cpu.rvfi.mode)
|
|
m.d.comb += insn_spec.rvfi_ixl.eq(cpu.rvfi.ixl)
|
|
m.d.comb += insn_spec.rvfi_rs1_addr.eq(cpu.rvfi.rs1_addr)
|
|
m.d.comb += insn_spec.rvfi_rs2_addr.eq(cpu.rvfi.rs2_addr)
|
|
m.d.comb += insn_spec.rvfi_rs1_rdata.eq(cpu.rvfi.rs1_rdata)
|
|
m.d.comb += insn_spec.rvfi_rs2_rdata.eq(cpu.rvfi.rs2_rdata)
|
|
m.d.comb += insn_spec.rvfi_rd_addr.eq(cpu.rvfi.rd_addr)
|
|
m.d.comb += insn_spec.rvfi_rd_wdata.eq(cpu.rvfi.rd_wdata)
|
|
m.d.comb += insn_spec.rvfi_pc_rdata.eq(cpu.rvfi.pc_rdata)
|
|
m.d.comb += insn_spec.rvfi_pc_wdata.eq(cpu.rvfi.pc_wdata)
|
|
m.d.comb += insn_spec.rvfi_mem_addr.eq(cpu.rvfi.mem_addr)
|
|
m.d.comb += insn_spec.rvfi_mem_rmask.eq(cpu.rvfi.mem_rmask)
|
|
m.d.comb += insn_spec.rvfi_mem_wmask.eq(cpu.rvfi.mem_wmask)
|
|
m.d.comb += insn_spec.rvfi_mem_rdata.eq(cpu.rvfi.mem_rdata)
|
|
m.d.comb += insn_spec.rvfi_mem_wdata.eq(cpu.rvfi.mem_wdata)
|
|
|
|
return m
|
|
|
|
class SbTestCase(FHDLTestCase):
|
|
def verify(self):
|
|
self.assertFormal(SbSpec(), mode="bmc", depth=12, engine="smtbmc --nopresat")
|
|
|
|
class ShSpec(Elaboratable):
|
|
def elaborate(self, platform):
|
|
m = Module()
|
|
|
|
m.submodules.cpu = cpu = Minerva(with_rvfi=True)
|
|
m.submodules.insn_spec = insn_spec = InsnCheck(RISCV_FORMAL_ILEN=32,
|
|
RISCV_FORMAL_XLEN=32,
|
|
RISCV_FORMAL_CSR_MISA=False,
|
|
RISCV_FORMAL_COMPRESSED=False,
|
|
RISCV_FORMAL_ALIGNED_MEM=False,
|
|
insn_model=InsnSh,
|
|
rvformal_addr_valid=lambda x:Const(1))
|
|
|
|
m.d.comb += insn_spec.reset.eq(0)
|
|
m.d.comb += insn_spec.check.eq(1)
|
|
|
|
m.d.comb += insn_spec.rvfi_valid.eq(cpu.rvfi.valid)
|
|
m.d.comb += insn_spec.rvfi_order.eq(cpu.rvfi.order)
|
|
m.d.comb += insn_spec.rvfi_insn.eq(cpu.rvfi.insn)
|
|
m.d.comb += insn_spec.rvfi_trap.eq(cpu.rvfi.trap)
|
|
m.d.comb += insn_spec.rvfi_halt.eq(cpu.rvfi.halt)
|
|
m.d.comb += insn_spec.rvfi_intr.eq(cpu.rvfi.intr)
|
|
m.d.comb += insn_spec.rvfi_mode.eq(cpu.rvfi.mode)
|
|
m.d.comb += insn_spec.rvfi_ixl.eq(cpu.rvfi.ixl)
|
|
m.d.comb += insn_spec.rvfi_rs1_addr.eq(cpu.rvfi.rs1_addr)
|
|
m.d.comb += insn_spec.rvfi_rs2_addr.eq(cpu.rvfi.rs2_addr)
|
|
m.d.comb += insn_spec.rvfi_rs1_rdata.eq(cpu.rvfi.rs1_rdata)
|
|
m.d.comb += insn_spec.rvfi_rs2_rdata.eq(cpu.rvfi.rs2_rdata)
|
|
m.d.comb += insn_spec.rvfi_rd_addr.eq(cpu.rvfi.rd_addr)
|
|
m.d.comb += insn_spec.rvfi_rd_wdata.eq(cpu.rvfi.rd_wdata)
|
|
m.d.comb += insn_spec.rvfi_pc_rdata.eq(cpu.rvfi.pc_rdata)
|
|
m.d.comb += insn_spec.rvfi_pc_wdata.eq(cpu.rvfi.pc_wdata)
|
|
m.d.comb += insn_spec.rvfi_mem_addr.eq(cpu.rvfi.mem_addr)
|
|
m.d.comb += insn_spec.rvfi_mem_rmask.eq(cpu.rvfi.mem_rmask)
|
|
m.d.comb += insn_spec.rvfi_mem_wmask.eq(cpu.rvfi.mem_wmask)
|
|
m.d.comb += insn_spec.rvfi_mem_rdata.eq(cpu.rvfi.mem_rdata)
|
|
m.d.comb += insn_spec.rvfi_mem_wdata.eq(cpu.rvfi.mem_wdata)
|
|
|
|
return m
|
|
|
|
class ShTestCase(FHDLTestCase):
|
|
def verify(self):
|
|
self.assertFormal(ShSpec(), mode="bmc", depth=12, engine="smtbmc --nopresat")
|
|
|
|
class SwSpec(Elaboratable):
|
|
def elaborate(self, platform):
|
|
m = Module()
|
|
|
|
m.submodules.cpu = cpu = Minerva(with_rvfi=True)
|
|
m.submodules.insn_spec = insn_spec = InsnCheck(RISCV_FORMAL_ILEN=32,
|
|
RISCV_FORMAL_XLEN=32,
|
|
RISCV_FORMAL_CSR_MISA=False,
|
|
RISCV_FORMAL_COMPRESSED=False,
|
|
RISCV_FORMAL_ALIGNED_MEM=False,
|
|
insn_model=InsnSw,
|
|
rvformal_addr_valid=lambda x:Const(1))
|
|
|
|
m.d.comb += insn_spec.reset.eq(0)
|
|
m.d.comb += insn_spec.check.eq(1)
|
|
|
|
m.d.comb += insn_spec.rvfi_valid.eq(cpu.rvfi.valid)
|
|
m.d.comb += insn_spec.rvfi_order.eq(cpu.rvfi.order)
|
|
m.d.comb += insn_spec.rvfi_insn.eq(cpu.rvfi.insn)
|
|
m.d.comb += insn_spec.rvfi_trap.eq(cpu.rvfi.trap)
|
|
m.d.comb += insn_spec.rvfi_halt.eq(cpu.rvfi.halt)
|
|
m.d.comb += insn_spec.rvfi_intr.eq(cpu.rvfi.intr)
|
|
m.d.comb += insn_spec.rvfi_mode.eq(cpu.rvfi.mode)
|
|
m.d.comb += insn_spec.rvfi_ixl.eq(cpu.rvfi.ixl)
|
|
m.d.comb += insn_spec.rvfi_rs1_addr.eq(cpu.rvfi.rs1_addr)
|
|
m.d.comb += insn_spec.rvfi_rs2_addr.eq(cpu.rvfi.rs2_addr)
|
|
m.d.comb += insn_spec.rvfi_rs1_rdata.eq(cpu.rvfi.rs1_rdata)
|
|
m.d.comb += insn_spec.rvfi_rs2_rdata.eq(cpu.rvfi.rs2_rdata)
|
|
m.d.comb += insn_spec.rvfi_rd_addr.eq(cpu.rvfi.rd_addr)
|
|
m.d.comb += insn_spec.rvfi_rd_wdata.eq(cpu.rvfi.rd_wdata)
|
|
m.d.comb += insn_spec.rvfi_pc_rdata.eq(cpu.rvfi.pc_rdata)
|
|
m.d.comb += insn_spec.rvfi_pc_wdata.eq(cpu.rvfi.pc_wdata)
|
|
m.d.comb += insn_spec.rvfi_mem_addr.eq(cpu.rvfi.mem_addr)
|
|
m.d.comb += insn_spec.rvfi_mem_rmask.eq(cpu.rvfi.mem_rmask)
|
|
m.d.comb += insn_spec.rvfi_mem_wmask.eq(cpu.rvfi.mem_wmask)
|
|
m.d.comb += insn_spec.rvfi_mem_rdata.eq(cpu.rvfi.mem_rdata)
|
|
m.d.comb += insn_spec.rvfi_mem_wdata.eq(cpu.rvfi.mem_wdata)
|
|
|
|
return m
|
|
|
|
class SwTestCase(FHDLTestCase):
|
|
def verify(self):
|
|
self.assertFormal(SwSpec(), mode="bmc", depth=12, engine="smtbmc --nopresat")
|
|
|
|
class AddiSpec(Elaboratable):
|
|
def elaborate(self, platform):
|
|
m = Module()
|
|
|
|
m.submodules.cpu = cpu = Minerva(with_rvfi=True)
|
|
m.submodules.insn_spec = insn_spec = InsnCheck(RISCV_FORMAL_ILEN=32,
|
|
RISCV_FORMAL_XLEN=32,
|
|
RISCV_FORMAL_CSR_MISA=False,
|
|
RISCV_FORMAL_COMPRESSED=False,
|
|
RISCV_FORMAL_ALIGNED_MEM=False,
|
|
insn_model=InsnAddi,
|
|
rvformal_addr_valid=lambda x:Const(1))
|
|
|
|
m.d.comb += insn_spec.reset.eq(0)
|
|
m.d.comb += insn_spec.check.eq(1)
|
|
|
|
m.d.comb += insn_spec.rvfi_valid.eq(cpu.rvfi.valid)
|
|
m.d.comb += insn_spec.rvfi_order.eq(cpu.rvfi.order)
|
|
m.d.comb += insn_spec.rvfi_insn.eq(cpu.rvfi.insn)
|
|
m.d.comb += insn_spec.rvfi_trap.eq(cpu.rvfi.trap)
|
|
m.d.comb += insn_spec.rvfi_halt.eq(cpu.rvfi.halt)
|
|
m.d.comb += insn_spec.rvfi_intr.eq(cpu.rvfi.intr)
|
|
m.d.comb += insn_spec.rvfi_mode.eq(cpu.rvfi.mode)
|
|
m.d.comb += insn_spec.rvfi_ixl.eq(cpu.rvfi.ixl)
|
|
m.d.comb += insn_spec.rvfi_rs1_addr.eq(cpu.rvfi.rs1_addr)
|
|
m.d.comb += insn_spec.rvfi_rs2_addr.eq(cpu.rvfi.rs2_addr)
|
|
m.d.comb += insn_spec.rvfi_rs1_rdata.eq(cpu.rvfi.rs1_rdata)
|
|
m.d.comb += insn_spec.rvfi_rs2_rdata.eq(cpu.rvfi.rs2_rdata)
|
|
m.d.comb += insn_spec.rvfi_rd_addr.eq(cpu.rvfi.rd_addr)
|
|
m.d.comb += insn_spec.rvfi_rd_wdata.eq(cpu.rvfi.rd_wdata)
|
|
m.d.comb += insn_spec.rvfi_pc_rdata.eq(cpu.rvfi.pc_rdata)
|
|
m.d.comb += insn_spec.rvfi_pc_wdata.eq(cpu.rvfi.pc_wdata)
|
|
m.d.comb += insn_spec.rvfi_mem_addr.eq(cpu.rvfi.mem_addr)
|
|
m.d.comb += insn_spec.rvfi_mem_rmask.eq(cpu.rvfi.mem_rmask)
|
|
m.d.comb += insn_spec.rvfi_mem_wmask.eq(cpu.rvfi.mem_wmask)
|
|
m.d.comb += insn_spec.rvfi_mem_rdata.eq(cpu.rvfi.mem_rdata)
|
|
m.d.comb += insn_spec.rvfi_mem_wdata.eq(cpu.rvfi.mem_wdata)
|
|
|
|
return m
|
|
|
|
class AddiTestCase(FHDLTestCase):
|
|
def verify(self):
|
|
self.assertFormal(AddiSpec(), mode="bmc", depth=12, engine="smtbmc --nopresat")
|
|
|
|
class SltiSpec(Elaboratable):
|
|
def elaborate(self, platform):
|
|
m = Module()
|
|
|
|
m.submodules.cpu = cpu = Minerva(with_rvfi=True)
|
|
m.submodules.insn_spec = insn_spec = InsnCheck(RISCV_FORMAL_ILEN=32,
|
|
RISCV_FORMAL_XLEN=32,
|
|
RISCV_FORMAL_CSR_MISA=False,
|
|
RISCV_FORMAL_COMPRESSED=False,
|
|
RISCV_FORMAL_ALIGNED_MEM=False,
|
|
insn_model=InsnSlti,
|
|
rvformal_addr_valid=lambda x:Const(1))
|
|
|
|
m.d.comb += insn_spec.reset.eq(0)
|
|
m.d.comb += insn_spec.check.eq(1)
|
|
|
|
m.d.comb += insn_spec.rvfi_valid.eq(cpu.rvfi.valid)
|
|
m.d.comb += insn_spec.rvfi_order.eq(cpu.rvfi.order)
|
|
m.d.comb += insn_spec.rvfi_insn.eq(cpu.rvfi.insn)
|
|
m.d.comb += insn_spec.rvfi_trap.eq(cpu.rvfi.trap)
|
|
m.d.comb += insn_spec.rvfi_halt.eq(cpu.rvfi.halt)
|
|
m.d.comb += insn_spec.rvfi_intr.eq(cpu.rvfi.intr)
|
|
m.d.comb += insn_spec.rvfi_mode.eq(cpu.rvfi.mode)
|
|
m.d.comb += insn_spec.rvfi_ixl.eq(cpu.rvfi.ixl)
|
|
m.d.comb += insn_spec.rvfi_rs1_addr.eq(cpu.rvfi.rs1_addr)
|
|
m.d.comb += insn_spec.rvfi_rs2_addr.eq(cpu.rvfi.rs2_addr)
|
|
m.d.comb += insn_spec.rvfi_rs1_rdata.eq(cpu.rvfi.rs1_rdata)
|
|
m.d.comb += insn_spec.rvfi_rs2_rdata.eq(cpu.rvfi.rs2_rdata)
|
|
m.d.comb += insn_spec.rvfi_rd_addr.eq(cpu.rvfi.rd_addr)
|
|
m.d.comb += insn_spec.rvfi_rd_wdata.eq(cpu.rvfi.rd_wdata)
|
|
m.d.comb += insn_spec.rvfi_pc_rdata.eq(cpu.rvfi.pc_rdata)
|
|
m.d.comb += insn_spec.rvfi_pc_wdata.eq(cpu.rvfi.pc_wdata)
|
|
m.d.comb += insn_spec.rvfi_mem_addr.eq(cpu.rvfi.mem_addr)
|
|
m.d.comb += insn_spec.rvfi_mem_rmask.eq(cpu.rvfi.mem_rmask)
|
|
m.d.comb += insn_spec.rvfi_mem_wmask.eq(cpu.rvfi.mem_wmask)
|
|
m.d.comb += insn_spec.rvfi_mem_rdata.eq(cpu.rvfi.mem_rdata)
|
|
m.d.comb += insn_spec.rvfi_mem_wdata.eq(cpu.rvfi.mem_wdata)
|
|
|
|
return m
|
|
|
|
class SltiTestCase(FHDLTestCase):
|
|
def verify(self):
|
|
self.assertFormal(SltiSpec(), mode="bmc", depth=12, engine="smtbmc --nopresat")
|
|
|
|
class SltiuSpec(Elaboratable):
|
|
def elaborate(self, platform):
|
|
m = Module()
|
|
|
|
m.submodules.cpu = cpu = Minerva(with_rvfi=True)
|
|
m.submodules.insn_spec = insn_spec = InsnCheck(RISCV_FORMAL_ILEN=32,
|
|
RISCV_FORMAL_XLEN=32,
|
|
RISCV_FORMAL_CSR_MISA=False,
|
|
RISCV_FORMAL_COMPRESSED=False,
|
|
RISCV_FORMAL_ALIGNED_MEM=False,
|
|
insn_model=InsnSltiu,
|
|
rvformal_addr_valid=lambda x:Const(1))
|
|
|
|
m.d.comb += insn_spec.reset.eq(0)
|
|
m.d.comb += insn_spec.check.eq(1)
|
|
|
|
m.d.comb += insn_spec.rvfi_valid.eq(cpu.rvfi.valid)
|
|
m.d.comb += insn_spec.rvfi_order.eq(cpu.rvfi.order)
|
|
m.d.comb += insn_spec.rvfi_insn.eq(cpu.rvfi.insn)
|
|
m.d.comb += insn_spec.rvfi_trap.eq(cpu.rvfi.trap)
|
|
m.d.comb += insn_spec.rvfi_halt.eq(cpu.rvfi.halt)
|
|
m.d.comb += insn_spec.rvfi_intr.eq(cpu.rvfi.intr)
|
|
m.d.comb += insn_spec.rvfi_mode.eq(cpu.rvfi.mode)
|
|
m.d.comb += insn_spec.rvfi_ixl.eq(cpu.rvfi.ixl)
|
|
m.d.comb += insn_spec.rvfi_rs1_addr.eq(cpu.rvfi.rs1_addr)
|
|
m.d.comb += insn_spec.rvfi_rs2_addr.eq(cpu.rvfi.rs2_addr)
|
|
m.d.comb += insn_spec.rvfi_rs1_rdata.eq(cpu.rvfi.rs1_rdata)
|
|
m.d.comb += insn_spec.rvfi_rs2_rdata.eq(cpu.rvfi.rs2_rdata)
|
|
m.d.comb += insn_spec.rvfi_rd_addr.eq(cpu.rvfi.rd_addr)
|
|
m.d.comb += insn_spec.rvfi_rd_wdata.eq(cpu.rvfi.rd_wdata)
|
|
m.d.comb += insn_spec.rvfi_pc_rdata.eq(cpu.rvfi.pc_rdata)
|
|
m.d.comb += insn_spec.rvfi_pc_wdata.eq(cpu.rvfi.pc_wdata)
|
|
m.d.comb += insn_spec.rvfi_mem_addr.eq(cpu.rvfi.mem_addr)
|
|
m.d.comb += insn_spec.rvfi_mem_rmask.eq(cpu.rvfi.mem_rmask)
|
|
m.d.comb += insn_spec.rvfi_mem_wmask.eq(cpu.rvfi.mem_wmask)
|
|
m.d.comb += insn_spec.rvfi_mem_rdata.eq(cpu.rvfi.mem_rdata)
|
|
m.d.comb += insn_spec.rvfi_mem_wdata.eq(cpu.rvfi.mem_wdata)
|
|
|
|
return m
|
|
|
|
class SltiuTestCase(FHDLTestCase):
|
|
def verify(self):
|
|
self.assertFormal(SltiuSpec(), mode="bmc", depth=12, engine="smtbmc --nopresat")
|
|
|
|
class XoriSpec(Elaboratable):
|
|
def elaborate(self, platform):
|
|
m = Module()
|
|
|
|
m.submodules.cpu = cpu = Minerva(with_rvfi=True)
|
|
m.submodules.insn_spec = insn_spec = InsnCheck(RISCV_FORMAL_ILEN=32,
|
|
RISCV_FORMAL_XLEN=32,
|
|
RISCV_FORMAL_CSR_MISA=False,
|
|
RISCV_FORMAL_COMPRESSED=False,
|
|
RISCV_FORMAL_ALIGNED_MEM=False,
|
|
insn_model=InsnXori,
|
|
rvformal_addr_valid=lambda x:Const(1))
|
|
|
|
m.d.comb += insn_spec.reset.eq(0)
|
|
m.d.comb += insn_spec.check.eq(1)
|
|
|
|
m.d.comb += insn_spec.rvfi_valid.eq(cpu.rvfi.valid)
|
|
m.d.comb += insn_spec.rvfi_order.eq(cpu.rvfi.order)
|
|
m.d.comb += insn_spec.rvfi_insn.eq(cpu.rvfi.insn)
|
|
m.d.comb += insn_spec.rvfi_trap.eq(cpu.rvfi.trap)
|
|
m.d.comb += insn_spec.rvfi_halt.eq(cpu.rvfi.halt)
|
|
m.d.comb += insn_spec.rvfi_intr.eq(cpu.rvfi.intr)
|
|
m.d.comb += insn_spec.rvfi_mode.eq(cpu.rvfi.mode)
|
|
m.d.comb += insn_spec.rvfi_ixl.eq(cpu.rvfi.ixl)
|
|
m.d.comb += insn_spec.rvfi_rs1_addr.eq(cpu.rvfi.rs1_addr)
|
|
m.d.comb += insn_spec.rvfi_rs2_addr.eq(cpu.rvfi.rs2_addr)
|
|
m.d.comb += insn_spec.rvfi_rs1_rdata.eq(cpu.rvfi.rs1_rdata)
|
|
m.d.comb += insn_spec.rvfi_rs2_rdata.eq(cpu.rvfi.rs2_rdata)
|
|
m.d.comb += insn_spec.rvfi_rd_addr.eq(cpu.rvfi.rd_addr)
|
|
m.d.comb += insn_spec.rvfi_rd_wdata.eq(cpu.rvfi.rd_wdata)
|
|
m.d.comb += insn_spec.rvfi_pc_rdata.eq(cpu.rvfi.pc_rdata)
|
|
m.d.comb += insn_spec.rvfi_pc_wdata.eq(cpu.rvfi.pc_wdata)
|
|
m.d.comb += insn_spec.rvfi_mem_addr.eq(cpu.rvfi.mem_addr)
|
|
m.d.comb += insn_spec.rvfi_mem_rmask.eq(cpu.rvfi.mem_rmask)
|
|
m.d.comb += insn_spec.rvfi_mem_wmask.eq(cpu.rvfi.mem_wmask)
|
|
m.d.comb += insn_spec.rvfi_mem_rdata.eq(cpu.rvfi.mem_rdata)
|
|
m.d.comb += insn_spec.rvfi_mem_wdata.eq(cpu.rvfi.mem_wdata)
|
|
|
|
return m
|
|
|
|
class XoriTestCase(FHDLTestCase):
|
|
def verify(self):
|
|
self.assertFormal(XoriSpec(), mode="bmc", depth=12, engine="smtbmc --nopresat")
|
|
|
|
class OriSpec(Elaboratable):
|
|
def elaborate(self, platform):
|
|
m = Module()
|
|
|
|
m.submodules.cpu = cpu = Minerva(with_rvfi=True)
|
|
m.submodules.insn_spec = insn_spec = InsnCheck(RISCV_FORMAL_ILEN=32,
|
|
RISCV_FORMAL_XLEN=32,
|
|
RISCV_FORMAL_CSR_MISA=False,
|
|
RISCV_FORMAL_COMPRESSED=False,
|
|
RISCV_FORMAL_ALIGNED_MEM=False,
|
|
insn_model=InsnOri,
|
|
rvformal_addr_valid=lambda x:Const(1))
|
|
|
|
m.d.comb += insn_spec.reset.eq(0)
|
|
m.d.comb += insn_spec.check.eq(1)
|
|
|
|
m.d.comb += insn_spec.rvfi_valid.eq(cpu.rvfi.valid)
|
|
m.d.comb += insn_spec.rvfi_order.eq(cpu.rvfi.order)
|
|
m.d.comb += insn_spec.rvfi_insn.eq(cpu.rvfi.insn)
|
|
m.d.comb += insn_spec.rvfi_trap.eq(cpu.rvfi.trap)
|
|
m.d.comb += insn_spec.rvfi_halt.eq(cpu.rvfi.halt)
|
|
m.d.comb += insn_spec.rvfi_intr.eq(cpu.rvfi.intr)
|
|
m.d.comb += insn_spec.rvfi_mode.eq(cpu.rvfi.mode)
|
|
m.d.comb += insn_spec.rvfi_ixl.eq(cpu.rvfi.ixl)
|
|
m.d.comb += insn_spec.rvfi_rs1_addr.eq(cpu.rvfi.rs1_addr)
|
|
m.d.comb += insn_spec.rvfi_rs2_addr.eq(cpu.rvfi.rs2_addr)
|
|
m.d.comb += insn_spec.rvfi_rs1_rdata.eq(cpu.rvfi.rs1_rdata)
|
|
m.d.comb += insn_spec.rvfi_rs2_rdata.eq(cpu.rvfi.rs2_rdata)
|
|
m.d.comb += insn_spec.rvfi_rd_addr.eq(cpu.rvfi.rd_addr)
|
|
m.d.comb += insn_spec.rvfi_rd_wdata.eq(cpu.rvfi.rd_wdata)
|
|
m.d.comb += insn_spec.rvfi_pc_rdata.eq(cpu.rvfi.pc_rdata)
|
|
m.d.comb += insn_spec.rvfi_pc_wdata.eq(cpu.rvfi.pc_wdata)
|
|
m.d.comb += insn_spec.rvfi_mem_addr.eq(cpu.rvfi.mem_addr)
|
|
m.d.comb += insn_spec.rvfi_mem_rmask.eq(cpu.rvfi.mem_rmask)
|
|
m.d.comb += insn_spec.rvfi_mem_wmask.eq(cpu.rvfi.mem_wmask)
|
|
m.d.comb += insn_spec.rvfi_mem_rdata.eq(cpu.rvfi.mem_rdata)
|
|
m.d.comb += insn_spec.rvfi_mem_wdata.eq(cpu.rvfi.mem_wdata)
|
|
|
|
return m
|
|
|
|
class OriTestCase(FHDLTestCase):
|
|
def verify(self):
|
|
self.assertFormal(OriSpec(), mode="bmc", depth=12, engine="smtbmc --nopresat")
|
|
|
|
class AndiSpec(Elaboratable):
|
|
def elaborate(self, platform):
|
|
m = Module()
|
|
|
|
m.submodules.cpu = cpu = Minerva(with_rvfi=True)
|
|
m.submodules.insn_spec = insn_spec = InsnCheck(RISCV_FORMAL_ILEN=32,
|
|
RISCV_FORMAL_XLEN=32,
|
|
RISCV_FORMAL_CSR_MISA=False,
|
|
RISCV_FORMAL_COMPRESSED=False,
|
|
RISCV_FORMAL_ALIGNED_MEM=False,
|
|
insn_model=InsnAndi,
|
|
rvformal_addr_valid=lambda x:Const(1))
|
|
|
|
m.d.comb += insn_spec.reset.eq(0)
|
|
m.d.comb += insn_spec.check.eq(1)
|
|
|
|
m.d.comb += insn_spec.rvfi_valid.eq(cpu.rvfi.valid)
|
|
m.d.comb += insn_spec.rvfi_order.eq(cpu.rvfi.order)
|
|
m.d.comb += insn_spec.rvfi_insn.eq(cpu.rvfi.insn)
|
|
m.d.comb += insn_spec.rvfi_trap.eq(cpu.rvfi.trap)
|
|
m.d.comb += insn_spec.rvfi_halt.eq(cpu.rvfi.halt)
|
|
m.d.comb += insn_spec.rvfi_intr.eq(cpu.rvfi.intr)
|
|
m.d.comb += insn_spec.rvfi_mode.eq(cpu.rvfi.mode)
|
|
m.d.comb += insn_spec.rvfi_ixl.eq(cpu.rvfi.ixl)
|
|
m.d.comb += insn_spec.rvfi_rs1_addr.eq(cpu.rvfi.rs1_addr)
|
|
m.d.comb += insn_spec.rvfi_rs2_addr.eq(cpu.rvfi.rs2_addr)
|
|
m.d.comb += insn_spec.rvfi_rs1_rdata.eq(cpu.rvfi.rs1_rdata)
|
|
m.d.comb += insn_spec.rvfi_rs2_rdata.eq(cpu.rvfi.rs2_rdata)
|
|
m.d.comb += insn_spec.rvfi_rd_addr.eq(cpu.rvfi.rd_addr)
|
|
m.d.comb += insn_spec.rvfi_rd_wdata.eq(cpu.rvfi.rd_wdata)
|
|
m.d.comb += insn_spec.rvfi_pc_rdata.eq(cpu.rvfi.pc_rdata)
|
|
m.d.comb += insn_spec.rvfi_pc_wdata.eq(cpu.rvfi.pc_wdata)
|
|
m.d.comb += insn_spec.rvfi_mem_addr.eq(cpu.rvfi.mem_addr)
|
|
m.d.comb += insn_spec.rvfi_mem_rmask.eq(cpu.rvfi.mem_rmask)
|
|
m.d.comb += insn_spec.rvfi_mem_wmask.eq(cpu.rvfi.mem_wmask)
|
|
m.d.comb += insn_spec.rvfi_mem_rdata.eq(cpu.rvfi.mem_rdata)
|
|
m.d.comb += insn_spec.rvfi_mem_wdata.eq(cpu.rvfi.mem_wdata)
|
|
|
|
return m
|
|
|
|
class AndiTestCase(FHDLTestCase):
|
|
def verify(self):
|
|
self.assertFormal(AndiSpec(), mode="bmc", depth=12, engine="smtbmc --nopresat")
|
|
|
|
class SlliSpec(Elaboratable):
|
|
def elaborate(self, platform):
|
|
m = Module()
|
|
|
|
m.submodules.cpu = cpu = Minerva(with_rvfi=True)
|
|
m.submodules.insn_spec = insn_spec = InsnCheck(RISCV_FORMAL_ILEN=32,
|
|
RISCV_FORMAL_XLEN=32,
|
|
RISCV_FORMAL_CSR_MISA=False,
|
|
RISCV_FORMAL_COMPRESSED=False,
|
|
RISCV_FORMAL_ALIGNED_MEM=False,
|
|
insn_model=InsnSlli,
|
|
rvformal_addr_valid=lambda x:Const(1))
|
|
|
|
m.d.comb += insn_spec.reset.eq(0)
|
|
m.d.comb += insn_spec.check.eq(1)
|
|
|
|
m.d.comb += insn_spec.rvfi_valid.eq(cpu.rvfi.valid)
|
|
m.d.comb += insn_spec.rvfi_order.eq(cpu.rvfi.order)
|
|
m.d.comb += insn_spec.rvfi_insn.eq(cpu.rvfi.insn)
|
|
m.d.comb += insn_spec.rvfi_trap.eq(cpu.rvfi.trap)
|
|
m.d.comb += insn_spec.rvfi_halt.eq(cpu.rvfi.halt)
|
|
m.d.comb += insn_spec.rvfi_intr.eq(cpu.rvfi.intr)
|
|
m.d.comb += insn_spec.rvfi_mode.eq(cpu.rvfi.mode)
|
|
m.d.comb += insn_spec.rvfi_ixl.eq(cpu.rvfi.ixl)
|
|
m.d.comb += insn_spec.rvfi_rs1_addr.eq(cpu.rvfi.rs1_addr)
|
|
m.d.comb += insn_spec.rvfi_rs2_addr.eq(cpu.rvfi.rs2_addr)
|
|
m.d.comb += insn_spec.rvfi_rs1_rdata.eq(cpu.rvfi.rs1_rdata)
|
|
m.d.comb += insn_spec.rvfi_rs2_rdata.eq(cpu.rvfi.rs2_rdata)
|
|
m.d.comb += insn_spec.rvfi_rd_addr.eq(cpu.rvfi.rd_addr)
|
|
m.d.comb += insn_spec.rvfi_rd_wdata.eq(cpu.rvfi.rd_wdata)
|
|
m.d.comb += insn_spec.rvfi_pc_rdata.eq(cpu.rvfi.pc_rdata)
|
|
m.d.comb += insn_spec.rvfi_pc_wdata.eq(cpu.rvfi.pc_wdata)
|
|
m.d.comb += insn_spec.rvfi_mem_addr.eq(cpu.rvfi.mem_addr)
|
|
m.d.comb += insn_spec.rvfi_mem_rmask.eq(cpu.rvfi.mem_rmask)
|
|
m.d.comb += insn_spec.rvfi_mem_wmask.eq(cpu.rvfi.mem_wmask)
|
|
m.d.comb += insn_spec.rvfi_mem_rdata.eq(cpu.rvfi.mem_rdata)
|
|
m.d.comb += insn_spec.rvfi_mem_wdata.eq(cpu.rvfi.mem_wdata)
|
|
|
|
return m
|
|
|
|
class SlliTestCase(FHDLTestCase):
|
|
def verify(self):
|
|
self.assertFormal(SlliSpec(), mode="bmc", depth=12, engine="smtbmc --nopresat")
|
|
|
|
class SrliSpec(Elaboratable):
|
|
def elaborate(self, platform):
|
|
m = Module()
|
|
|
|
m.submodules.cpu = cpu = Minerva(with_rvfi=True)
|
|
m.submodules.insn_spec = insn_spec = InsnCheck(RISCV_FORMAL_ILEN=32,
|
|
RISCV_FORMAL_XLEN=32,
|
|
RISCV_FORMAL_CSR_MISA=False,
|
|
RISCV_FORMAL_COMPRESSED=False,
|
|
RISCV_FORMAL_ALIGNED_MEM=False,
|
|
insn_model=InsnSrli,
|
|
rvformal_addr_valid=lambda x:Const(1))
|
|
|
|
m.d.comb += insn_spec.reset.eq(0)
|
|
m.d.comb += insn_spec.check.eq(1)
|
|
|
|
m.d.comb += insn_spec.rvfi_valid.eq(cpu.rvfi.valid)
|
|
m.d.comb += insn_spec.rvfi_order.eq(cpu.rvfi.order)
|
|
m.d.comb += insn_spec.rvfi_insn.eq(cpu.rvfi.insn)
|
|
m.d.comb += insn_spec.rvfi_trap.eq(cpu.rvfi.trap)
|
|
m.d.comb += insn_spec.rvfi_halt.eq(cpu.rvfi.halt)
|
|
m.d.comb += insn_spec.rvfi_intr.eq(cpu.rvfi.intr)
|
|
m.d.comb += insn_spec.rvfi_mode.eq(cpu.rvfi.mode)
|
|
m.d.comb += insn_spec.rvfi_ixl.eq(cpu.rvfi.ixl)
|
|
m.d.comb += insn_spec.rvfi_rs1_addr.eq(cpu.rvfi.rs1_addr)
|
|
m.d.comb += insn_spec.rvfi_rs2_addr.eq(cpu.rvfi.rs2_addr)
|
|
m.d.comb += insn_spec.rvfi_rs1_rdata.eq(cpu.rvfi.rs1_rdata)
|
|
m.d.comb += insn_spec.rvfi_rs2_rdata.eq(cpu.rvfi.rs2_rdata)
|
|
m.d.comb += insn_spec.rvfi_rd_addr.eq(cpu.rvfi.rd_addr)
|
|
m.d.comb += insn_spec.rvfi_rd_wdata.eq(cpu.rvfi.rd_wdata)
|
|
m.d.comb += insn_spec.rvfi_pc_rdata.eq(cpu.rvfi.pc_rdata)
|
|
m.d.comb += insn_spec.rvfi_pc_wdata.eq(cpu.rvfi.pc_wdata)
|
|
m.d.comb += insn_spec.rvfi_mem_addr.eq(cpu.rvfi.mem_addr)
|
|
m.d.comb += insn_spec.rvfi_mem_rmask.eq(cpu.rvfi.mem_rmask)
|
|
m.d.comb += insn_spec.rvfi_mem_wmask.eq(cpu.rvfi.mem_wmask)
|
|
m.d.comb += insn_spec.rvfi_mem_rdata.eq(cpu.rvfi.mem_rdata)
|
|
m.d.comb += insn_spec.rvfi_mem_wdata.eq(cpu.rvfi.mem_wdata)
|
|
|
|
return m
|
|
|
|
class SrliTestCase(FHDLTestCase):
|
|
def verify(self):
|
|
self.assertFormal(SrliSpec(), mode="bmc", depth=12, engine="smtbmc --nopresat")
|
|
|
|
class SraiSpec(Elaboratable):
|
|
def elaborate(self, platform):
|
|
m = Module()
|
|
|
|
m.submodules.cpu = cpu = Minerva(with_rvfi=True)
|
|
m.submodules.insn_spec = insn_spec = InsnCheck(RISCV_FORMAL_ILEN=32,
|
|
RISCV_FORMAL_XLEN=32,
|
|
RISCV_FORMAL_CSR_MISA=False,
|
|
RISCV_FORMAL_COMPRESSED=False,
|
|
RISCV_FORMAL_ALIGNED_MEM=False,
|
|
insn_model=InsnSrai,
|
|
rvformal_addr_valid=lambda x:Const(1))
|
|
|
|
m.d.comb += insn_spec.reset.eq(0)
|
|
m.d.comb += insn_spec.check.eq(1)
|
|
|
|
m.d.comb += insn_spec.rvfi_valid.eq(cpu.rvfi.valid)
|
|
m.d.comb += insn_spec.rvfi_order.eq(cpu.rvfi.order)
|
|
m.d.comb += insn_spec.rvfi_insn.eq(cpu.rvfi.insn)
|
|
m.d.comb += insn_spec.rvfi_trap.eq(cpu.rvfi.trap)
|
|
m.d.comb += insn_spec.rvfi_halt.eq(cpu.rvfi.halt)
|
|
m.d.comb += insn_spec.rvfi_intr.eq(cpu.rvfi.intr)
|
|
m.d.comb += insn_spec.rvfi_mode.eq(cpu.rvfi.mode)
|
|
m.d.comb += insn_spec.rvfi_ixl.eq(cpu.rvfi.ixl)
|
|
m.d.comb += insn_spec.rvfi_rs1_addr.eq(cpu.rvfi.rs1_addr)
|
|
m.d.comb += insn_spec.rvfi_rs2_addr.eq(cpu.rvfi.rs2_addr)
|
|
m.d.comb += insn_spec.rvfi_rs1_rdata.eq(cpu.rvfi.rs1_rdata)
|
|
m.d.comb += insn_spec.rvfi_rs2_rdata.eq(cpu.rvfi.rs2_rdata)
|
|
m.d.comb += insn_spec.rvfi_rd_addr.eq(cpu.rvfi.rd_addr)
|
|
m.d.comb += insn_spec.rvfi_rd_wdata.eq(cpu.rvfi.rd_wdata)
|
|
m.d.comb += insn_spec.rvfi_pc_rdata.eq(cpu.rvfi.pc_rdata)
|
|
m.d.comb += insn_spec.rvfi_pc_wdata.eq(cpu.rvfi.pc_wdata)
|
|
m.d.comb += insn_spec.rvfi_mem_addr.eq(cpu.rvfi.mem_addr)
|
|
m.d.comb += insn_spec.rvfi_mem_rmask.eq(cpu.rvfi.mem_rmask)
|
|
m.d.comb += insn_spec.rvfi_mem_wmask.eq(cpu.rvfi.mem_wmask)
|
|
m.d.comb += insn_spec.rvfi_mem_rdata.eq(cpu.rvfi.mem_rdata)
|
|
m.d.comb += insn_spec.rvfi_mem_wdata.eq(cpu.rvfi.mem_wdata)
|
|
|
|
return m
|
|
|
|
class SraiTestCase(FHDLTestCase):
|
|
def verify(self):
|
|
self.assertFormal(SraiSpec(), mode="bmc", depth=12, engine="smtbmc --nopresat")
|
|
|
|
class AddSpec(Elaboratable):
|
|
def elaborate(self, platform):
|
|
m = Module()
|
|
|
|
m.submodules.cpu = cpu = Minerva(with_rvfi=True)
|
|
m.submodules.insn_spec = insn_spec = InsnCheck(RISCV_FORMAL_ILEN=32,
|
|
RISCV_FORMAL_XLEN=32,
|
|
RISCV_FORMAL_CSR_MISA=False,
|
|
RISCV_FORMAL_COMPRESSED=False,
|
|
RISCV_FORMAL_ALIGNED_MEM=False,
|
|
insn_model=InsnAdd,
|
|
rvformal_addr_valid=lambda x:Const(1))
|
|
|
|
m.d.comb += insn_spec.reset.eq(0)
|
|
m.d.comb += insn_spec.check.eq(1)
|
|
|
|
m.d.comb += insn_spec.rvfi_valid.eq(cpu.rvfi.valid)
|
|
m.d.comb += insn_spec.rvfi_order.eq(cpu.rvfi.order)
|
|
m.d.comb += insn_spec.rvfi_insn.eq(cpu.rvfi.insn)
|
|
m.d.comb += insn_spec.rvfi_trap.eq(cpu.rvfi.trap)
|
|
m.d.comb += insn_spec.rvfi_halt.eq(cpu.rvfi.halt)
|
|
m.d.comb += insn_spec.rvfi_intr.eq(cpu.rvfi.intr)
|
|
m.d.comb += insn_spec.rvfi_mode.eq(cpu.rvfi.mode)
|
|
m.d.comb += insn_spec.rvfi_ixl.eq(cpu.rvfi.ixl)
|
|
m.d.comb += insn_spec.rvfi_rs1_addr.eq(cpu.rvfi.rs1_addr)
|
|
m.d.comb += insn_spec.rvfi_rs2_addr.eq(cpu.rvfi.rs2_addr)
|
|
m.d.comb += insn_spec.rvfi_rs1_rdata.eq(cpu.rvfi.rs1_rdata)
|
|
m.d.comb += insn_spec.rvfi_rs2_rdata.eq(cpu.rvfi.rs2_rdata)
|
|
m.d.comb += insn_spec.rvfi_rd_addr.eq(cpu.rvfi.rd_addr)
|
|
m.d.comb += insn_spec.rvfi_rd_wdata.eq(cpu.rvfi.rd_wdata)
|
|
m.d.comb += insn_spec.rvfi_pc_rdata.eq(cpu.rvfi.pc_rdata)
|
|
m.d.comb += insn_spec.rvfi_pc_wdata.eq(cpu.rvfi.pc_wdata)
|
|
m.d.comb += insn_spec.rvfi_mem_addr.eq(cpu.rvfi.mem_addr)
|
|
m.d.comb += insn_spec.rvfi_mem_rmask.eq(cpu.rvfi.mem_rmask)
|
|
m.d.comb += insn_spec.rvfi_mem_wmask.eq(cpu.rvfi.mem_wmask)
|
|
m.d.comb += insn_spec.rvfi_mem_rdata.eq(cpu.rvfi.mem_rdata)
|
|
m.d.comb += insn_spec.rvfi_mem_wdata.eq(cpu.rvfi.mem_wdata)
|
|
|
|
return m
|
|
|
|
class AddTestCase(FHDLTestCase):
|
|
def verify(self):
|
|
self.assertFormal(AddSpec(), mode="bmc", depth=12, engine="smtbmc --nopresat")
|
|
|
|
class SubSpec(Elaboratable):
|
|
def elaborate(self, platform):
|
|
m = Module()
|
|
|
|
m.submodules.cpu = cpu = Minerva(with_rvfi=True)
|
|
m.submodules.insn_spec = insn_spec = InsnCheck(RISCV_FORMAL_ILEN=32,
|
|
RISCV_FORMAL_XLEN=32,
|
|
RISCV_FORMAL_CSR_MISA=False,
|
|
RISCV_FORMAL_COMPRESSED=False,
|
|
RISCV_FORMAL_ALIGNED_MEM=False,
|
|
insn_model=InsnSub,
|
|
rvformal_addr_valid=lambda x:Const(1))
|
|
|
|
m.d.comb += insn_spec.reset.eq(0)
|
|
m.d.comb += insn_spec.check.eq(1)
|
|
|
|
m.d.comb += insn_spec.rvfi_valid.eq(cpu.rvfi.valid)
|
|
m.d.comb += insn_spec.rvfi_order.eq(cpu.rvfi.order)
|
|
m.d.comb += insn_spec.rvfi_insn.eq(cpu.rvfi.insn)
|
|
m.d.comb += insn_spec.rvfi_trap.eq(cpu.rvfi.trap)
|
|
m.d.comb += insn_spec.rvfi_halt.eq(cpu.rvfi.halt)
|
|
m.d.comb += insn_spec.rvfi_intr.eq(cpu.rvfi.intr)
|
|
m.d.comb += insn_spec.rvfi_mode.eq(cpu.rvfi.mode)
|
|
m.d.comb += insn_spec.rvfi_ixl.eq(cpu.rvfi.ixl)
|
|
m.d.comb += insn_spec.rvfi_rs1_addr.eq(cpu.rvfi.rs1_addr)
|
|
m.d.comb += insn_spec.rvfi_rs2_addr.eq(cpu.rvfi.rs2_addr)
|
|
m.d.comb += insn_spec.rvfi_rs1_rdata.eq(cpu.rvfi.rs1_rdata)
|
|
m.d.comb += insn_spec.rvfi_rs2_rdata.eq(cpu.rvfi.rs2_rdata)
|
|
m.d.comb += insn_spec.rvfi_rd_addr.eq(cpu.rvfi.rd_addr)
|
|
m.d.comb += insn_spec.rvfi_rd_wdata.eq(cpu.rvfi.rd_wdata)
|
|
m.d.comb += insn_spec.rvfi_pc_rdata.eq(cpu.rvfi.pc_rdata)
|
|
m.d.comb += insn_spec.rvfi_pc_wdata.eq(cpu.rvfi.pc_wdata)
|
|
m.d.comb += insn_spec.rvfi_mem_addr.eq(cpu.rvfi.mem_addr)
|
|
m.d.comb += insn_spec.rvfi_mem_rmask.eq(cpu.rvfi.mem_rmask)
|
|
m.d.comb += insn_spec.rvfi_mem_wmask.eq(cpu.rvfi.mem_wmask)
|
|
m.d.comb += insn_spec.rvfi_mem_rdata.eq(cpu.rvfi.mem_rdata)
|
|
m.d.comb += insn_spec.rvfi_mem_wdata.eq(cpu.rvfi.mem_wdata)
|
|
|
|
return m
|
|
|
|
class SubTestCase(FHDLTestCase):
|
|
def verify(self):
|
|
self.assertFormal(SubSpec(), mode="bmc", depth=12, engine="smtbmc --nopresat")
|
|
|
|
class SllSpec(Elaboratable):
|
|
def elaborate(self, platform):
|
|
m = Module()
|
|
|
|
m.submodules.cpu = cpu = Minerva(with_rvfi=True)
|
|
m.submodules.insn_spec = insn_spec = InsnCheck(RISCV_FORMAL_ILEN=32,
|
|
RISCV_FORMAL_XLEN=32,
|
|
RISCV_FORMAL_CSR_MISA=False,
|
|
RISCV_FORMAL_COMPRESSED=False,
|
|
RISCV_FORMAL_ALIGNED_MEM=False,
|
|
insn_model=InsnSll,
|
|
rvformal_addr_valid=lambda x:Const(1))
|
|
|
|
m.d.comb += insn_spec.reset.eq(0)
|
|
m.d.comb += insn_spec.check.eq(1)
|
|
|
|
m.d.comb += insn_spec.rvfi_valid.eq(cpu.rvfi.valid)
|
|
m.d.comb += insn_spec.rvfi_order.eq(cpu.rvfi.order)
|
|
m.d.comb += insn_spec.rvfi_insn.eq(cpu.rvfi.insn)
|
|
m.d.comb += insn_spec.rvfi_trap.eq(cpu.rvfi.trap)
|
|
m.d.comb += insn_spec.rvfi_halt.eq(cpu.rvfi.halt)
|
|
m.d.comb += insn_spec.rvfi_intr.eq(cpu.rvfi.intr)
|
|
m.d.comb += insn_spec.rvfi_mode.eq(cpu.rvfi.mode)
|
|
m.d.comb += insn_spec.rvfi_ixl.eq(cpu.rvfi.ixl)
|
|
m.d.comb += insn_spec.rvfi_rs1_addr.eq(cpu.rvfi.rs1_addr)
|
|
m.d.comb += insn_spec.rvfi_rs2_addr.eq(cpu.rvfi.rs2_addr)
|
|
m.d.comb += insn_spec.rvfi_rs1_rdata.eq(cpu.rvfi.rs1_rdata)
|
|
m.d.comb += insn_spec.rvfi_rs2_rdata.eq(cpu.rvfi.rs2_rdata)
|
|
m.d.comb += insn_spec.rvfi_rd_addr.eq(cpu.rvfi.rd_addr)
|
|
m.d.comb += insn_spec.rvfi_rd_wdata.eq(cpu.rvfi.rd_wdata)
|
|
m.d.comb += insn_spec.rvfi_pc_rdata.eq(cpu.rvfi.pc_rdata)
|
|
m.d.comb += insn_spec.rvfi_pc_wdata.eq(cpu.rvfi.pc_wdata)
|
|
m.d.comb += insn_spec.rvfi_mem_addr.eq(cpu.rvfi.mem_addr)
|
|
m.d.comb += insn_spec.rvfi_mem_rmask.eq(cpu.rvfi.mem_rmask)
|
|
m.d.comb += insn_spec.rvfi_mem_wmask.eq(cpu.rvfi.mem_wmask)
|
|
m.d.comb += insn_spec.rvfi_mem_rdata.eq(cpu.rvfi.mem_rdata)
|
|
m.d.comb += insn_spec.rvfi_mem_wdata.eq(cpu.rvfi.mem_wdata)
|
|
|
|
return m
|
|
|
|
class SllTestCase(FHDLTestCase):
|
|
def verify(self):
|
|
self.assertFormal(SllSpec(), mode="bmc", depth=12, engine="smtbmc --nopresat")
|
|
|
|
class SltSpec(Elaboratable):
|
|
def elaborate(self, platform):
|
|
m = Module()
|
|
|
|
m.submodules.cpu = cpu = Minerva(with_rvfi=True)
|
|
m.submodules.insn_spec = insn_spec = InsnCheck(RISCV_FORMAL_ILEN=32,
|
|
RISCV_FORMAL_XLEN=32,
|
|
RISCV_FORMAL_CSR_MISA=False,
|
|
RISCV_FORMAL_COMPRESSED=False,
|
|
RISCV_FORMAL_ALIGNED_MEM=False,
|
|
insn_model=InsnSlt,
|
|
rvformal_addr_valid=lambda x:Const(1))
|
|
|
|
m.d.comb += insn_spec.reset.eq(0)
|
|
m.d.comb += insn_spec.check.eq(1)
|
|
|
|
m.d.comb += insn_spec.rvfi_valid.eq(cpu.rvfi.valid)
|
|
m.d.comb += insn_spec.rvfi_order.eq(cpu.rvfi.order)
|
|
m.d.comb += insn_spec.rvfi_insn.eq(cpu.rvfi.insn)
|
|
m.d.comb += insn_spec.rvfi_trap.eq(cpu.rvfi.trap)
|
|
m.d.comb += insn_spec.rvfi_halt.eq(cpu.rvfi.halt)
|
|
m.d.comb += insn_spec.rvfi_intr.eq(cpu.rvfi.intr)
|
|
m.d.comb += insn_spec.rvfi_mode.eq(cpu.rvfi.mode)
|
|
m.d.comb += insn_spec.rvfi_ixl.eq(cpu.rvfi.ixl)
|
|
m.d.comb += insn_spec.rvfi_rs1_addr.eq(cpu.rvfi.rs1_addr)
|
|
m.d.comb += insn_spec.rvfi_rs2_addr.eq(cpu.rvfi.rs2_addr)
|
|
m.d.comb += insn_spec.rvfi_rs1_rdata.eq(cpu.rvfi.rs1_rdata)
|
|
m.d.comb += insn_spec.rvfi_rs2_rdata.eq(cpu.rvfi.rs2_rdata)
|
|
m.d.comb += insn_spec.rvfi_rd_addr.eq(cpu.rvfi.rd_addr)
|
|
m.d.comb += insn_spec.rvfi_rd_wdata.eq(cpu.rvfi.rd_wdata)
|
|
m.d.comb += insn_spec.rvfi_pc_rdata.eq(cpu.rvfi.pc_rdata)
|
|
m.d.comb += insn_spec.rvfi_pc_wdata.eq(cpu.rvfi.pc_wdata)
|
|
m.d.comb += insn_spec.rvfi_mem_addr.eq(cpu.rvfi.mem_addr)
|
|
m.d.comb += insn_spec.rvfi_mem_rmask.eq(cpu.rvfi.mem_rmask)
|
|
m.d.comb += insn_spec.rvfi_mem_wmask.eq(cpu.rvfi.mem_wmask)
|
|
m.d.comb += insn_spec.rvfi_mem_rdata.eq(cpu.rvfi.mem_rdata)
|
|
m.d.comb += insn_spec.rvfi_mem_wdata.eq(cpu.rvfi.mem_wdata)
|
|
|
|
return m
|
|
|
|
class SltTestCase(FHDLTestCase):
|
|
def verify(self):
|
|
self.assertFormal(SltSpec(), mode="bmc", depth=12, engine="smtbmc --nopresat")
|
|
|
|
class SltuSpec(Elaboratable):
|
|
def elaborate(self, platform):
|
|
m = Module()
|
|
|
|
m.submodules.cpu = cpu = Minerva(with_rvfi=True)
|
|
m.submodules.insn_spec = insn_spec = InsnCheck(RISCV_FORMAL_ILEN=32,
|
|
RISCV_FORMAL_XLEN=32,
|
|
RISCV_FORMAL_CSR_MISA=False,
|
|
RISCV_FORMAL_COMPRESSED=False,
|
|
RISCV_FORMAL_ALIGNED_MEM=False,
|
|
insn_model=InsnSltu,
|
|
rvformal_addr_valid=lambda x:Const(1))
|
|
|
|
m.d.comb += insn_spec.reset.eq(0)
|
|
m.d.comb += insn_spec.check.eq(1)
|
|
|
|
m.d.comb += insn_spec.rvfi_valid.eq(cpu.rvfi.valid)
|
|
m.d.comb += insn_spec.rvfi_order.eq(cpu.rvfi.order)
|
|
m.d.comb += insn_spec.rvfi_insn.eq(cpu.rvfi.insn)
|
|
m.d.comb += insn_spec.rvfi_trap.eq(cpu.rvfi.trap)
|
|
m.d.comb += insn_spec.rvfi_halt.eq(cpu.rvfi.halt)
|
|
m.d.comb += insn_spec.rvfi_intr.eq(cpu.rvfi.intr)
|
|
m.d.comb += insn_spec.rvfi_mode.eq(cpu.rvfi.mode)
|
|
m.d.comb += insn_spec.rvfi_ixl.eq(cpu.rvfi.ixl)
|
|
m.d.comb += insn_spec.rvfi_rs1_addr.eq(cpu.rvfi.rs1_addr)
|
|
m.d.comb += insn_spec.rvfi_rs2_addr.eq(cpu.rvfi.rs2_addr)
|
|
m.d.comb += insn_spec.rvfi_rs1_rdata.eq(cpu.rvfi.rs1_rdata)
|
|
m.d.comb += insn_spec.rvfi_rs2_rdata.eq(cpu.rvfi.rs2_rdata)
|
|
m.d.comb += insn_spec.rvfi_rd_addr.eq(cpu.rvfi.rd_addr)
|
|
m.d.comb += insn_spec.rvfi_rd_wdata.eq(cpu.rvfi.rd_wdata)
|
|
m.d.comb += insn_spec.rvfi_pc_rdata.eq(cpu.rvfi.pc_rdata)
|
|
m.d.comb += insn_spec.rvfi_pc_wdata.eq(cpu.rvfi.pc_wdata)
|
|
m.d.comb += insn_spec.rvfi_mem_addr.eq(cpu.rvfi.mem_addr)
|
|
m.d.comb += insn_spec.rvfi_mem_rmask.eq(cpu.rvfi.mem_rmask)
|
|
m.d.comb += insn_spec.rvfi_mem_wmask.eq(cpu.rvfi.mem_wmask)
|
|
m.d.comb += insn_spec.rvfi_mem_rdata.eq(cpu.rvfi.mem_rdata)
|
|
m.d.comb += insn_spec.rvfi_mem_wdata.eq(cpu.rvfi.mem_wdata)
|
|
|
|
return m
|
|
|
|
class SltuTestCase(FHDLTestCase):
|
|
def verify(self):
|
|
self.assertFormal(SltuSpec(), mode="bmc", depth=12, engine="smtbmc --nopresat")
|
|
|
|
class XorSpec(Elaboratable):
|
|
def elaborate(self, platform):
|
|
m = Module()
|
|
|
|
m.submodules.cpu = cpu = Minerva(with_rvfi=True)
|
|
m.submodules.insn_spec = insn_spec = InsnCheck(RISCV_FORMAL_ILEN=32,
|
|
RISCV_FORMAL_XLEN=32,
|
|
RISCV_FORMAL_CSR_MISA=False,
|
|
RISCV_FORMAL_COMPRESSED=False,
|
|
RISCV_FORMAL_ALIGNED_MEM=False,
|
|
insn_model=InsnXor,
|
|
rvformal_addr_valid=lambda x:Const(1))
|
|
|
|
m.d.comb += insn_spec.reset.eq(0)
|
|
m.d.comb += insn_spec.check.eq(1)
|
|
|
|
m.d.comb += insn_spec.rvfi_valid.eq(cpu.rvfi.valid)
|
|
m.d.comb += insn_spec.rvfi_order.eq(cpu.rvfi.order)
|
|
m.d.comb += insn_spec.rvfi_insn.eq(cpu.rvfi.insn)
|
|
m.d.comb += insn_spec.rvfi_trap.eq(cpu.rvfi.trap)
|
|
m.d.comb += insn_spec.rvfi_halt.eq(cpu.rvfi.halt)
|
|
m.d.comb += insn_spec.rvfi_intr.eq(cpu.rvfi.intr)
|
|
m.d.comb += insn_spec.rvfi_mode.eq(cpu.rvfi.mode)
|
|
m.d.comb += insn_spec.rvfi_ixl.eq(cpu.rvfi.ixl)
|
|
m.d.comb += insn_spec.rvfi_rs1_addr.eq(cpu.rvfi.rs1_addr)
|
|
m.d.comb += insn_spec.rvfi_rs2_addr.eq(cpu.rvfi.rs2_addr)
|
|
m.d.comb += insn_spec.rvfi_rs1_rdata.eq(cpu.rvfi.rs1_rdata)
|
|
m.d.comb += insn_spec.rvfi_rs2_rdata.eq(cpu.rvfi.rs2_rdata)
|
|
m.d.comb += insn_spec.rvfi_rd_addr.eq(cpu.rvfi.rd_addr)
|
|
m.d.comb += insn_spec.rvfi_rd_wdata.eq(cpu.rvfi.rd_wdata)
|
|
m.d.comb += insn_spec.rvfi_pc_rdata.eq(cpu.rvfi.pc_rdata)
|
|
m.d.comb += insn_spec.rvfi_pc_wdata.eq(cpu.rvfi.pc_wdata)
|
|
m.d.comb += insn_spec.rvfi_mem_addr.eq(cpu.rvfi.mem_addr)
|
|
m.d.comb += insn_spec.rvfi_mem_rmask.eq(cpu.rvfi.mem_rmask)
|
|
m.d.comb += insn_spec.rvfi_mem_wmask.eq(cpu.rvfi.mem_wmask)
|
|
m.d.comb += insn_spec.rvfi_mem_rdata.eq(cpu.rvfi.mem_rdata)
|
|
m.d.comb += insn_spec.rvfi_mem_wdata.eq(cpu.rvfi.mem_wdata)
|
|
|
|
return m
|
|
|
|
class XorTestCase(FHDLTestCase):
|
|
def verify(self):
|
|
self.assertFormal(XorSpec(), mode="bmc", depth=12, engine="smtbmc --nopresat")
|
|
|
|
class SrlSpec(Elaboratable):
|
|
def elaborate(self, platform):
|
|
m = Module()
|
|
|
|
m.submodules.cpu = cpu = Minerva(with_rvfi=True)
|
|
m.submodules.insn_spec = insn_spec = InsnCheck(RISCV_FORMAL_ILEN=32,
|
|
RISCV_FORMAL_XLEN=32,
|
|
RISCV_FORMAL_CSR_MISA=False,
|
|
RISCV_FORMAL_COMPRESSED=False,
|
|
RISCV_FORMAL_ALIGNED_MEM=False,
|
|
insn_model=InsnSrl,
|
|
rvformal_addr_valid=lambda x:Const(1))
|
|
|
|
m.d.comb += insn_spec.reset.eq(0)
|
|
m.d.comb += insn_spec.check.eq(1)
|
|
|
|
m.d.comb += insn_spec.rvfi_valid.eq(cpu.rvfi.valid)
|
|
m.d.comb += insn_spec.rvfi_order.eq(cpu.rvfi.order)
|
|
m.d.comb += insn_spec.rvfi_insn.eq(cpu.rvfi.insn)
|
|
m.d.comb += insn_spec.rvfi_trap.eq(cpu.rvfi.trap)
|
|
m.d.comb += insn_spec.rvfi_halt.eq(cpu.rvfi.halt)
|
|
m.d.comb += insn_spec.rvfi_intr.eq(cpu.rvfi.intr)
|
|
m.d.comb += insn_spec.rvfi_mode.eq(cpu.rvfi.mode)
|
|
m.d.comb += insn_spec.rvfi_ixl.eq(cpu.rvfi.ixl)
|
|
m.d.comb += insn_spec.rvfi_rs1_addr.eq(cpu.rvfi.rs1_addr)
|
|
m.d.comb += insn_spec.rvfi_rs2_addr.eq(cpu.rvfi.rs2_addr)
|
|
m.d.comb += insn_spec.rvfi_rs1_rdata.eq(cpu.rvfi.rs1_rdata)
|
|
m.d.comb += insn_spec.rvfi_rs2_rdata.eq(cpu.rvfi.rs2_rdata)
|
|
m.d.comb += insn_spec.rvfi_rd_addr.eq(cpu.rvfi.rd_addr)
|
|
m.d.comb += insn_spec.rvfi_rd_wdata.eq(cpu.rvfi.rd_wdata)
|
|
m.d.comb += insn_spec.rvfi_pc_rdata.eq(cpu.rvfi.pc_rdata)
|
|
m.d.comb += insn_spec.rvfi_pc_wdata.eq(cpu.rvfi.pc_wdata)
|
|
m.d.comb += insn_spec.rvfi_mem_addr.eq(cpu.rvfi.mem_addr)
|
|
m.d.comb += insn_spec.rvfi_mem_rmask.eq(cpu.rvfi.mem_rmask)
|
|
m.d.comb += insn_spec.rvfi_mem_wmask.eq(cpu.rvfi.mem_wmask)
|
|
m.d.comb += insn_spec.rvfi_mem_rdata.eq(cpu.rvfi.mem_rdata)
|
|
m.d.comb += insn_spec.rvfi_mem_wdata.eq(cpu.rvfi.mem_wdata)
|
|
|
|
return m
|
|
|
|
class SrlTestCase(FHDLTestCase):
|
|
def verify(self):
|
|
self.assertFormal(SrlSpec(), mode="bmc", depth=12, engine="smtbmc --nopresat")
|
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class SraSpec(Elaboratable):
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def elaborate(self, platform):
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m = Module()
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m.submodules.cpu = cpu = Minerva(with_rvfi=True)
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m.submodules.insn_spec = insn_spec = InsnCheck(RISCV_FORMAL_ILEN=32,
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RISCV_FORMAL_XLEN=32,
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RISCV_FORMAL_CSR_MISA=False,
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RISCV_FORMAL_COMPRESSED=False,
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RISCV_FORMAL_ALIGNED_MEM=False,
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insn_model=InsnSra,
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rvformal_addr_valid=lambda x:Const(1))
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m.d.comb += insn_spec.reset.eq(0)
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m.d.comb += insn_spec.check.eq(1)
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m.d.comb += insn_spec.rvfi_valid.eq(cpu.rvfi.valid)
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m.d.comb += insn_spec.rvfi_order.eq(cpu.rvfi.order)
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m.d.comb += insn_spec.rvfi_insn.eq(cpu.rvfi.insn)
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m.d.comb += insn_spec.rvfi_trap.eq(cpu.rvfi.trap)
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m.d.comb += insn_spec.rvfi_halt.eq(cpu.rvfi.halt)
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m.d.comb += insn_spec.rvfi_intr.eq(cpu.rvfi.intr)
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m.d.comb += insn_spec.rvfi_mode.eq(cpu.rvfi.mode)
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m.d.comb += insn_spec.rvfi_ixl.eq(cpu.rvfi.ixl)
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m.d.comb += insn_spec.rvfi_rs1_addr.eq(cpu.rvfi.rs1_addr)
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m.d.comb += insn_spec.rvfi_rs2_addr.eq(cpu.rvfi.rs2_addr)
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m.d.comb += insn_spec.rvfi_rs1_rdata.eq(cpu.rvfi.rs1_rdata)
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m.d.comb += insn_spec.rvfi_rs2_rdata.eq(cpu.rvfi.rs2_rdata)
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m.d.comb += insn_spec.rvfi_rd_addr.eq(cpu.rvfi.rd_addr)
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m.d.comb += insn_spec.rvfi_rd_wdata.eq(cpu.rvfi.rd_wdata)
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m.d.comb += insn_spec.rvfi_pc_rdata.eq(cpu.rvfi.pc_rdata)
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m.d.comb += insn_spec.rvfi_pc_wdata.eq(cpu.rvfi.pc_wdata)
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m.d.comb += insn_spec.rvfi_mem_addr.eq(cpu.rvfi.mem_addr)
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m.d.comb += insn_spec.rvfi_mem_rmask.eq(cpu.rvfi.mem_rmask)
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m.d.comb += insn_spec.rvfi_mem_wmask.eq(cpu.rvfi.mem_wmask)
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m.d.comb += insn_spec.rvfi_mem_rdata.eq(cpu.rvfi.mem_rdata)
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m.d.comb += insn_spec.rvfi_mem_wdata.eq(cpu.rvfi.mem_wdata)
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|
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return m
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|
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class SraTestCase(FHDLTestCase):
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def verify(self):
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self.assertFormal(SraSpec(), mode="bmc", depth=12, engine="smtbmc --nopresat")
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|
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class OrSpec(Elaboratable):
|
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def elaborate(self, platform):
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m = Module()
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|
|
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m.submodules.cpu = cpu = Minerva(with_rvfi=True)
|
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m.submodules.insn_spec = insn_spec = InsnCheck(RISCV_FORMAL_ILEN=32,
|
|
RISCV_FORMAL_XLEN=32,
|
|
RISCV_FORMAL_CSR_MISA=False,
|
|
RISCV_FORMAL_COMPRESSED=False,
|
|
RISCV_FORMAL_ALIGNED_MEM=False,
|
|
insn_model=InsnOr,
|
|
rvformal_addr_valid=lambda x:Const(1))
|
|
|
|
m.d.comb += insn_spec.reset.eq(0)
|
|
m.d.comb += insn_spec.check.eq(1)
|
|
|
|
m.d.comb += insn_spec.rvfi_valid.eq(cpu.rvfi.valid)
|
|
m.d.comb += insn_spec.rvfi_order.eq(cpu.rvfi.order)
|
|
m.d.comb += insn_spec.rvfi_insn.eq(cpu.rvfi.insn)
|
|
m.d.comb += insn_spec.rvfi_trap.eq(cpu.rvfi.trap)
|
|
m.d.comb += insn_spec.rvfi_halt.eq(cpu.rvfi.halt)
|
|
m.d.comb += insn_spec.rvfi_intr.eq(cpu.rvfi.intr)
|
|
m.d.comb += insn_spec.rvfi_mode.eq(cpu.rvfi.mode)
|
|
m.d.comb += insn_spec.rvfi_ixl.eq(cpu.rvfi.ixl)
|
|
m.d.comb += insn_spec.rvfi_rs1_addr.eq(cpu.rvfi.rs1_addr)
|
|
m.d.comb += insn_spec.rvfi_rs2_addr.eq(cpu.rvfi.rs2_addr)
|
|
m.d.comb += insn_spec.rvfi_rs1_rdata.eq(cpu.rvfi.rs1_rdata)
|
|
m.d.comb += insn_spec.rvfi_rs2_rdata.eq(cpu.rvfi.rs2_rdata)
|
|
m.d.comb += insn_spec.rvfi_rd_addr.eq(cpu.rvfi.rd_addr)
|
|
m.d.comb += insn_spec.rvfi_rd_wdata.eq(cpu.rvfi.rd_wdata)
|
|
m.d.comb += insn_spec.rvfi_pc_rdata.eq(cpu.rvfi.pc_rdata)
|
|
m.d.comb += insn_spec.rvfi_pc_wdata.eq(cpu.rvfi.pc_wdata)
|
|
m.d.comb += insn_spec.rvfi_mem_addr.eq(cpu.rvfi.mem_addr)
|
|
m.d.comb += insn_spec.rvfi_mem_rmask.eq(cpu.rvfi.mem_rmask)
|
|
m.d.comb += insn_spec.rvfi_mem_wmask.eq(cpu.rvfi.mem_wmask)
|
|
m.d.comb += insn_spec.rvfi_mem_rdata.eq(cpu.rvfi.mem_rdata)
|
|
m.d.comb += insn_spec.rvfi_mem_wdata.eq(cpu.rvfi.mem_wdata)
|
|
|
|
return m
|
|
|
|
class OrTestCase(FHDLTestCase):
|
|
def verify(self):
|
|
self.assertFormal(OrSpec(), mode="bmc", depth=12, engine="smtbmc --nopresat")
|
|
|
|
class AndSpec(Elaboratable):
|
|
def elaborate(self, platform):
|
|
m = Module()
|
|
|
|
m.submodules.cpu = cpu = Minerva(with_rvfi=True)
|
|
m.submodules.insn_spec = insn_spec = InsnCheck(RISCV_FORMAL_ILEN=32,
|
|
RISCV_FORMAL_XLEN=32,
|
|
RISCV_FORMAL_CSR_MISA=False,
|
|
RISCV_FORMAL_COMPRESSED=False,
|
|
RISCV_FORMAL_ALIGNED_MEM=False,
|
|
insn_model=InsnAnd,
|
|
rvformal_addr_valid=lambda x:Const(1))
|
|
|
|
m.d.comb += insn_spec.reset.eq(0)
|
|
m.d.comb += insn_spec.check.eq(1)
|
|
|
|
m.d.comb += insn_spec.rvfi_valid.eq(cpu.rvfi.valid)
|
|
m.d.comb += insn_spec.rvfi_order.eq(cpu.rvfi.order)
|
|
m.d.comb += insn_spec.rvfi_insn.eq(cpu.rvfi.insn)
|
|
m.d.comb += insn_spec.rvfi_trap.eq(cpu.rvfi.trap)
|
|
m.d.comb += insn_spec.rvfi_halt.eq(cpu.rvfi.halt)
|
|
m.d.comb += insn_spec.rvfi_intr.eq(cpu.rvfi.intr)
|
|
m.d.comb += insn_spec.rvfi_mode.eq(cpu.rvfi.mode)
|
|
m.d.comb += insn_spec.rvfi_ixl.eq(cpu.rvfi.ixl)
|
|
m.d.comb += insn_spec.rvfi_rs1_addr.eq(cpu.rvfi.rs1_addr)
|
|
m.d.comb += insn_spec.rvfi_rs2_addr.eq(cpu.rvfi.rs2_addr)
|
|
m.d.comb += insn_spec.rvfi_rs1_rdata.eq(cpu.rvfi.rs1_rdata)
|
|
m.d.comb += insn_spec.rvfi_rs2_rdata.eq(cpu.rvfi.rs2_rdata)
|
|
m.d.comb += insn_spec.rvfi_rd_addr.eq(cpu.rvfi.rd_addr)
|
|
m.d.comb += insn_spec.rvfi_rd_wdata.eq(cpu.rvfi.rd_wdata)
|
|
m.d.comb += insn_spec.rvfi_pc_rdata.eq(cpu.rvfi.pc_rdata)
|
|
m.d.comb += insn_spec.rvfi_pc_wdata.eq(cpu.rvfi.pc_wdata)
|
|
m.d.comb += insn_spec.rvfi_mem_addr.eq(cpu.rvfi.mem_addr)
|
|
m.d.comb += insn_spec.rvfi_mem_rmask.eq(cpu.rvfi.mem_rmask)
|
|
m.d.comb += insn_spec.rvfi_mem_wmask.eq(cpu.rvfi.mem_wmask)
|
|
m.d.comb += insn_spec.rvfi_mem_rdata.eq(cpu.rvfi.mem_rdata)
|
|
m.d.comb += insn_spec.rvfi_mem_wdata.eq(cpu.rvfi.mem_wdata)
|
|
|
|
return m
|
|
|
|
class AndTestCase(FHDLTestCase):
|
|
def verify(self):
|
|
self.assertFormal(AndSpec(), mode="bmc", depth=12, engine="smtbmc --nopresat")
|