120 lines
4.7 KiB
Markdown
120 lines
4.7 KiB
Markdown
# RISC-V Instructions
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## Instructions
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Below is a table of RISC-V instructions supported by the original riscv-formal framework at the time of writing, categorized by instruction type.
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| Instruction type | Instructions |
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| --- | --- |
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| R-type | ADD, ADDW, AND, DIV, DIVU, DIVUW, DIVW, MUL, MULH, MULHSU, MULHU, MULW, OR, REM, REMU, REMUW, REMW, SLL, SLLW, SLT, SLTU, SRA, SRAW, SRL, SRLW, SUB, SUBW, XOR |
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| I-type | ADDI, ADDIW, ANDI, JALR, LB, LBU, LD, LH, LHU, LW, LWU, ORI, SLTI, SLTIU, XORI |
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| I-type (shift variation) | SLLI, SLLIW, SRAI, SRAIW, SRLI, SRLIW |
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| S-type | SB, SD, SH, SW |
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| SB-type | BEQ, BGE, BGEU, BLT, BLTU, BNE |
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| U-type | AUIPC, LUI |
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| UJ-type | JAL |
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| CI-type | C\_ADD, C\_ADDI, C\_ADDIW, C\_JALR, C\_JR, C\_LI, C\_MV |
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| CI-type (SP variation) | C\_ADDI16SP |
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| CI-type (ANDI variation) | C\_ANDI |
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| CI-type (LSP variation, 32 bit version) | C\_LWSP |
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| CI-type (LSP variation, 64 bit version) | C\_LDSP |
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| CI-type (LUI variation) | C\_LUI |
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| CI-type (SLI variation) | C\_SLLI |
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| CI-type (SRI variation) | C\_SRAI, C\_SRLI |
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| CIW-type | C\_ADDI4SPN |
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| CS-type (ALU version) | C\_ADDW, C\_AND, C\_OR, C\_SUB, C\_SUBW, C\_XOR |
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| CS-type (32 bit version) | C\_SW |
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| CS-type (64 bit version) | C\_SD |
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| CSS-type (32 bit version) | C\_SWSP |
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| CSS-type (64 bit version) | C\_SDSP |
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| CB-type | C\_BEQZ, C\_BNEZ |
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| CJ-type | C\_J, C\_JAL |
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| CL-type (32 bit version) | C\_LW |
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| CL-type (64 bit version) | C\_LD |
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## Class Synopsis
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### Instructions
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Below is a list of instructions currently supported by this port of the riscv-formal framework and is expected to grow over time. The instructions are roughly grouped by instruction type but sometimes with further specializations - the hierarchy of the lists reflects the hierarchy of inheritance in the classes used to represent various instructions.
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- `Insn`: General RISC-V instruction
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- `InsnRV32IRType`: RV32I R-Type Instruction
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- `InsnAdd`: ADD instruction
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- `InsnSub`: SUB instruction
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- `InsnSll`: SLL instruction
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- `InsnSlt`: SLT instruction
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- `InsnSltu`: SLTU instruction
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- `InsnXor`: XOR instruction
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- `InsnSrl`: SRL instruction
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- `InsnSra`: SRA instruction
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- `InsnOr`: OR instruction
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- `InsnAnd`: AND instruction
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- `InsnRV32IITypeShift`: RV32I I-Type Instruction (Shift Variation)
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- `InsnSlli`: SLLI instruction
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- `InsnSrli`: SRLI instruction
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- `InsnSrai`: SRAI instruction
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- `InsnRV32IIType`: RV32I I-Type Instruction
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- `InsnJalr`: JALR instruction
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- `InsnRV32IITypeLoad`: RV32I I-Type Instruction (Load Variation)
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- `InsnLb`: LB instruction
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- `InsnLh`: LH instruction
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- `InsnLw`: LW instruction
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- `InsnLbu`: LBU instruction
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- `InsnLhu`: LHU instruction
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- `InsnRV32IITypeArith`: RV32I I-Type Instruction (Arithmetic Variation)
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- `InsnAddi`: ADDI instruction
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- `InsnSlti`: SLTI instruction
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- `InsnSltiu`: SLTIU instruction
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- `InsnXori`: XORI instruction
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- `InsnOri`: ORI instruction
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- `InsnAndi`: ANDI instruction
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- `InsnRV32ISType`: RV32I S-Type Instruction
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- `InsnSb`: SB instruction
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- `InsnSh`: SH instruction
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- `InsnSw`: SW instruction
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- `InsnRV32ISBType`: RV32I SB-Type Instruction
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- `InsnBeq`: BEQ instruction
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- `InsnBne`: BNE instruction
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- `InsnBlt`: BLT instruction
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- `InsnBge`: BGE instruction
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- `InsnBltu`: BLTU instruction
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- `InsnBgeu`: BGEU instruction
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- `InsnJal`: JAL instruction
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- `InsnRV32IUType`: RV32I U-Type Instruction
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- `InsnLui`: LUI instruction
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- `InsnAuipc`: AUIPC instruction
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- `InsnRV32MRType`: RV32M R-Type Instruction
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- `InsnMul`: MUL instruction
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- `InsnMulh`: MULH instruction
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- `InsnMulhsu`: MULHSU instruction
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- `InsnMulhu`: MULHU instruction
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- `InsnDiv`: DIV instruction
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- `InsnDivu`: DIVU instruction
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- `InsnRem`: REM instruction
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- `InsnRemu`: REMU instruction
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- `InsnRV64IIType`: RV64I I-Type Instruction
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- `InsnRV64IITypeLoad`: RV64I I-Type Instruction (Load Variation)
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- `InsnLwu`: LWU instruction
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- `InsnLd`: LD instruction
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- `InsnAddiw`: ADDIW instruction
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- `InsnSd`: SD instruction
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### ISAs
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- `IsaRV32I`: RV32I Base ISA
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- `IsaRV32M`: RV32M Standard Extension
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## Core-specific parameters
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The following core-specific parameters are currently supported:
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| Parameter | Description | Valid value(s) |
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| --- | --- | --- |
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| `params.ilen` | Max length of instruction retired by core | `32` |
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| `params.xlen` | Width of integer registers | `32` |
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| `params.csr_misa` | Support for MISA CSRs enabled | `True`, `False` |
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| `params.compressed` | Support for compressed instructions | `True`, `False` |
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| `params.aligned_mem` | Require aligned memory accesses | `True`, `False` |
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| `params.altops` | Use alternative operations for multiplication/division | `True`, `False` |
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