536 lines
20 KiB
Python
536 lines
20 KiB
Python
from nmigen.test.utils import *
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from ...checks.insn_check import *
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from ...checks.pc_fwd_check import *
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from ...checks.pc_bwd_check import *
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from ...checks.reg_check import *
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from ...checks.causal_check import *
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from ...checks.liveness_check import *
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from ...checks.unique_check import *
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from minerva.core import *
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from ...insns.insn_lui import *
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from ...insns.insn_auipc import *
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from ...insns.insn_jal import *
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from ...insns.insn_jalr import *
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from ...insns.insn_beq import *
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from ...insns.insn_bne import *
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from ...insns.insn_blt import *
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from ...insns.insn_bge import *
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from ...insns.insn_bltu import *
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from ...insns.insn_bgeu import *
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from ...insns.insn_lb import *
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from ...insns.insn_lh import *
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from ...insns.insn_lw import *
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from ...insns.insn_lbu import *
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from ...insns.insn_lhu import *
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from ...insns.insn_sb import *
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from ...insns.insn_sh import *
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from ...insns.insn_sw import *
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from ...insns.insn_addi import *
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from ...insns.insn_slti import *
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from ...insns.insn_sltiu import *
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from ...insns.insn_xori import *
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from ...insns.insn_ori import *
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from ...insns.insn_andi import *
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from ...insns.insn_slli import *
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from ...insns.insn_srli import *
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from ...insns.insn_srai import *
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from ...insns.insn_add import *
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from ...insns.insn_sub import *
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from ...insns.insn_sll import *
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from ...insns.insn_slt import *
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from ...insns.insn_sltu import *
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from ...insns.insn_xor import *
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from ...insns.insn_srl import *
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from ...insns.insn_sra import *
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from ...insns.insn_or import *
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from ...insns.insn_and import *
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from ...insns.insn_mul import *
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from ...insns.insn_mulh import *
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from ...insns.insn_mulhsu import *
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from ...insns.insn_mulhu import *
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from ...insns.insn_div import *
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from ...insns.insn_divu import *
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from ...insns.insn_rem import *
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from ...insns.insn_remu import *
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from collections import namedtuple
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from multiprocessing import Pool
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import sys
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import os
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if len(sys.argv) == 1:
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processes = os.cpu_count()
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else:
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processes = int(sys.argv[1])
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RISCVFormalParameters = namedtuple('RISCVFormalParameters',
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['ilen', 'xlen', 'csr_misa', 'compressed', 'aligned_mem', 'altops'])
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class InsnSpec(Elaboratable):
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def __init__(self, insn_model):
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self.insn_model = insn_model
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def elaborate(self, platform):
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m = Module()
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m.submodules.cpu = cpu = Minerva(
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with_rvfi=True,
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with_muldiv=True,
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with_icache=True,
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icache_nways=2,
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icache_nlines=2,
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icache_nwords=4,
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icache_base=0x1000,
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icache_limit=0x4000,
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with_dcache=True,
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dcache_nways=2,
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dcache_nlines=2,
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dcache_nwords=4,
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dcache_base=0x1000,
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dcache_limit=0x4000)
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m.submodules.insn_spec = insn_spec = InsnCheck(
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params=RISCVFormalParameters(32, 32, False, False, True, True),
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insn_model=self.insn_model,
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rvformal_addr_valid=lambda x:Const(1))
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# Wire input ports to Minerva core
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m.d.comb += cpu.external_interrupt.eq(0)
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m.d.comb += cpu.timer_interrupt.eq(0)
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m.d.comb += cpu.software_interrupt.eq(0)
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m.d.comb += cpu.ibus.dat_r.eq(AnySeq(32))
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m.d.comb += cpu.ibus.ack.eq(AnySeq(1))
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m.d.comb += cpu.ibus.err.eq(0)
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m.d.comb += cpu.dbus.dat_r.eq(AnySeq(32))
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m.d.comb += cpu.dbus.ack.eq(AnySeq(1))
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m.d.comb += cpu.dbus.err.eq(0)
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m.d.comb += insn_spec.reset.eq(AnySeq(1))
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m.d.comb += insn_spec.check.eq(AnySeq(1))
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m.d.comb += insn_spec.rvfi_valid.eq(cpu.rvfi.valid)
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m.d.comb += insn_spec.rvfi_order.eq(cpu.rvfi.order)
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m.d.comb += insn_spec.rvfi_insn.eq(cpu.rvfi.insn)
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m.d.comb += insn_spec.rvfi_trap.eq(cpu.rvfi.trap)
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m.d.comb += insn_spec.rvfi_halt.eq(cpu.rvfi.halt)
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m.d.comb += insn_spec.rvfi_intr.eq(cpu.rvfi.intr)
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m.d.comb += insn_spec.rvfi_mode.eq(cpu.rvfi.mode)
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m.d.comb += insn_spec.rvfi_ixl.eq(cpu.rvfi.ixl)
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m.d.comb += insn_spec.rvfi_rs1_addr.eq(cpu.rvfi.rs1_addr)
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m.d.comb += insn_spec.rvfi_rs2_addr.eq(cpu.rvfi.rs2_addr)
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m.d.comb += insn_spec.rvfi_rs1_rdata.eq(cpu.rvfi.rs1_rdata)
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m.d.comb += insn_spec.rvfi_rs2_rdata.eq(cpu.rvfi.rs2_rdata)
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m.d.comb += insn_spec.rvfi_rd_addr.eq(cpu.rvfi.rd_addr)
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m.d.comb += insn_spec.rvfi_rd_wdata.eq(cpu.rvfi.rd_wdata)
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m.d.comb += insn_spec.rvfi_pc_rdata.eq(cpu.rvfi.pc_rdata)
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m.d.comb += insn_spec.rvfi_pc_wdata.eq(cpu.rvfi.pc_wdata)
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m.d.comb += insn_spec.rvfi_mem_addr.eq(cpu.rvfi.mem_addr)
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m.d.comb += insn_spec.rvfi_mem_rmask.eq(cpu.rvfi.mem_rmask)
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m.d.comb += insn_spec.rvfi_mem_wmask.eq(cpu.rvfi.mem_wmask)
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m.d.comb += insn_spec.rvfi_mem_rdata.eq(cpu.rvfi.mem_rdata)
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m.d.comb += insn_spec.rvfi_mem_wdata.eq(cpu.rvfi.mem_wdata)
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return m
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class PcFwdSpec(Elaboratable):
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def elaborate(self, platform):
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m = Module()
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m.submodules.cpu = cpu = Minerva(
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with_rvfi=True,
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with_muldiv=True,
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with_icache=True,
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icache_nways=2,
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icache_nlines=2,
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icache_nwords=4,
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icache_base=0x1000,
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icache_limit=0x4000,
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with_dcache=True,
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dcache_nways=2,
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dcache_nlines=2,
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dcache_nwords=4,
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dcache_base=0x1000,
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dcache_limit=0x4000)
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m.submodules.pc_fwd_spec = pc_fwd_spec = PcFwdCheck(
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params=RISCVFormalParameters(32, 32, False, False, True, True),
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rvformal_addr_valid=lambda x:Const(1))
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# Wire input ports to Minerva core
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m.d.comb += cpu.external_interrupt.eq(0)
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m.d.comb += cpu.timer_interrupt.eq(0)
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m.d.comb += cpu.software_interrupt.eq(0)
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m.d.comb += cpu.ibus.dat_r.eq(AnySeq(32))
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m.d.comb += cpu.ibus.ack.eq(AnySeq(1))
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m.d.comb += cpu.ibus.err.eq(0)
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m.d.comb += cpu.dbus.dat_r.eq(AnySeq(32))
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m.d.comb += cpu.dbus.ack.eq(AnySeq(1))
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m.d.comb += cpu.dbus.err.eq(0)
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m.d.comb += pc_fwd_spec.reset.eq(AnySeq(1))
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m.d.comb += pc_fwd_spec.check.eq(AnySeq(1))
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m.d.comb += pc_fwd_spec.rvfi_valid.eq(cpu.rvfi.valid)
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m.d.comb += pc_fwd_spec.rvfi_order.eq(cpu.rvfi.order)
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m.d.comb += pc_fwd_spec.rvfi_pc_rdata.eq(cpu.rvfi.pc_rdata)
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m.d.comb += pc_fwd_spec.rvfi_pc_wdata.eq(cpu.rvfi.pc_wdata)
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return m
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class PcFwdTestCase(FHDLTestCase):
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def verify(self):
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self.assertFormal(PcFwdSpec(), mode="cover", depth=20, spec_name="verify_pc_fwd")
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self.assertFormal(PcFwdSpec(), mode="bmc", depth=20, spec_name="verify_pc_fwd")
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print("verify_pc_fwd PASS")
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class PcBwdSpec(Elaboratable):
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def elaborate(self, platform):
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m = Module()
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m.submodules.cpu = cpu = Minerva(
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with_rvfi=True,
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with_muldiv=True,
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with_icache=True,
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icache_nways=2,
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icache_nlines=2,
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icache_nwords=4,
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icache_base=0x1000,
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icache_limit=0x4000,
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with_dcache=True,
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dcache_nways=2,
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dcache_nlines=2,
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dcache_nwords=4,
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dcache_base=0x1000,
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dcache_limit=0x4000)
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m.submodules.pc_bwd_spec = pc_bwd_spec = PcBwdCheck(
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params=RISCVFormalParameters(32, 32, False, False, True, True),
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rvformal_addr_valid=lambda x:Const(1))
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# Wire input ports to Minerva core
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m.d.comb += cpu.external_interrupt.eq(0)
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m.d.comb += cpu.timer_interrupt.eq(0)
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m.d.comb += cpu.software_interrupt.eq(0)
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m.d.comb += cpu.ibus.dat_r.eq(AnySeq(32))
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m.d.comb += cpu.ibus.ack.eq(AnySeq(1))
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m.d.comb += cpu.ibus.err.eq(0)
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m.d.comb += cpu.dbus.dat_r.eq(AnySeq(32))
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m.d.comb += cpu.dbus.ack.eq(AnySeq(1))
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m.d.comb += cpu.dbus.err.eq(0)
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m.d.comb += pc_bwd_spec.reset.eq(AnySeq(1))
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m.d.comb += pc_bwd_spec.check.eq(AnySeq(1))
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m.d.comb += pc_bwd_spec.rvfi_valid.eq(cpu.rvfi.valid)
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m.d.comb += pc_bwd_spec.rvfi_order.eq(cpu.rvfi.order)
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m.d.comb += pc_bwd_spec.rvfi_pc_rdata.eq(cpu.rvfi.pc_rdata)
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m.d.comb += pc_bwd_spec.rvfi_pc_wdata.eq(cpu.rvfi.pc_wdata)
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return m
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class PcBwdTestCase(FHDLTestCase):
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def verify(self):
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self.assertFormal(PcBwdSpec(), mode="cover", depth=20, spec_name="verify_pc_bwd")
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self.assertFormal(PcBwdSpec(), mode="bmc", depth=20, spec_name="verify_pc_bwd")
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print("verify_pc_bwd PASS")
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class RegSpec(Elaboratable):
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def elaborate(self, platform):
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m = Module()
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m.submodules.cpu = cpu = Minerva(
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with_rvfi=True,
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with_muldiv=True,
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with_icache=True,
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icache_nways=2,
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icache_nlines=2,
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icache_nwords=4,
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icache_base=0x1000,
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icache_limit=0x4000,
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with_dcache=True,
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dcache_nways=2,
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dcache_nlines=2,
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dcache_nwords=4,
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dcache_base=0x1000,
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dcache_limit=0x4000)
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m.submodules.reg_spec = reg_spec = RegCheck(params=RISCVFormalParameters(32, 32, False, False, True, True))
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# Wire input ports to Minerva core
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m.d.comb += cpu.external_interrupt.eq(0)
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m.d.comb += cpu.timer_interrupt.eq(0)
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m.d.comb += cpu.software_interrupt.eq(0)
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m.d.comb += cpu.ibus.dat_r.eq(AnySeq(32))
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m.d.comb += cpu.ibus.ack.eq(AnySeq(1))
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m.d.comb += cpu.ibus.err.eq(0)
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m.d.comb += cpu.dbus.dat_r.eq(AnySeq(32))
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m.d.comb += cpu.dbus.ack.eq(AnySeq(1))
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m.d.comb += cpu.dbus.err.eq(0)
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m.d.comb += reg_spec.reset.eq(AnySeq(1))
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m.d.comb += reg_spec.check.eq(AnySeq(1))
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m.d.comb += reg_spec.rvfi_valid.eq(cpu.rvfi.valid)
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m.d.comb += reg_spec.rvfi_order.eq(cpu.rvfi.order)
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m.d.comb += reg_spec.rvfi_rs1_addr.eq(cpu.rvfi.rs1_addr)
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m.d.comb += reg_spec.rvfi_rs1_rdata.eq(cpu.rvfi.rs1_rdata)
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m.d.comb += reg_spec.rvfi_rs2_addr.eq(cpu.rvfi.rs2_addr)
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m.d.comb += reg_spec.rvfi_rs2_rdata.eq(cpu.rvfi.rs2_rdata)
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m.d.comb += reg_spec.rvfi_rd_addr.eq(cpu.rvfi.rd_addr)
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m.d.comb += reg_spec.rvfi_rd_wdata.eq(cpu.rvfi.rd_wdata)
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return m
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class RegTestCase(FHDLTestCase):
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def verify(self):
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self.assertFormal(RegSpec(), mode="cover", depth=10, spec_name="verify_reg")
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self.assertFormal(RegSpec(), mode="bmc", depth=10, spec_name="verify_reg")
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print("verify_reg PASS")
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class CausalSpec(Elaboratable):
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def elaborate(self, platform):
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m = Module()
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m.submodules.cpu = cpu = Minerva(
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with_rvfi=True,
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with_muldiv=True,
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with_icache=True,
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icache_nways=2,
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icache_nlines=2,
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icache_nwords=4,
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icache_base=0x1000,
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icache_limit=0x4000,
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with_dcache=True,
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dcache_nways=2,
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dcache_nlines=2,
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dcache_nwords=4,
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dcache_base=0x1000,
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dcache_limit=0x4000)
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m.submodules.causal_spec = causal_spec = CausalCheck()
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# Wire input ports to Minerva core
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m.d.comb += cpu.external_interrupt.eq(0)
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m.d.comb += cpu.timer_interrupt.eq(0)
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m.d.comb += cpu.software_interrupt.eq(0)
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m.d.comb += cpu.ibus.dat_r.eq(AnySeq(32))
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m.d.comb += cpu.ibus.ack.eq(AnySeq(1))
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m.d.comb += cpu.ibus.err.eq(0)
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m.d.comb += cpu.dbus.dat_r.eq(AnySeq(32))
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m.d.comb += cpu.dbus.ack.eq(AnySeq(1))
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m.d.comb += cpu.dbus.err.eq(0)
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m.d.comb += causal_spec.reset.eq(AnySeq(1))
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m.d.comb += causal_spec.check.eq(AnySeq(1))
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m.d.comb += causal_spec.rvfi_valid.eq(cpu.rvfi.valid)
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m.d.comb += causal_spec.rvfi_rd_addr.eq(cpu.rvfi.rd_addr)
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m.d.comb += causal_spec.rvfi_order.eq(cpu.rvfi.order)
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m.d.comb += causal_spec.rvfi_rs1_addr.eq(cpu.rvfi.rs1_addr)
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m.d.comb += causal_spec.rvfi_rs2_addr.eq(cpu.rvfi.rs2_addr)
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return m
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class CausalTestCase(FHDLTestCase):
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def verify(self):
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self.assertFormal(CausalSpec(), mode="cover", depth=20, spec_name="verify_causal")
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self.assertFormal(CausalSpec(), mode="bmc", depth=20, spec_name="verify_causal")
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print("verify_causal PASS")
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class LivenessSpec(Elaboratable):
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def elaborate(self, platform):
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m = Module()
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m.submodules.cpu = cpu = Minerva(
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with_rvfi=True,
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with_muldiv=True,
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with_icache=True,
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icache_nways=2,
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icache_nlines=2,
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icache_nwords=4,
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icache_base=0x1000,
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icache_limit=0x4000,
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with_dcache=True,
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dcache_nways=2,
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dcache_nlines=2,
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dcache_nwords=4,
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dcache_base=0x1000,
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dcache_limit=0x4000)
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m.submodules.liveness_spec = liveness_spec = LivenessCheck()
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# Wire input ports to Minerva core
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m.d.comb += cpu.external_interrupt.eq(0)
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m.d.comb += cpu.timer_interrupt.eq(0)
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m.d.comb += cpu.software_interrupt.eq(0)
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m.d.comb += cpu.ibus.dat_r.eq(AnySeq(32))
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m.d.comb += cpu.ibus.ack.eq(AnySeq(1))
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m.d.comb += cpu.ibus.err.eq(0)
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m.d.comb += cpu.dbus.dat_r.eq(AnySeq(32))
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m.d.comb += cpu.dbus.ack.eq(AnySeq(1))
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m.d.comb += cpu.dbus.err.eq(0)
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cycle = Signal(8, reset=0)
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with m.If(cycle != 0xFF):
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m.d.sync += cycle.eq(cycle + 1)
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m.d.comb += liveness_spec.reset.eq(cycle < 1)
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m.d.comb += liveness_spec.trig.eq(cycle == 11)
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m.d.comb += liveness_spec.check.eq(cycle == 39)
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m.d.comb += liveness_spec.rvfi_valid.eq(cpu.rvfi.valid)
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m.d.comb += liveness_spec.rvfi_order.eq(cpu.rvfi.order)
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m.d.comb += liveness_spec.rvfi_halt.eq(cpu.rvfi.halt)
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# Bounded fairness constraints
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ibus_wait = Signal(2, reset=0)
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dbus_wait = Signal(2, reset=0)
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with m.If(cpu.ibus.cyc & cpu.ibus.stb & ~(cpu.ibus.ack | cpu.ibus.err)):
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m.d.sync += ibus_wait.eq(ibus_wait + 1)
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with m.Else():
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m.d.sync += ibus_wait.eq(0)
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with m.If(cpu.dbus.cyc & cpu.dbus.stb & ~(cpu.dbus.ack | cpu.dbus.err)):
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m.d.sync += dbus_wait.eq(dbus_wait + 1)
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with m.Else():
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m.d.sync += dbus_wait.eq(0)
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m.d.comb += Assume((ibus_wait < 2) & (dbus_wait < 2))
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with m.If(liveness_spec.reset):
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m.d.sync += ibus_wait.eq(0)
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m.d.sync += dbus_wait.eq(0)
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return m
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class LivenessTestCase(FHDLTestCase):
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def verify(self):
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self.assertFormal(LivenessSpec(), mode="cover", depth=40, spec_name="verify_liveness")
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self.assertFormal(LivenessSpec(), mode="bmc", depth=40, spec_name="verify_liveness")
|
|
print("verify_liveness PASS")
|
|
|
|
class UniqueSpec(Elaboratable):
|
|
def elaborate(self, platform):
|
|
m = Module()
|
|
|
|
m.submodules.cpu = cpu = Minerva(
|
|
with_rvfi=True,
|
|
with_muldiv=True,
|
|
with_icache=True,
|
|
icache_nways=2,
|
|
icache_nlines=2,
|
|
icache_nwords=4,
|
|
icache_base=0x1000,
|
|
icache_limit=0x4000,
|
|
with_dcache=True,
|
|
dcache_nways=2,
|
|
dcache_nlines=2,
|
|
dcache_nwords=4,
|
|
dcache_base=0x1000,
|
|
dcache_limit=0x4000)
|
|
m.submodules.unique_spec = unique_spec = UniqueCheck()
|
|
|
|
# Wire input ports to Minerva core
|
|
m.d.comb += cpu.external_interrupt.eq(0)
|
|
m.d.comb += cpu.timer_interrupt.eq(0)
|
|
m.d.comb += cpu.software_interrupt.eq(0)
|
|
m.d.comb += cpu.ibus.dat_r.eq(AnySeq(32))
|
|
m.d.comb += cpu.ibus.ack.eq(AnySeq(1))
|
|
m.d.comb += cpu.ibus.err.eq(0)
|
|
m.d.comb += cpu.dbus.dat_r.eq(AnySeq(32))
|
|
m.d.comb += cpu.dbus.ack.eq(AnySeq(1))
|
|
m.d.comb += cpu.dbus.err.eq(0)
|
|
|
|
cycle = Signal(8, reset=0)
|
|
with m.If(cycle != 0xFF):
|
|
m.d.sync += cycle.eq(cycle + 1)
|
|
m.d.comb += unique_spec.reset.eq(cycle < 1)
|
|
m.d.comb += unique_spec.trig.eq(cycle == 11)
|
|
m.d.comb += unique_spec.check.eq(cycle == 24)
|
|
|
|
m.d.comb += unique_spec.rvfi_valid.eq(cpu.rvfi.valid)
|
|
m.d.comb += unique_spec.rvfi_order.eq(cpu.rvfi.order)
|
|
|
|
return m
|
|
|
|
class UniqueTestCase(FHDLTestCase):
|
|
def verify(self):
|
|
self.assertFormal(UniqueSpec(), mode="cover", depth=25, spec_name="verify_uniqueness")
|
|
self.assertFormal(UniqueSpec(), mode="bmc", depth=25, spec_name="verify_uniqueness")
|
|
print("verify_uniqueness PASS")
|
|
|
|
def verify_insn(testcase, insn_spec, spec_name):
|
|
testcase.assertFormal(InsnSpec(insn_spec), mode="cover", depth=20, spec_name=spec_name)
|
|
testcase.assertFormal(InsnSpec(insn_spec), mode="bmc", depth=20, spec_name=spec_name)
|
|
print("%s PASS" % spec_name)
|
|
|
|
class MinervaTestCase(FHDLTestCase):
|
|
def verify(self):
|
|
with Pool(processes=processes) as pool:
|
|
insns = [
|
|
(InsnLui, "verify_lui"),
|
|
(InsnAuipc, "verify_auipc"),
|
|
(InsnJal, "verify_jal"),
|
|
(InsnJalr, "verify_jalr"),
|
|
(InsnBeq, "verify_beq"),
|
|
(InsnBne, "verify_bne"),
|
|
(InsnBlt, "verify_blt"),
|
|
(InsnBge, "verify_bge"),
|
|
(InsnBltu, "verify_bltu"),
|
|
(InsnBgeu, "verify_bgeu"),
|
|
(InsnLb, "verify_lb"),
|
|
(InsnLh, "verify_lh"),
|
|
(InsnLw, "verify_lw"),
|
|
(InsnLbu, "verify_lbu"),
|
|
(InsnLhu, "verify_lhu"),
|
|
(InsnSb, "verify_sb"),
|
|
(InsnSh, "verify_sh"),
|
|
(InsnSw, "verify_sw"),
|
|
(InsnAddi, "verify_addi"),
|
|
(InsnSlti, "verify_slti"),
|
|
(InsnSltiu, "verify_sltiu"),
|
|
(InsnXori, "verify_xori"),
|
|
(InsnOri, "verify_ori"),
|
|
(InsnAndi, "verify_andi"),
|
|
(InsnSlli, "verify_slli"),
|
|
(InsnSrli, "verify_srli"),
|
|
(InsnSrai, "verify_srai"),
|
|
(InsnAdd, "verify_add"),
|
|
(InsnSub, "verify_sub"),
|
|
(InsnSll, "verify_sll"),
|
|
(InsnSlt, "verify_slt"),
|
|
(InsnSltu, "verify_sltu"),
|
|
(InsnXor, "verify_xor"),
|
|
(InsnSrl, "verify_srl"),
|
|
(InsnSra, "verify_sra"),
|
|
(InsnOr, "verify_or"),
|
|
(InsnAnd, "verify_and"),
|
|
(InsnMul, "verify_mul"),
|
|
(InsnMulh, "verify_mulh"),
|
|
(InsnMulhsu, "verify_mulhsu"),
|
|
(InsnMulhu, "verify_mulhu"),
|
|
(InsnDiv, "verify_div"),
|
|
(InsnDivu, "verify_divu"),
|
|
(InsnRem, "verify_rem"),
|
|
(InsnRemu, "verify_remu")
|
|
]
|
|
tasks = [pool.apply_async(verify_insn, (self, insn_spec, spec_name)) for insn_spec, spec_name in insns]
|
|
tasks.append(pool.apply_async(PcFwdTestCase().verify))
|
|
tasks.append(pool.apply_async(PcBwdTestCase().verify))
|
|
tasks.append(pool.apply_async(RegTestCase().verify))
|
|
tasks.append(pool.apply_async(CausalTestCase().verify))
|
|
tasks.append(pool.apply_async(LivenessTestCase().verify))
|
|
tasks.append(pool.apply_async(UniqueTestCase().verify))
|
|
[p.get() for p in tasks]
|
|
|
|
print('*' * 80)
|
|
print('*' + ' ' * 78 + '*')
|
|
print('* Verifying the Minerva core ... *')
|
|
print('*' + ' ' * 78 + '*')
|
|
print('*' * 80)
|
|
|
|
print("Verifying RV32M instructions ...")
|
|
print("Verifying PC forward checks ...")
|
|
print("Verifying PC backward checks ...")
|
|
print("Verifying register checks ...")
|
|
print("Verifying causal checks ...")
|
|
print("Verifying liveness checks ...")
|
|
print("Verifying uniqueness checks ...")
|
|
|
|
MinervaTestCase().verify()
|
|
|
|
print('*' * 80)
|
|
print('*' + ' ' * 78 + '*')
|
|
print('* All verification tasks successful! *')
|
|
print('*' + ' ' * 78 + '*')
|
|
print('*' * 80)
|