M-Labs/riscv-formal-nmigen
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A port of [riscv-formal](https://github.com/SymbioticEDA/riscv-formal) to nMigen
17 Commits 1 Branch 0 Tags 683 KiB
Python 99.4%
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Donald Sebastian Leung 37f21b317b Add LBU instruction for RV32I
2020-07-22 12:46:56 +08:00
insns Add LBU instruction for RV32I 2020-07-22 12:46:56 +08:00
LICENSE Copy license from source 2020-07-14 10:42:06 +08:00
README.md Mention expected scope of project in README 2020-07-21 17:55:28 +08:00

README.md

riscv-formal-nmigen

A port of riscv-formal to nMigen

Dependencies

Build

TODO

Support

The full RISC-V specification is hundreds of pages long including numerous possible extensions, some of which are still under active development at the time of writing. Therefore, this project does not aim to formalize the entire specification, but only the core parts of the specification, namely RV32I and perhaps RV32IM. Support for other extensions of the RISC-V specification may be added in the future.

License

See LICENSE