50 lines
2.1 KiB
Python
50 lines
2.1 KiB
Python
from nmigen import *
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from nmigen.test.utils import *
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from ..core import *
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from ....checks.insn_check import *
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from ....insns.insn_lui import *
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class LuiSpec(Elaboratable):
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def elaborate(self, platform):
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m = Module()
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m.submodules.cpu = cpu = Minerva(with_rvfi=True)
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m.submodules.insn_spec = insn_spec = InsnCheck(RISCV_FORMAL_ILEN=32,
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RISCV_FORMAL_XLEN=32,
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RISCV_FORMAL_CSR_MISA=False,
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RISCV_FORMAL_COMPRESSED=False,
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RISCV_FORMAL_ALIGNED_MEM=False,
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insn_model=InsnLui,
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rvformal_addr_valid=lambda x:Const(1))
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m.d.comb += insn_spec.reset.eq(0)
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m.d.comb += insn_spec.check.eq(1)
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m.d.comb += insn_spec.rvfi_valid.eq(cpu.rvfi.valid)
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m.d.comb += insn_spec.rvfi_order.eq(cpu.rvfi.order)
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m.d.comb += insn_spec.rvfi_insn.eq(cpu.rvfi.insn)
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m.d.comb += insn_spec.rvfi_trap.eq(cpu.rvfi.trap)
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m.d.comb += insn_spec.rvfi_halt.eq(cpu.rvfi.halt)
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m.d.comb += insn_spec.rvfi_intr.eq(cpu.rvfi.intr)
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m.d.comb += insn_spec.rvfi_mode.eq(cpu.rvfi.mode)
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m.d.comb += insn_spec.rvfi_ixl.eq(cpu.rvfi.ixl)
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m.d.comb += insn_spec.rvfi_rs1_addr.eq(cpu.rvfi.rs1_addr)
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m.d.comb += insn_spec.rvfi_rs2_addr.eq(cpu.rvfi.rs2_addr)
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m.d.comb += insn_spec.rvfi_rs1_rdata.eq(cpu.rvfi.rs1_rdata)
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m.d.comb += insn_spec.rvfi_rs2_rdata.eq(cpu.rvfi.rs2_rdata)
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m.d.comb += insn_spec.rvfi_rd_addr.eq(cpu.rvfi.rd_addr)
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m.d.comb += insn_spec.rvfi_rd_wdata.eq(cpu.rvfi.rd_wdata)
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m.d.comb += insn_spec.rvfi_pc_rdata.eq(cpu.rvfi.pc_rdata)
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m.d.comb += insn_spec.rvfi_pc_wdata.eq(cpu.rvfi.pc_wdata)
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m.d.comb += insn_spec.rvfi_mem_addr.eq(cpu.rvfi.mem_addr)
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m.d.comb += insn_spec.rvfi_mem_rmask.eq(cpu.rvfi.mem_rmask)
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m.d.comb += insn_spec.rvfi_mem_wmask.eq(cpu.rvfi.mem_wmask)
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m.d.comb += insn_spec.rvfi_mem_rdata.eq(cpu.rvfi.mem_rdata)
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m.d.comb += insn_spec.rvfi_mem_wdata.eq(cpu.rvfi.mem_wdata)
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return m
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class LuiTestCase(FHDLTestCase):
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def verify(self):
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self.assertFormal(LuiSpec(), mode="bmc", depth=12)
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