M-Labs/riscv-formal-nmigen
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Restructure insns directory contents #2

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dsleung merged 109 commits from restructuring into master 2020-08-13 15:20:35 +08:00
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1 changed files with 2 additions and 2 deletions
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insns/InsnRV32IITypeLoad.py
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@ -5,8 +5,8 @@ RV32I I-Type Instruction (Load Variation)
""" """
class InsnRV32IITypeLoad(InsnRV32IIType): class InsnRV32IITypeLoad(InsnRV32IIType):
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, RISCV_FORMAL_ALIGNED_MEM, funct3, mask_shift, is_signed): def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM, funct3, mask_shift, is_signed):
super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED) super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA)
self.RISCV_FORMAL_ALIGNED_MEM = RISCV_FORMAL_ALIGNED_MEM self.RISCV_FORMAL_ALIGNED_MEM = RISCV_FORMAL_ALIGNED_MEM
self.funct3 = funct3 self.funct3 = funct3
self.mask_shift = mask_shift self.mask_shift = mask_shift