From 3eaed129c295d6a15ce618ebc527e606c8aca095 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Thu, 6 Aug 2020 12:36:01 +0800 Subject: [PATCH 001/109] Begin re-organization of project structure --- README.md | 2 +- checks/rvfi_causal_check.py | 81 -- checks/rvfi_channel.py | 103 --- checks/rvfi_dmem_check.py | 82 -- checks/rvfi_hang_check.py | 77 -- checks/rvfi_ill_check.py | 109 --- checks/rvfi_imem_check.py | 88 -- checks/rvfi_insn_check.py | 205 ----- checks/rvfi_liveness_check.py | 79 -- checks/rvfi_pc_bwd_check.py | 82 -- checks/rvfi_pc_fwd_check.py | 82 -- checks/rvfi_reg_check.py | 84 -- checks/rvfi_unique_check.py | 78 -- insns/README.md | 28 - insns/insn.py | 51 -- insns/insn_I.py | 38 - insns/insn_I_shift.py | 38 - insns/insn_R.py | 37 - insns/insn_S.py | 32 - insns/insn_SB.py | 38 - insns/insn_U.py | 33 - insns/insn_UJ.py | 34 - insns/insn_add.py | 21 - insns/insn_addi.py | 20 - insns/insn_and.py | 21 - insns/insn_andi.py | 20 - insns/insn_auipc.py | 17 - insns/insn_beq.py | 22 - insns/insn_bge.py | 22 - insns/insn_bgeu.py | 22 - insns/insn_blt.py | 22 - insns/insn_bltu.py | 22 - insns/insn_bne.py | 22 - insns/insn_div.py | 23 - insns/insn_divu.py | 23 - insns/insn_jal.py | 20 - insns/insn_jalr.py | 21 - insns/insn_lb.py | 25 - insns/insn_lbu.py | 25 - insns/insn_lh.py | 25 - insns/insn_lhu.py | 25 - insns/insn_lui.py | 17 - insns/insn_lw.py | 25 - insns/insn_mul.py | 23 - insns/insn_mulh.py | 23 - insns/insn_mulhsu.py | 23 - insns/insn_mulhu.py | 23 - insns/insn_or.py | 21 - insns/insn_ori.py | 20 - insns/insn_rem.py | 23 - insns/insn_remu.py | 23 - insns/insn_sb.py | 23 - insns/insn_sh.py | 23 - insns/insn_sll.py | 23 - insns/insn_slli.py | 20 - insns/insn_slt.py | 21 - insns/insn_slti.py | 20 - insns/insn_sltiu.py | 20 - insns/insn_sltu.py | 21 - insns/insn_sra.py | 23 - insns/insn_srai.py | 20 - insns/insn_srl.py | 23 - insns/insn_srli.py | 20 - insns/insn_sub.py | 21 - insns/insn_sw.py | 23 - insns/insn_types.md | 11 - insns/insn_xor.py | 21 - insns/insn_xori.py | 20 - insns/isa_rv32i.py | 1211 --------------------------- insns/isa_rv32i.txt | 37 - insns/isa_rv32i_gen.py | 107 --- insns/isa_rv32im.py | 1459 --------------------------------- insns/isa_rv32im.txt | 45 - insns/isa_rv32im_gen.py | 107 --- 74 files changed, 1 insertion(+), 5438 deletions(-) delete mode 100644 checks/rvfi_causal_check.py delete mode 100644 checks/rvfi_channel.py delete mode 100644 checks/rvfi_dmem_check.py delete mode 100644 checks/rvfi_hang_check.py delete mode 100644 checks/rvfi_ill_check.py delete mode 100644 checks/rvfi_imem_check.py delete mode 100644 checks/rvfi_insn_check.py delete mode 100644 checks/rvfi_liveness_check.py delete mode 100644 checks/rvfi_pc_bwd_check.py delete mode 100644 checks/rvfi_pc_fwd_check.py delete mode 100644 checks/rvfi_reg_check.py delete mode 100644 checks/rvfi_unique_check.py delete mode 100644 insns/README.md delete mode 100644 insns/insn.py delete mode 100644 insns/insn_I.py delete mode 100644 insns/insn_I_shift.py delete mode 100644 insns/insn_R.py delete mode 100644 insns/insn_S.py delete mode 100644 insns/insn_SB.py delete mode 100644 insns/insn_U.py delete mode 100644 insns/insn_UJ.py delete mode 100644 insns/insn_add.py delete mode 100644 insns/insn_addi.py delete mode 100644 insns/insn_and.py delete mode 100644 insns/insn_andi.py delete mode 100644 insns/insn_auipc.py delete mode 100644 insns/insn_beq.py delete mode 100644 insns/insn_bge.py delete mode 100644 insns/insn_bgeu.py delete mode 100644 insns/insn_blt.py delete mode 100644 insns/insn_bltu.py delete mode 100644 insns/insn_bne.py delete mode 100644 insns/insn_div.py delete mode 100644 insns/insn_divu.py delete mode 100644 insns/insn_jal.py delete mode 100644 insns/insn_jalr.py delete mode 100644 insns/insn_lb.py delete mode 100644 insns/insn_lbu.py delete mode 100644 insns/insn_lh.py delete mode 100644 insns/insn_lhu.py delete mode 100644 insns/insn_lui.py delete mode 100644 insns/insn_lw.py delete mode 100644 insns/insn_mul.py delete mode 100644 insns/insn_mulh.py delete mode 100644 insns/insn_mulhsu.py delete mode 100644 insns/insn_mulhu.py delete mode 100644 insns/insn_or.py delete mode 100644 insns/insn_ori.py delete mode 100644 insns/insn_rem.py delete mode 100644 insns/insn_remu.py delete mode 100644 insns/insn_sb.py delete mode 100644 insns/insn_sh.py delete mode 100644 insns/insn_sll.py delete mode 100644 insns/insn_slli.py delete mode 100644 insns/insn_slt.py delete mode 100644 insns/insn_slti.py delete mode 100644 insns/insn_sltiu.py delete mode 100644 insns/insn_sltu.py delete mode 100644 insns/insn_sra.py delete mode 100644 insns/insn_srai.py delete mode 100644 insns/insn_srl.py delete mode 100644 insns/insn_srli.py delete mode 100644 insns/insn_sub.py delete mode 100644 insns/insn_sw.py delete mode 100644 insns/insn_types.md delete mode 100644 insns/insn_xor.py delete mode 100644 insns/insn_xori.py delete mode 100644 insns/isa_rv32i.py delete mode 100644 insns/isa_rv32i.txt delete mode 100644 insns/isa_rv32i_gen.py delete mode 100644 insns/isa_rv32im.py delete mode 100644 insns/isa_rv32im.txt delete mode 100644 insns/isa_rv32im_gen.py diff --git a/README.md b/README.md index e08822d..4da6fa1 100644 --- a/README.md +++ b/README.md @@ -12,7 +12,7 @@ TODO ## Scope -The full [RISC-V specification](https://riscv.org/specifications/) is hundreds of pages long including numerous possible extensions, some of which are still under active development at the time of writing. Therefore, this project does not aim to formalize the entire specification, but only the core parts of the specification, namely RV32I (except FENCE, ECALL and EBREAK) and perhaps RV32IM. Support for other extensions of the RISC-V specification may be added in the future. +As with the original riscv-formal, support is planned for the RV32I and RV64I base ISAs, as well as the M and C extensions and combinations thereof (e.g. RV32IM, RV64IMC). ## License diff --git a/checks/rvfi_causal_check.py b/checks/rvfi_causal_check.py deleted file mode 100644 index df87bab..0000000 --- a/checks/rvfi_causal_check.py +++ /dev/null @@ -1,81 +0,0 @@ -from nmigen import * -from nmigen.hdl.ast import * - -class rvfi_causal_check(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.reset = Signal(1) - self.check = Signal(1) - self.rvfi_valid = Signal(1) - self.rvfi_order = Signal(64) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_trap = Signal(1) - self.rvfi_halt = Signal(1) - self.rvfi_intr = Signal(1) - self.rvfi_mode = Signal(2) - self.rvfi_ixl = Signal(2) - self.rvfi_rs1_addr = Signal(5) - self.rvfi_rs2_addr = Signal(5) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rd_addr = Signal(5) - self.rvfi_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.rvfi_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.reset, - self.check, - self.rvfi_valid, - self.rvfi_order, - self.rvfi_insn, - self.rvfi_trap, - self.rvfi_halt, - self.rvfi_intr, - self.rvfi_mode, - self.rvfi_ixl, - self.rvfi_rs1_addr, - self.rvfi_rs2_addr, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_rd_addr, - self.rvfi_rd_wdata, - self.rvfi_pc_rdata, - self.rvfi_pc_wdata, - self.rvfi_mem_addr, - self.rvfi_mem_rmask, - self.rvfi_mem_wmask, - self.rvfi_mem_rdata, - self.rvfi_mem_wdata - ] - output_ports = [] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - insn_order = AnyConst(64) - register_index = AnyConst(5) - found_non_causal = Signal(1, reset=0) - - with m.If(self.reset): - m.d.sync += found_non_causal.eq(0) - with m.Else(): - with m.If(self.check): - m.d.comb += Assume(register_index != 0) - m.d.comb += Assume(self.rvfi_valid) - m.d.comb += Assume(register_index == self.rvfi_rd_addr) - m.d.comb += Assume(insn_order == self.rvfi_order) - m.d.comb += Assert(~found_non_causal) - with m.Else(): - with m.If(self.rvfi_valid & (self.rvfi_order > insn_order) & \ - ((register_index == self.rvfi_rs1_addr) | \ - (register_index == self.rvfi_rs2_addr))): - m.d.sync += found_non_causal.eq(1) - - return m diff --git a/checks/rvfi_channel.py b/checks/rvfi_channel.py deleted file mode 100644 index e149c19..0000000 --- a/checks/rvfi_channel.py +++ /dev/null @@ -1,103 +0,0 @@ -from nmigen import * -from nmigen.hdl.ast import * - -class rvfi_channel(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_order = Signal(64) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_trap = Signal(1) - self.rvfi_halt = Signal(1) - self.rvfi_intr = Signal(1) - self.rvfi_mode = Signal(2) - self.rvfi_ixl = Signal(2) - self.rvfi_rs1_addr = Signal(5) - self.rvfi_rs2_addr = Signal(5) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rd_addr = Signal(5) - self.rvfi_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.rvfi_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_order, - self.rvfi_insn, - self.rvfi_trap, - self.rvfi_halt, - self.rvfi_intr, - self.rvfi_mode, - self.rvfi_ixl, - self.rvfi_rs1_addr, - self.rvfi_rs2_addr, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_rd_addr, - self.rvfi_rd_wdata, - self.rvfi_pc_rdata, - self.rvfi_pc_wdata, - self.rvfi_mem_addr, - self.rvfi_mem_rmask, - self.rvfi_mem_wmask, - self.rvfi_mem_rdata, - self.rvfi_mem_wdata - ] - output_ports = [] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - valid = Signal(1) - m.d.comb += valid.eq(self.rvfi_valid) - order = Signal(64) - m.d.comb += order.eq(self.rvfi_order) - insn = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn.eq(self.rvfi_insn) - trap = Signal(1) - m.d.comb += trap.eq(self.rvfi_trap) - halt = Signal(1) - m.d.comb += halt.eq(self.rvfi_halt) - intr = Signal(1) - m.d.comb += intr.eq(self.rvfi_intr) - mode = Signal(2) - m.d.comb += mode.eq(self.rvfi_mode) - ixl = Signal(2) - m.d.comb += ixl.eq(self.rvfi_ixl) - - rs1_addr = Signal(5) - m.d.comb += rs1_addr.eq(self.rvfi_rs1_addr) - rs2_addr = Signal(5) - m.d.comb += rs2_addr.eq(self.rvfi_rs2_addr) - rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += rs1_rdata.eq(self.rvfi_rs1_rdata) - rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += rs2_rdata.eq(self.rvfi_rs2_rdata) - rd_addr = Signal(5) - m.d.comb += rd_addr.eq(self.rvfi_rd_addr) - rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += rd_wdata.eq(self.rvfi_rd_wdata) - pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += pc_rdata.eq(self.rvfi_pc_rdata) - pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += pc_wdata.eq(self.rvfi_pc_wdata) - - mem_addr = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += mem_addr.eq(self.rvfi_mem_addr) - mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - m.d.comb += mem_rmask.eq(self.rvfi_mem_rmask) - mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - m.d.comb += mem_wmask.eq(self.rvfi_mem_wmask) - mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += mem_rdata.eq(self.rvfi_mem_rdata) - mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += mem_wdata.eq(self.rvfi_mem_wdata) - - return m diff --git a/checks/rvfi_dmem_check.py b/checks/rvfi_dmem_check.py deleted file mode 100644 index 4444ed7..0000000 --- a/checks/rvfi_dmem_check.py +++ /dev/null @@ -1,82 +0,0 @@ -from nmigen import * -from nmigen.hdl.ast import * - -class rvfi_dmem_check(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.reset = Signal(1) - self.enable = Signal(1) - self.dmem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_valid = Signal(1) - self.rvfi_order = Signal(64) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_trap = Signal(1) - self.rvfi_halt = Signal(1) - self.rvfi_intr = Signal(1) - self.rvfi_mode = Signal(2) - self.rvfi_ixl = Signal(2) - self.rvfi_rs1_addr = Signal(5) - self.rvfi_rs2_addr = Signal(5) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rd_addr = Signal(5) - self.rvfi_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.rvfi_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.reset, - self.enable, - self.rvfi_valid, - self.rvfi_order, - self.rvfi_insn, - self.rvfi_trap, - self.rvfi_halt, - self.rvfi_intr, - self.rvfi_mode, - self.rvfi_ixl, - self.rvfi_rs1_addr, - self.rvfi_rs2_addr, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_rd_addr, - self.rvfi_rd_wdata, - self.rvfi_pc_rdata, - self.rvfi_pc_wdata, - self.rvfi_mem_addr, - self.rvfi_mem_rmask, - self.rvfi_mem_wmask, - self.rvfi_mem_rdata, - self.rvfi_mem_wdata - ] - output_ports = [ - self.dmem_addr - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - dmem_addr_randval = AnyConst(self.RISCV_FORMAL_XLEN) - m.d.comb += self.dmem_addr.eq(dmem_addr_randval) - - dmem_shadow = Signal(self.RISCV_FORMAL_XLEN) - dmem_written = Signal(int(self.RISCV_FORMAL_XLEN // 8), reset=0) - - with m.If(self.reset): - m.d.sync += dmem_written.eq(0) - with m.Else(): - with m.If(self.rvfi_valid & (self.rvfi_mem_addr == self.dmem_addr) & 1): - for i in range(int(self.RISCV_FORMAL_XLEN // 8)): - with m.If(self.enable & self.rvfi_mem_rmask[i] & dmem_written[i]): - m.d.comb += Assert(dmem_shadow[i*8:i*8+8] == self.rvfi_mem_rdata[i*8:i*8+8]) - with m.If(self.rvfi_mem_wmask[i]): - m.d.sync += dmem_shadow[i*8:i*8+8].eq(self.rvfi_mem_wdata[i*8:i*8+8]) - m.d.sync += dmem_written[i].eq(1) - - return m diff --git a/checks/rvfi_hang_check.py b/checks/rvfi_hang_check.py deleted file mode 100644 index acfc371..0000000 --- a/checks/rvfi_hang_check.py +++ /dev/null @@ -1,77 +0,0 @@ -from nmigen import * -from nmigen.hdl.ast import * - -class rvfi_hang_check(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.reset = Signal(1) - self.trig = Signal(1) - self.check = Signal(1) - self.rvfi_valid = Signal(1) - self.rvfi_order = Signal(64) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_trap = Signal(1) - self.rvfi_halt = Signal(1) - self.rvfi_intr = Signal(1) - self.rvfi_mode = Signal(2) - self.rvfi_ixl = Signal(2) - self.rvfi_rs1_addr = Signal(5) - self.rvfi_rs2_addr = Signal(5) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rd_addr = Signal(5) - self.rvfi_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.rvfi_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.reset, - self.trig, - self.check, - self.rvfi_valid, - self.rvfi_order, - self.rvfi_insn, - self.rvfi_trap, - self.rvfi_halt, - self.rvfi_intr, - self.rvfi_mode, - self.rvfi_ixl, - self.rvfi_rs1_addr, - self.rvfi_rs2_addr, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_rd_addr, - self.rvfi_rd_wdata, - self.rvfi_pc_rdata, - self.rvfi_pc_wdata, - self.rvfi_mem_addr, - self.rvfi_mem_rmask, - self.rvfi_mem_wmask, - self.rvfi_mem_rdata, - self.rvfi_mem_wdata - ] - output_ports = [] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - okay = Signal(1, reset=0) - - with m.If(self.reset): - m.d.sync += okay.eq(0) - with m.Else(): - with m.If(self.rvfi_valid): - m.d.sync += okay.eq(1) - with m.If(self.check): - m.d.comb += Assert(okay) - with m.If(self.rvfi_valid): - m.d.comb += Assume(~self.rvfi_halt) - m.d.comb += Assume(self.rvfi_insn != 0b00010000010100000000000001110011) # WFI - - return m diff --git a/checks/rvfi_ill_check.py b/checks/rvfi_ill_check.py deleted file mode 100644 index e2e17f7..0000000 --- a/checks/rvfi_ill_check.py +++ /dev/null @@ -1,109 +0,0 @@ -from nmigen import * -from nmigen.hdl.ast import * - -class rvfi_ill_check(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.reset = Signal(1) - self.check = Signal(1) - self.rvfi_valid = Signal(1) - self.rvfi_order = Signal(64) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_trap = Signal(1) - self.rvfi_halt = Signal(1) - self.rvfi_intr = Signal(1) - self.rvfi_mode = Signal(2) - self.rvfi_ixl = Signal(2) - self.rvfi_rs1_addr = Signal(5) - self.rvfi_rs2_addr = Signal(5) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rd_addr = Signal(5) - self.rvfi_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.rvfi_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.reset, - self.check, - self.rvfi_valid, - self.rvfi_order, - self.rvfi_insn, - self.rvfi_trap, - self.rvfi_halt, - self.rvfi_intr, - self.rvfi_mode, - self.rvfi_ixl, - self.rvfi_rs1_addr, - self.rvfi_rs2_addr, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_rd_addr, - self.rvfi_rd_wdata, - self.rvfi_pc_rdata, - self.rvfi_pc_wdata, - self.rvfi_mem_addr, - self.rvfi_mem_rmask, - self.rvfi_mem_wmask, - self.rvfi_mem_rdata, - self.rvfi_mem_wdata - ] - output_ports = [] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - valid = Signal(1) - m.d.comb += valid.eq((~self.reset) & self.rvfi_valid) - insn = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn.eq(self.rvfi_insn) - trap = Signal(1) - m.d.comb += trap.eq(self.rvfi_trap) - halt = Signal(1) - m.d.comb += halt.eq(self.rvfi_halt) - intr = Signal(1) - m.d.comb += intr.eq(self.rvfi_intr) - rs1_addr = Signal(5) - m.d.comb += rs1_addr.eq(self.rvfi_rs1_addr) - rs2_addr = Signal(5) - m.d.comb += rs2_addr.eq(self.rvfi_rs2_addr) - rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += rs1_rdata.eq(self.rvfi_rs1_rdata) - rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += rs2_rdata.eq(self.rvfi_rs2_rdata) - rd_addr = Signal(5) - m.d.comb += rd_addr.eq(self.rvfi_rd_addr) - rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += rd_wdata.eq(self.rvfi_rd_wdata) - pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += pc_rdata.eq(self.rvfi_pc_rdata) - pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += pc_wdata.eq(self.rvfi_pc_wdata) - - mem_addr = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += mem_addr.eq(self.rvfi_mem_addr) - mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - m.d.comb += mem_rmask.eq(self.rvfi_mem_rmask) - mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - m.d.comb += mem_wmask.eq(self.rvfi_mem_wmask) - mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += mem_rdata.eq(self.rvfi_mem_rdata) - mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += mem_wdata.eq(self.rvfi_mem_wdata) - - m.d.comb += Cover((~self.reset) & self.check & valid & (insn == 0)) - with m.If((~self.reset) & self.check): - m.d.comb += Assume(valid) - m.d.comb += Assume(insn == 0) - m.d.comb += Assert(trap) - m.d.comb += Assert(rd_addr == 0) - m.d.comb += Assert(rd_wdata == 0) - m.d.comb += Assert(mem_wmask == 0) - - return m diff --git a/checks/rvfi_imem_check.py b/checks/rvfi_imem_check.py deleted file mode 100644 index 304a988..0000000 --- a/checks/rvfi_imem_check.py +++ /dev/null @@ -1,88 +0,0 @@ -from nmigen import * -from nmigen.hdl.ast import * - -class rvfi_imem_check(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.reset = Signal(1) - self.enable = Signal(1) - self.imem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.imem_data = Signal(16) - self.rvfi_valid = Signal(1) - self.rvfi_order = Signal(64) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_trap = Signal(1) - self.rvfi_halt = Signal(1) - self.rvfi_intr = Signal(1) - self.rvfi_mode = Signal(2) - self.rvfi_ixl = Signal(2) - self.rvfi_rs1_addr = Signal(5) - self.rvfi_rs2_addr = Signal(5) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rd_addr = Signal(5) - self.rvfi_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.rvfi_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.reset, - self.enable, - self.rvfi_valid, - self.rvfi_order, - self.rvfi_insn, - self.rvfi_trap, - self.rvfi_halt, - self.rvfi_intr, - self.rvfi_mode, - self.rvfi_ixl, - self.rvfi_rs1_addr, - self.rvfi_rs2_addr, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_rd_addr, - self.rvfi_rd_wdata, - self.rvfi_pc_rdata, - self.rvfi_pc_wdata, - self.rvfi_mem_addr, - self.rvfi_mem_rmask, - self.rvfi_mem_wmask, - self.rvfi_mem_rdata, - self.rvfi_mem_wdata - ] - output_ports = [ - self.imem_addr, - self.imem_data - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - imem_addr_randval = AnyConst(self.RISCV_FORMAL_XLEN) - imem_data_randval = AnyConst(16) - m.d.comb += self.imem_addr.eq(imem_addr_randval) - m.d.comb += self.imem_data.eq(imem_data_randval) - - pc = Signal(self.RISCV_FORMAL_XLEN) - insn = Signal(self.RISCV_FORMAL_ILEN) - - with m.If(self.reset): - pass - with m.Else(): - with m.If(self.enable & self.rvfi_valid): - m.d.sync += pc.eq(self.rvfi_pc_rdata) - m.d.sync += insn.eq(self.rvfi_insn) - - with m.If(pc == self.imem_addr): - m.d.comb += Assert(insn[:16] == self.imem_data) - - with m.If((insn[:2] == 0b11) & (pc + 2 == self.imem_addr)): - m.d.comb += Assert(insn[16:32] == self.imem_data) - - return m diff --git a/checks/rvfi_insn_check.py b/checks/rvfi_insn_check.py deleted file mode 100644 index 5a9b4cf..0000000 --- a/checks/rvfi_insn_check.py +++ /dev/null @@ -1,205 +0,0 @@ -from nmigen import * -from nmigen.hdl.ast import * - -# Ugly hack for now to get the insn_add import working -import sys -sys.path.append('../insns') -from insn_add import * - -class rvfi_insn_check(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.reset = Signal(1) - self.check = Signal(1) - self.rvfi_valid = Signal(1) - self.rvfi_order = Signal(64) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_trap = Signal(1) - self.rvfi_halt = Signal(1) - self.rvfi_intr = Signal(1) - self.rvfi_mode = Signal(2) - self.rvfi_ixl = Signal(2) - self.rvfi_rs1_addr = Signal(5) - self.rvfi_rs2_addr = Signal(5) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rd_addr = Signal(5) - self.rvfi_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.rvfi_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.reset, - self.check, - self.rvfi_valid, - self.rvfi_order, - self.rvfi_insn, - self.rvfi_trap, - self.rvfi_halt, - self.rvfi_intr, - self.rvfi_mode, - self.rvfi_ixl, - self.rvfi_rs1_addr, - self.rvfi_rs2_addr, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_rd_addr, - self.rvfi_rd_wdata, - self.rvfi_pc_rdata, - self.rvfi_pc_wdata, - self.rvfi_mem_addr, - self.rvfi_mem_rmask, - self.rvfi_mem_wmask, - self.rvfi_mem_rdata, - self.rvfi_mem_wdata - ] - output_ports = [] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - valid = Signal(1) - m.d.comb += valid.eq((~self.reset) & self.rvfi_valid) - insn = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn.eq(self.rvfi_insn) - trap = Signal(1) - m.d.comb += trap.eq(self.rvfi_trap) - halt = Signal(1) - m.d.comb += halt.eq(self.rvfi_halt) - intr = Signal(1) - m.d.comb += intr.eq(self.rvfi_intr) - rs1_addr = Signal(5) - m.d.comb += rs1_addr.eq(self.rvfi_rs1_addr) - rs2_addr = Signal(5) - m.d.comb += rs2_addr.eq(self.rvfi_rs2_addr) - rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += rs1_rdata.eq(self.rvfi_rs1_rdata) - rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += rs2_rdata.eq(self.rvfi_rs2_rdata) - rd_addr = Signal(5) - m.d.comb += rd_addr.eq(self.rvfi_rd_addr) - rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += rd_wdata.eq(self.rvfi_rd_wdata) - pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += pc_rdata.eq(self.rvfi_pc_rdata) - pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += pc_wdata.eq(self.rvfi_pc_wdata) - - mem_addr = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += mem_addr.eq(self.rvfi_mem_addr) - mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - m.d.comb += mem_rmask.eq(self.rvfi_mem_rmask) - mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - m.d.comb += mem_wmask.eq(self.rvfi_mem_wmask) - mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += mem_rdata.eq(self.rvfi_mem_rdata) - mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += mem_wdata.eq(self.rvfi_mem_wdata) - - spec_valid = Signal(1) - spec_trap = Signal(1) - spec_rs1_addr = Signal(5) - spec_rs2_addr = Signal(5) - spec_rd_addr = Signal(5) - spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - - rs1_rdata_or_zero = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += rs1_rdata_or_zero.eq(Mux(spec_rs1_addr != 0, rs1_rdata, 0)) - rs2_rdata_or_zero = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += rs2_rdata_or_zero.eq(Mux(spec_rs2_addr != 0, rs2_rdata, 0)) - - # Change this submodule accordingly to test for different instructions(?) - m.submodules.insn_spec = insn_spec = rvfi_insn_add(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN) - - m.d.comb += insn_spec.rvfi_valid.eq(valid) - m.d.comb += insn_spec.rvfi_insn.eq(insn) - m.d.comb += insn_spec.rvfi_pc_rdata.eq(pc_rdata) - m.d.comb += insn_spec.rvfi_rs1_rdata.eq(rs1_rdata_or_zero) - m.d.comb += insn_spec.rvfi_rs2_rdata.eq(rs2_rdata_or_zero) - m.d.comb += insn_spec.rvfi_mem_rdata.eq(mem_rdata) - - m.d.comb += spec_valid.eq(insn_spec.spec_valid) - m.d.comb += spec_trap.eq(insn_spec.spec_trap) - m.d.comb += spec_rs1_addr.eq(insn_spec.spec_rs1_addr) - m.d.comb += spec_rs2_addr.eq(insn_spec.spec_rs2_addr) - m.d.comb += spec_rd_addr.eq(insn_spec.spec_rd_addr) - m.d.comb += spec_rd_wdata.eq(insn_spec.spec_rd_wdata) - m.d.comb += spec_pc_wdata.eq(insn_spec.spec_pc_wdata) - m.d.comb += spec_mem_addr.eq(insn_spec.spec_mem_addr) - m.d.comb += spec_mem_rmask.eq(insn_spec.spec_mem_rmask) - m.d.comb += spec_mem_wmask.eq(insn_spec.spec_mem_wmask) - m.d.comb += spec_mem_wdata.eq(insn_spec.spec_mem_wdata) - - insn_pma_x = Signal(1) - mem_pma_r = Signal(1) - mem_pma_w = Signal(1) - - mem_log2len = Signal(2) - m.d.comb += mem_log2len.eq(Mux((spec_mem_rmask | spec_mem_wmask) & 0b11110000, 3, Mux((spec_mem_rmask | spec_mem_wmask) & 0b00001100, 2, Mux((spec_mem_rmask | spec_mem_wmask) & 0b00000010, 1, 0)))) - - m.d.comb += insn_pma_x.eq(1) - m.d.comb += mem_pma_r.eq(1) - m.d.comb += mem_pma_w.eq(1) - - mem_access_fault = Signal(1) - m.d.comb += mem_access_fault.eq((spec_mem_rmask & ~mem_pma_r) | (spec_mem_wmask & ~mem_pma_w) | (spec_mem_rmask | spec_mem_wmask)) - - with m.If(~self.reset): - m.d.comb += Cover(spec_valid) - m.d.comb += Cover(spec_valid & ~trap) - m.d.comb += Cover(self.check & spec_valid) - m.d.comb += Cover(self.check & spec_valid & ~trap) - with m.If((~self.reset) & self.check): - m.d.comb += Assume(spec_valid) - - with m.If((~insn_pma_x) | mem_access_fault): - m.d.comb += Assert(trap) - m.d.comb += Assert(rd_addr == 0) - m.d.comb += Assert(rd_wdata == 0) - m.d.comb += Assert(mem_wmask == 0) - with m.Else(): - with m.If(rs1_addr == 0): - m.d.comb += Assert(rs1_rdata == 0) - - with m.If(rs2_addr == 0): - m.d.comb += Assert(rs2_rdata == 0) - - with m.If(~spec_trap): - with m.If(spec_rs1_addr != 0): - m.d.comb += Assert(spec_rs1_addr == rs1_addr) - - with m.If(spec_rs2_addr != 0): - m.d.comb += Assert(spec_rs2_addr == rs2_addr) - - m.d.comb += Assert(spec_rd_addr == rd_addr) - m.d.comb += Assert(spec_rd_wdata == rd_wdata) - m.d.comb += Assert(spec_pc_wdata == pc_wdata) - - with m.If(spec_mem_wmask | spec_mem_rmask): - m.d.comb += Assert(spec_mem_addr == mem_addr) - - for i in range(int(self.RISCV_FORMAL_XLEN // 8)): - with m.If(spec_mem_wmask[i]): - m.d.comb += Assert(mem_wmask[i]) - m.d.comb += Assert(spec_mem_wdata[i*8:i*8+8] == mem_wdata[i*8:i*8+8]) - with m.Elif(mem_wmask[i]): - m.d.comb += Assert(mem_rmask[i]) - m.d.comb += Assert(mem_rdata[i*8:i*8+8] == mem_wdata[i*8:i*8+8]) - with m.If(spec_mem_rmask[i]): - m.d.comb += Assert(mem_rmask[i]) - - - m.d.comb += Assert(spec_trap == trap) - - return m diff --git a/checks/rvfi_liveness_check.py b/checks/rvfi_liveness_check.py deleted file mode 100644 index 29210df..0000000 --- a/checks/rvfi_liveness_check.py +++ /dev/null @@ -1,79 +0,0 @@ -from nmigen import * -from nmigen.hdl.ast import * - -class rvfi_liveness_check(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.reset = Signal(1) - self.trig = Signal(1) - self.check = Signal(1) - self.rvfi_valid = Signal(1) - self.rvfi_order = Signal(64) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_trap = Signal(1) - self.rvfi_halt = Signal(1) - self.rvfi_intr = Signal(1) - self.rvfi_mode = Signal(2) - self.rvfi_ixl = Signal(2) - self.rvfi_rs1_addr = Signal(5) - self.rvfi_rs2_addr = Signal(5) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rd_addr = Signal(5) - self.rvfi_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.rvfi_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.reset, - self.trig, - self.check, - self.rvfi_valid, - self.rvfi_order, - self.rvfi_insn, - self.rvfi_trap, - self.rvfi_halt, - self.rvfi_intr, - self.rvfi_mode, - self.rvfi_ixl, - self.rvfi_rs1_addr, - self.rvfi_rs2_addr, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_rd_addr, - self.rvfi_rd_wdata, - self.rvfi_pc_rdata, - self.rvfi_pc_wdata, - self.rvfi_mem_addr, - self.rvfi_mem_rmask, - self.rvfi_mem_wmask, - self.rvfi_mem_rdata, - self.rvfi_mem_wdata - ] - output_ports = [] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - insn_order = AnyConst(64) - found_next_insn = Signal(1, reset=0) - - with m.If(self.reset): - m.d.sync += found_next_insn.eq(0) - with m.Else(): - with m.If(self.rvfi_valid & (self.rvfi_order == insn_order + 1)): - m.d.sync += found_next_insn.eq(1) - with m.If(self.trig): - m.d.comb += Assume(self.rvfi_valid) - m.d.comb += Assume(~self.rvfi_halt) - m.d.comb += Assume(insn_order == self.rvfi_order) - with m.If(self.check): - m.d.comb += Assert(found_next_insn) - - return m diff --git a/checks/rvfi_pc_bwd_check.py b/checks/rvfi_pc_bwd_check.py deleted file mode 100644 index c025fa0..0000000 --- a/checks/rvfi_pc_bwd_check.py +++ /dev/null @@ -1,82 +0,0 @@ -from nmigen import * -from nmigen.hdl.ast import * - -class rvfi_pc_bwd_check(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.reset = Signal(1) - self.check = Signal(1) - self.rvfi_valid = Signal(1) - self.rvfi_order = Signal(64) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_trap = Signal(1) - self.rvfi_halt = Signal(1) - self.rvfi_intr = Signal(1) - self.rvfi_mode = Signal(2) - self.rvfi_ixl = Signal(2) - self.rvfi_rs1_addr = Signal(5) - self.rvfi_rs2_addr = Signal(5) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rd_addr = Signal(5) - self.rvfi_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.rvfi_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.reset, - self.check, - self.rvfi_valid, - self.rvfi_order, - self.rvfi_insn, - self.rvfi_trap, - self.rvfi_halt, - self.rvfi_intr, - self.rvfi_mode, - self.rvfi_ixl, - self.rvfi_rs1_addr, - self.rvfi_rs2_addr, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_rd_addr, - self.rvfi_rd_wdata, - self.rvfi_pc_rdata, - self.rvfi_pc_wdata, - self.rvfi_mem_addr, - self.rvfi_mem_rmask, - self.rvfi_mem_wmask, - self.rvfi_mem_rdata, - self.rvfi_mem_wdata - ] - output_ports = [] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - insn_order = AnyConst(64) - expect_pc = Signal(self.RISCV_FORMAL_XLEN) - expect_pc_valid = Signal(1, reset=0) - - pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += pc_wdata.eq(self.rvfi_pc_wdata) - - with m.If(self.reset): - m.d.sync += expect_pc_valid.eq(0) - with m.Else(): - with m.If(self.check): - m.d.comb += Assume(self.rvfi_valid) - m.d.comb += Assume(insn_order == self.rvfi_order) - with m.If(expect_pc_valid): - m.d.comb += Assert(expect_pc == pc_wdata) - with m.Else(): - with m.If(self.rvfi_valid & (self.rvfi_order == insn_order + 1)): - m.d.sync += expect_pc.eq(self.rvfi_pc_rdata) - m.d.sync += expect_pc_valid.eq(1) - - return m diff --git a/checks/rvfi_pc_fwd_check.py b/checks/rvfi_pc_fwd_check.py deleted file mode 100644 index 9fa5c61..0000000 --- a/checks/rvfi_pc_fwd_check.py +++ /dev/null @@ -1,82 +0,0 @@ -from nmigen import * -from nmigen.hdl.ast import * - -class rvfi_pc_fwd_check(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.reset = Signal(1) - self.check = Signal(1) - self.rvfi_valid = Signal(1) - self.rvfi_order = Signal(64) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_trap = Signal(1) - self.rvfi_halt = Signal(1) - self.rvfi_intr = Signal(1) - self.rvfi_mode = Signal(2) - self.rvfi_ixl = Signal(2) - self.rvfi_rs1_addr = Signal(5) - self.rvfi_rs2_addr = Signal(5) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rd_addr = Signal(5) - self.rvfi_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.rvfi_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.reset, - self.check, - self.rvfi_valid, - self.rvfi_order, - self.rvfi_insn, - self.rvfi_trap, - self.rvfi_halt, - self.rvfi_intr, - self.rvfi_mode, - self.rvfi_ixl, - self.rvfi_rs1_addr, - self.rvfi_rs2_addr, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_rd_addr, - self.rvfi_rd_wdata, - self.rvfi_pc_rdata, - self.rvfi_pc_wdata, - self.rvfi_mem_addr, - self.rvfi_mem_rmask, - self.rvfi_mem_wmask, - self.rvfi_mem_rdata, - self.rvfi_mem_wdata - ] - output_ports = [] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - insn_order = AnyConst(64) - expect_pc = Signal(self.RISCV_FORMAL_XLEN) - expect_pc_valid = Signal(1, reset=0) - - pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += pc_rdata.eq(self.rvfi_pc_rdata) - - with m.If(self.reset): - m.d.sync += expect_pc_valid.eq(0) - with m.Else(): - with m.If(self.check): - m.d.comb += Assume(self.rvfi_valid) - m.d.comb += Assume(insn_order == self.rvfi_order) - with m.If(expect_pc_valid): - m.d.comb += Assert(expect_pc == pc_rdata) - with m.Else(): - with m.If(self.rvfi_valid & (self.rvfi_order == insn_order - 1)): - m.d.sync += expect_pc.eq(self.rvfi_pc_wdata) - m.d.sync += expect_pc_valid.eq(1) - - return m diff --git a/checks/rvfi_reg_check.py b/checks/rvfi_reg_check.py deleted file mode 100644 index 5347be8..0000000 --- a/checks/rvfi_reg_check.py +++ /dev/null @@ -1,84 +0,0 @@ -from nmigen import * -from nmigen.hdl.ast import * - -class rvfi_reg_check(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.reset = Signal(1) - self.check = Signal(1) - self.rvfi_valid = Signal(1) - self.rvfi_order = Signal(64) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_trap = Signal(1) - self.rvfi_halt = Signal(1) - self.rvfi_intr = Signal(1) - self.rvfi_mode = Signal(2) - self.rvfi_ixl = Signal(2) - self.rvfi_rs1_addr = Signal(5) - self.rvfi_rs2_addr = Signal(5) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rd_addr = Signal(5) - self.rvfi_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.rvfi_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.reset, - self.check, - self.rvfi_valid, - self.rvfi_order, - self.rvfi_insn, - self.rvfi_trap, - self.rvfi_halt, - self.rvfi_intr, - self.rvfi_mode, - self.rvfi_ixl, - self.rvfi_rs1_addr, - self.rvfi_rs2_addr, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_rd_addr, - self.rvfi_rd_wdata, - self.rvfi_pc_rdata, - self.rvfi_pc_wdata, - self.rvfi_mem_addr, - self.rvfi_mem_rmask, - self.rvfi_mem_wmask, - self.rvfi_mem_rdata, - self.rvfi_mem_wdata - ] - output_ports = [] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - insn_order = AnyConst(64) - register_index = AnyConst(5) - register_shadow = Signal(self.RISCV_FORMAL_XLEN, reset=0) - register_written = Signal(1, reset=0) - - with m.If(self.reset): - m.d.sync += register_shadow.eq(0) - m.d.sync += register_written.eq(0) - with m.Else(): - with m.If(self.check): - m.d.comb += Assume(self.rvfi_valid) - m.d.comb += Assume(insn_order == self.rvfi_order) - - with m.If(register_written & (register_index == self.rvfi_rs1_addr)): - m.d.comb += Assert(register_shadow == self.rvfi_rs1_rdata) - with m.If(register_written & (register_index == self.rvfi_rs2_addr)): - m.d.comb += Assert(register_shadow == self.rvfi_rs2_rdata) - with m.Else(): - with m.If(self.rvfi_valid & (self.rvfi_order < insn_order) & (register_index == self.rvfi_rd_addr)): - m.d.sync += register_shadow.eq(self.rvfi_rd_wdata) - m.d.sync += register_written.eq(1) - - return m diff --git a/checks/rvfi_unique_check.py b/checks/rvfi_unique_check.py deleted file mode 100644 index fe73ba5..0000000 --- a/checks/rvfi_unique_check.py +++ /dev/null @@ -1,78 +0,0 @@ -from nmigen import * -from nmigen.hdl.ast import * - -class rvfi_unique_check(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.reset = Signal(1) - self.trig = Signal(1) - self.check = Signal(1) - self.rvfi_valid = Signal(1) - self.rvfi_order = Signal(64) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_trap = Signal(1) - self.rvfi_halt = Signal(1) - self.rvfi_intr = Signal(1) - self.rvfi_mode = Signal(2) - self.rvfi_ixl = Signal(2) - self.rvfi_rs1_addr = Signal(5) - self.rvfi_rs2_addr = Signal(5) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rd_addr = Signal(5) - self.rvfi_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.rvfi_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.reset, - self.trig, - self.check, - self.rvfi_valid, - self.rvfi_order, - self.rvfi_insn, - self.rvfi_trap, - self.rvfi_halt, - self.rvfi_intr, - self.rvfi_mode, - self.rvfi_ixl, - self.rvfi_rs1_addr, - self.rvfi_rs2_addr, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_rd_addr, - self.rvfi_rd_wdata, - self.rvfi_pc_rdata, - self.rvfi_pc_wdata, - self.rvfi_mem_addr, - self.rvfi_mem_rmask, - self.rvfi_mem_wmask, - self.rvfi_mem_rdata, - self.rvfi_mem_wdata - ] - output_ports = [] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - insn_order = AnyConst(64) - found_other_insn = Signal(1, reset=0) - - with m.If(self.reset): - m.d.sync += found_other_insn.eq(0) - with m.Else(): - with m.If(self.rvfi_valid & (self.rvfi_order == insn_order) & ~self.trig): - m.d.sync += found_other_insn.eq(1) - with m.If(self.trig): - m.d.comb += Assume(self.rvfi_valid) - m.d.comb += Assume(insn_order == self.rvfi_order) - with m.If(self.check): - m.d.comb += Assert(~found_other_insn) - - return m diff --git a/insns/README.md b/insns/README.md deleted file mode 100644 index 034ebc4..0000000 --- a/insns/README.md +++ /dev/null @@ -1,28 +0,0 @@ -# RISC-V Instructions - -Refer to the table below for the instructions currently supported. At the time of writing, it covers the instructions in the RV32I base ISA except FENCE, ECALL and EBREAK, as well as the RV32M extension\*. - -| Instruction type | Instructions | -| --- | --- | -| U-type | lui, auipc | -| UJ-type | jal | -| I-type | jalr, lb, lh, lw, lbu, lhu, addi, slti, sltiu, xori, ori, andi | -| SB-type | beq, bne, blt, bge, bltu, bgeu | -| S-type | sb, sh, sw | -| I-type (shift variation) | slli, srli, srai | -| R-type | add, sub, sll, slt, sltu, xor, srl, sra, or, and, mul, mulh, mulhsu, mulhu, div, divu, rem, remu | - -\* Due to limitations with modern solvers, they are sometimes unable to verify assertions involving multiplication and/or division; therefore, the core under test is expected to implement alternative operations for the RV32M extensions for the purposes of formal verification only, replacing multiplication/division operations with addition/subtraction and XORing with selected bitmasks. - -## Caveats - -At the time of writing, the set of instructions supported in this port of riscv-formal is a mere subset of those supported in the original riscv-formal; for example, compressed instructions and 64-bit ISAs/extensions are not supported. Also note that the original riscv-formal contains tunable parameters that have been fixed to certain values in this translation: - -| Parameter from riscv-formal | Fixed value in riscv-formal-nmigen | -| --- | --- | -| `RISCV_FORMAL_ILEN` | 32 | -| `RISCV_FORMAL_XLEN` | 32 | -| `RISCV_FORMAL_CSR_MISA` | undefined | -| `RISCV_FORMAL_COMPRESSED` | undefined | -| `RISCV_FORMAL_ALIGNED_MEM` | undefined | -| `RISCV_FORMAL_ALTOPS` | defined | diff --git a/insns/insn.py b/insns/insn.py deleted file mode 100644 index 4588ff3..0000000 --- a/insns/insn.py +++ /dev/null @@ -1,51 +0,0 @@ -from nmigen import * - -class rvfi_insn(Elaboratable): - def __init__(self): - # Input ports - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(32) - self.rvfi_pc_rdata = Signal(32) - self.rvfi_rs1_rdata = Signal(32) - self.rvfi_rs2_rdata = Signal(32) - self.rvfi_mem_rdata = Signal(32) - - # Output ports - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(32) - self.spec_pc_wdata = Signal(32) - self.spec_mem_addr = Signal(32) - self.spec_mem_rmask = Signal(4) - self.spec_mem_wmask = Signal(4) - self.spec_mem_wdata = Signal(32) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - return m diff --git a/insns/insn_I.py b/insns/insn_I.py deleted file mode 100644 index 3d0c7e3..0000000 --- a/insns/insn_I.py +++ /dev/null @@ -1,38 +0,0 @@ -from insn import * - -class rvfi_insn_I(rvfi_insn): - def __init__(self): - super(rvfi_insn_I, self).__init__() - self.insn_padding = Signal(32) - self.insn_imm = Signal(32) - self.insn_rs1 = Signal(5) - self.insn_funct3 = Signal(3) - self.insn_rd = Signal(5) - self.insn_opcode = Signal(7) - self.misa_ok = Signal(1) - self.ialign16 = Signal(1) - def ports(self): - return super(rvfi_insn_I, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_I, self).elaborate(platform) - - # I-type instruction format - m.d.comb += self.insn_padding.eq(self.rvfi_insn >> 32) - m.d.comb += self.insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32])) - m.d.comb += self.insn_rs1.eq(self.rvfi_insn[15:20]) - m.d.comb += self.insn_funct3.eq(self.rvfi_insn[12:15]) - m.d.comb += self.insn_rd.eq(self.rvfi_insn[7:12]) - m.d.comb += self.insn_opcode.eq(self.rvfi_insn[:7]) - - m.d.comb += self.misa_ok.eq(1) - m.d.comb += self.ialign16.eq(0) - - # default assignments - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_trap.eq(~self.misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_I_shift.py b/insns/insn_I_shift.py deleted file mode 100644 index 45f2819..0000000 --- a/insns/insn_I_shift.py +++ /dev/null @@ -1,38 +0,0 @@ -from insn import * - -class rvfi_insn_I_shift(rvfi_insn): - def __init__(self): - super(rvfi_insn_I_shift, self).__init__() - self.insn_padding = Signal(32) - self.insn_funct6 = Signal(7) - self.insn_shamt = Signal(6) - self.insn_rs1 = Signal(5) - self.insn_funct3 = Signal(3) - self.insn_rd = Signal(5) - self.insn_opcode = Signal(7) - self.misa_ok = Signal(1) - def ports(self): - return super(rvfi_insn_I_shift, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_I_shift, self).elaborate(platform) - - # I-type instruction format (shift variation) - m.d.comb += self.insn_padding.eq(self.rvfi_insn >> 32) - m.d.comb += self.insn_funct6.eq(self.rvfi_insn[26:32]) - m.d.comb += self.insn_shamt.eq(self.rvfi_insn[20:26]) - m.d.comb += self.insn_rs1.eq(self.rvfi_insn[15:20]) - m.d.comb += self.insn_funct3.eq(self.rvfi_insn[12:15]) - m.d.comb += self.insn_rd.eq(self.rvfi_insn[7:12]) - m.d.comb += self.insn_opcode.eq(self.rvfi_insn[:7]) - - m.d.comb += self.misa_ok.eq(1) - - # default assignments - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_trap.eq(~self.misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_R.py b/insns/insn_R.py deleted file mode 100644 index 8fb73fb..0000000 --- a/insns/insn_R.py +++ /dev/null @@ -1,37 +0,0 @@ -from insn import * - -class rvfi_insn_R(rvfi_insn): - def __init__(self): - super(rvfi_insn_R, self).__init__() - self.insn_padding = Signal(32) - self.insn_funct7 = Signal(7) - self.insn_rs2 = Signal(5) - self.insn_rs1 = Signal(5) - self.insn_funct3 = Signal(3) - self.insn_rd = Signal(5) - self.insn_opcode = Signal(7) - self.misa_ok = Signal(1) - def ports(self): - return super(rvfi_insn_R, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_R, self).elaborate(platform) - - # R-type instruction format - m.d.comb += self.insn_padding.eq(self.rvfi_insn >> 32) - m.d.comb += self.insn_funct7.eq(self.rvfi_insn[25:32]) - m.d.comb += self.insn_rs2.eq(self.rvfi_insn[20:25]) - m.d.comb += self.insn_rs1.eq(self.rvfi_insn[15:20]) - m.d.comb += self.insn_funct3.eq(self.rvfi_insn[12:15]) - m.d.comb += self.insn_rd.eq(self.rvfi_insn[7:12]) - m.d.comb += self.insn_opcode.eq(self.rvfi_insn[:7]) - - m.d.comb += self.misa_ok.eq(1) - - # default assignments - m.d.comb += self.spec_trap.eq(~self.misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_S.py b/insns/insn_S.py deleted file mode 100644 index b757fbf..0000000 --- a/insns/insn_S.py +++ /dev/null @@ -1,32 +0,0 @@ -from insn import * -class rvfi_insn_S(rvfi_insn): - def __init__(self): - super(rvfi_insn_S, self).__init__() - self.insn_padding = Signal(32) - self.insn_imm = Signal(32) - self.insn_rs2 = Signal(5) - self.insn_rs1 = Signal(5) - self.insn_funct3 = Signal(3) - self.insn_opcode = Signal(7) - self.misa_ok = Signal(1) - def ports(self): - return super(rvfi_insn_S, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_S, self).elaborate(platform) - - # S-type instruction format - m.d.comb += self.insn_padding.eq(self.rvfi_insn >> 32) - m.d.comb += self.insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[7:12], self.rvfi_insn[25:32]))) - m.d.comb += self.insn_rs2.eq(self.rvfi_insn[20:25]) - m.d.comb += self.insn_rs1.eq(self.rvfi_insn[15:20]) - m.d.comb += self.insn_funct3.eq(self.rvfi_insn[12:15]) - m.d.comb += self.insn_opcode.eq(self.rvfi_insn[:7]) - - m.d.comb += self.misa_ok.eq(1) - - # default assignments - m.d.comb += self.spec_rd_addr.eq(0) - m.d.comb += self.spec_rd_wdata.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - - return m diff --git a/insns/insn_SB.py b/insns/insn_SB.py deleted file mode 100644 index 352f0c6..0000000 --- a/insns/insn_SB.py +++ /dev/null @@ -1,38 +0,0 @@ -from insn import * - -class rvfi_insn_SB(rvfi_insn): - def __init__(self): - super(rvfi_insn_SB, self).__init__() - self.insn_padding = Signal(32) - self.insn_imm = Signal(32) - self.insn_rs2 = Signal(5) - self.insn_rs1 = Signal(5) - self.insn_funct3 = Signal(3) - self.insn_opcode = Signal(7) - self.misa_ok = Signal(1) - self.ialign16 = Signal(1) - def ports(self): - return super(rvfi_insn_SB, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_SB, self).elaborate(platform) - - # SB-type instruction format - m.d.comb += self.insn_padding.eq(self.rvfi_insn >> 32) - m.d.comb += self.insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[8:12], self.rvfi_insn[25:31], self.rvfi_insn[7], self.rvfi_insn[31]) << 1)) - m.d.comb += self.insn_rs2.eq(self.rvfi_insn[20:25]) - m.d.comb += self.insn_rs1.eq(self.rvfi_insn[15:20]) - m.d.comb += self.insn_funct3.eq(self.rvfi_insn[12:15]) - m.d.comb += self.insn_opcode.eq(self.rvfi_insn[:7]) - - m.d.comb += self.misa_ok.eq(1) - m.d.comb += self.ialign16.eq(0) - - # default assignments - m.d.comb += self.spec_rd_addr.eq(0) - m.d.comb += self.spec_rd_wdata.eq(0) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_U.py b/insns/insn_U.py deleted file mode 100644 index aec6828..0000000 --- a/insns/insn_U.py +++ /dev/null @@ -1,33 +0,0 @@ -from insn import * - -class rvfi_insn_U(rvfi_insn): - def __init__(self): - super(rvfi_insn_U, self).__init__() - self.insn_padding = Signal(32) - self.insn_imm = Signal(32) - self.insn_rd = Signal(5) - self.insn_opcode = Signal(7) - self.misa_ok = Signal(1) - def ports(self): - return super(rvfi_insn_U, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_U, self).elaborate(platform) - - # U-type instruction format - m.d.comb += self.insn_padding.eq(self.rvfi_insn >> 32) - m.d.comb += self.insn_imm.eq(Value.as_signed(self.rvfi_insn[12:32] << 12)) - m.d.comb += self.insn_rd.eq(self.rvfi_insn[7:12]) - m.d.comb += self.insn_opcode.eq(self.rvfi_insn[:7]) - - m.d.comb += self.misa_ok.eq(1) - - # Default assignments - m.d.comb += self.spec_rs1_addr.eq(0) - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_trap.eq(~self.misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_UJ.py b/insns/insn_UJ.py deleted file mode 100644 index d5d2b8f..0000000 --- a/insns/insn_UJ.py +++ /dev/null @@ -1,34 +0,0 @@ -from insn import * - -class rvfi_insn_UJ(rvfi_insn): - def __init__(self): - super(rvfi_insn_UJ, self).__init__() - self.insn_padding = Signal(32) - self.insn_imm = Signal(32) - self.insn_rd = Signal(5) - self.insn_opcode = Signal(7) - self.misa_ok = Signal(1) - self.ialign16 = Signal(1) - def ports(self): - return super(rvfi_insn_UJ, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_UJ, self).elaborate(platform) - - # UJ-type instruction format - m.d.comb += self.insn_padding.eq(self.rvfi_insn >> 32) - m.d.comb += self.insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[21:31], self.rvfi_insn[20], self.rvfi_insn[12:20], self.rvfi_insn[31]) << 1)) - m.d.comb += self.insn_rd.eq(self.rvfi_insn[7:12]) - m.d.comb += self.insn_opcode.eq(self.rvfi_insn[:7]) - - m.d.comb += self.misa_ok.eq(1) - m.d.comb += self.ialign16.eq(0) - - # Default assignments - m.d.comb += self.spec_rs1_addr.eq(0) - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_add.py b/insns/insn_add.py deleted file mode 100644 index 58a9300..0000000 --- a/insns/insn_add.py +++ /dev/null @@ -1,21 +0,0 @@ -from insn_R import * - -class rvfi_insn_add(rvfi_insn_R): - def __init__(self): - super(rvfi_insn_add, self).__init__() - def ports(self): - return super(rvfi_insn_add, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_add, self).elaborate(platform) - - # ADD instruction - result = Signal(32) - m.d.comb += result.eq(self.rvfi_rs1_rdata + self.rvfi_rs2_rdata) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000000) & (self.insn_funct3 == 0b000) & (self.insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - return m diff --git a/insns/insn_addi.py b/insns/insn_addi.py deleted file mode 100644 index 70c7537..0000000 --- a/insns/insn_addi.py +++ /dev/null @@ -1,20 +0,0 @@ -from insn_I import * - -class rvfi_insn_addi(rvfi_insn_I): - def __init__(self): - super(rvfi_insn_addi, self).__init__() - def ports(self): - return super(rvfi_insn_addi, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_addi, self).elaborate(platform) - - # ADDI instruction - result = Signal(32) - m.d.comb += result.eq(self.rvfi_rs1_rdata + self.insn_imm) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b000) & (self.insn_opcode == 0b0010011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - return m diff --git a/insns/insn_and.py b/insns/insn_and.py deleted file mode 100644 index 4cf5a52..0000000 --- a/insns/insn_and.py +++ /dev/null @@ -1,21 +0,0 @@ -from insn_R import * - -class rvfi_insn_and(rvfi_insn_R): - def __init__(self): - super(rvfi_insn_and, self).__init__() - def ports(self): - return super(rvfi_insn_and, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_and, self).elaborate(platform) - - # AND instruction - result = Signal(32) - m.d.comb += result.eq(self.rvfi_rs1_rdata & self.rvfi_rs2_rdata) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000000) & (self.insn_funct3 == 0b111) & (self.insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - return m diff --git a/insns/insn_andi.py b/insns/insn_andi.py deleted file mode 100644 index 6d4c0fa..0000000 --- a/insns/insn_andi.py +++ /dev/null @@ -1,20 +0,0 @@ -from insn_I import * - -class rvfi_insn_andi(rvfi_insn_I): - def __init__(self): - super(rvfi_insn_andi, self).__init__() - def ports(self): - return super(rvfi_insn_andi, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_andi, self).elaborate(platform) - - # ANDI instruction - result = Signal(32) - m.d.comb += result.eq(self.rvfi_rs1_rdata & self.insn_imm) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b111) & (self.insn_opcode == 0b0010011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - return m diff --git a/insns/insn_auipc.py b/insns/insn_auipc.py deleted file mode 100644 index 07a9f63..0000000 --- a/insns/insn_auipc.py +++ /dev/null @@ -1,17 +0,0 @@ -from insn_U import * - -class rvfi_insn_auipc(rvfi_insn_U): - def __init__(self): - super(rvfi_insn_auipc, self).__init__() - def ports(self): - return super(rvfi_insn_auipc, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_auipc, self).elaborate(platform) - - # AUIPC instruction - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_opcode == 0b0010111)) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_pc_rdata + self.insn_imm, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - return m diff --git a/insns/insn_beq.py b/insns/insn_beq.py deleted file mode 100644 index 582a331..0000000 --- a/insns/insn_beq.py +++ /dev/null @@ -1,22 +0,0 @@ -from insn_SB import * - -class rvfi_insn_beq(rvfi_insn_SB): - def __init__(self): - super(rvfi_insn_beq, self).__init__() - def ports(self): - return super(rvfi_insn_beq, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_beq, self).elaborate(platform) - - # BEQ instruction - cond = Signal(1) - m.d.comb += cond.eq(self.rvfi_rs1_rdata == self.rvfi_rs2_rdata) - next_pc = Signal(32) - m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4)) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b000) & (self.insn_opcode == 0b1100011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_pc_wdata.eq(next_pc) - m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) - - return m diff --git a/insns/insn_bge.py b/insns/insn_bge.py deleted file mode 100644 index 3309baa..0000000 --- a/insns/insn_bge.py +++ /dev/null @@ -1,22 +0,0 @@ -from insn_SB import * - -class rvfi_insn_bge(rvfi_insn_SB): - def __init__(self): - super(rvfi_insn_bge, self).__init__() - def ports(self): - return super(rvfi_insn_bge, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_bge, self).elaborate(platform) - - # BGE instruction - cond = Signal(1) - m.d.comb += cond.eq(Value.as_signed(self.rvfi_rs1_rdata) >= Value.as_signed(self.rvfi_rs2_rdata)) - next_pc = Signal(32) - m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4)) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b101) & (self.insn_opcode == 0b1100011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_pc_wdata.eq(next_pc) - m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) - - return m diff --git a/insns/insn_bgeu.py b/insns/insn_bgeu.py deleted file mode 100644 index 049be95..0000000 --- a/insns/insn_bgeu.py +++ /dev/null @@ -1,22 +0,0 @@ -from insn_SB import * - -class rvfi_insn_bgeu(rvfi_insn_SB): - def __init__(self): - super(rvfi_insn_bgeu, self).__init__() - def ports(self): - return super(rvfi_insn_bgeu, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_bgeu, self).elaborate(platform) - - # BGEU instruction - cond = Signal(1) - m.d.comb += cond.eq(self.rvfi_rs1_rdata >= self.rvfi_rs2_rdata) - next_pc = Signal(32) - m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4)) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b111) & (self.insn_opcode == 0b1100011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_pc_wdata.eq(next_pc) - m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) - - return m diff --git a/insns/insn_blt.py b/insns/insn_blt.py deleted file mode 100644 index 471f032..0000000 --- a/insns/insn_blt.py +++ /dev/null @@ -1,22 +0,0 @@ -from insn_SB import * - -class rvfi_insn_blt(rvfi_insn_SB): - def __init__(self): - super(rvfi_insn_blt, self).__init__() - def ports(self): - return super(rvfi_insn_blt, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_blt, self).elaborate(platform) - - # BLT instruction - cond = Signal(1) - m.d.comb += cond.eq(Value.as_signed(self.rvfi_rs1_rdata) < Value.as_signed(self.rvfi_rs2_rdata)) - next_pc = Signal(32) - m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4)) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b100) & (self.insn_opcode == 0b1100011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_pc_wdata.eq(next_pc) - m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) - - return m diff --git a/insns/insn_bltu.py b/insns/insn_bltu.py deleted file mode 100644 index 16dd557..0000000 --- a/insns/insn_bltu.py +++ /dev/null @@ -1,22 +0,0 @@ -from insn_SB import * - -class rvfi_insn_bltu(rvfi_insn_SB): - def __init__(self): - super(rvfi_insn_bltu, self).__init__() - def ports(self): - return super(rvfi_insn_bltu, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_bltu, self).elaborate(platform) - - # BLTU instruction - cond = Signal(1) - m.d.comb += cond.eq(self.rvfi_rs1_rdata < self.rvfi_rs2_rdata) - next_pc = Signal(32) - m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4)) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b110) & (self.insn_opcode == 0b1100011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_pc_wdata.eq(next_pc) - m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) - - return m diff --git a/insns/insn_bne.py b/insns/insn_bne.py deleted file mode 100644 index 6c273f0..0000000 --- a/insns/insn_bne.py +++ /dev/null @@ -1,22 +0,0 @@ -from insn_SB import * - -class rvfi_insn_bne(rvfi_insn_SB): - def __init__(self): - super(rvfi_insn_bne, self).__init__() - def ports(self): - return super(rvfi_insn_bne, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_bne, self).elaborate(platform) - - # BNE instruction - cond = Signal(1) - m.d.comb += cond.eq(self.rvfi_rs1_rdata != self.rvfi_rs2_rdata) - next_pc = Signal(32) - m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4)) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b001) & (self.insn_opcode == 0b1100011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_pc_wdata.eq(next_pc) - m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) - - return m diff --git a/insns/insn_div.py b/insns/insn_div.py deleted file mode 100644 index 2cd2523..0000000 --- a/insns/insn_div.py +++ /dev/null @@ -1,23 +0,0 @@ -from insn_R import * - -class rvfi_insn_div(rvfi_insn_R): - def __init__(self): - super(rvfi_insn_div, self).__init__() - def ports(self): - return super(rvfi_insn_div, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_div, self).elaborate(platform) - - # DIV instruction - altops_bitmask = Signal(32) - m.d.comb += altops_bitmask.eq(0x29bbf66f7f8529ec) - result = Signal(32) - m.d.comb += result.eq((self.rvfi_rs1_rdata - self.rvfi_rs2_rdata) ^ altops_bitmask) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000001) & (self.insn_funct3 == 0b100) & (self.insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - return m diff --git a/insns/insn_divu.py b/insns/insn_divu.py deleted file mode 100644 index 454eb00..0000000 --- a/insns/insn_divu.py +++ /dev/null @@ -1,23 +0,0 @@ -from insn_R import * - -class rvfi_insn_divu(rvfi_insn_R): - def __init__(self): - super(rvfi_insn_divu, self).__init__() - def ports(self): - return super(rvfi_insn_divu, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_divu, self).elaborate(platform) - - # DIVU instruction - altops_bitmask = Signal(32) - m.d.comb += altops_bitmask.eq(0x8c629acb10e8fd70) - result = Signal(32) - m.d.comb += result.eq((self.rvfi_rs1_rdata - self.rvfi_rs2_rdata) ^ altops_bitmask) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000001) & (self.insn_funct3 == 0b101) & (self.insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - return m diff --git a/insns/insn_jal.py b/insns/insn_jal.py deleted file mode 100644 index c95cb14..0000000 --- a/insns/insn_jal.py +++ /dev/null @@ -1,20 +0,0 @@ -from insn_UJ import * - -class rvfi_insn_jal(rvfi_insn_UJ): - def __init__(self): - super(rvfi_insn_jal, self).__init__() - def ports(self): - return super(rvfi_insn_jal, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_jal, self).elaborate(platform) - - # JAL instruction - next_pc = Signal(32) - m.d.comb += next_pc.eq(self.rvfi_pc_rdata + self.insn_imm) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_opcode == 0b1101111)) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_pc_rdata + 4, 0)) - m.d.comb += self.spec_pc_wdata.eq(next_pc) - m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) - - return m diff --git a/insns/insn_jalr.py b/insns/insn_jalr.py deleted file mode 100644 index 56dddd0..0000000 --- a/insns/insn_jalr.py +++ /dev/null @@ -1,21 +0,0 @@ -from insn_I import * - -class rvfi_insn_jalr(rvfi_insn_I): - def __init__(self): - super(rvfi_insn_jalr, self).__init__() - def ports(self): - return super(rvfi_insn_jalr, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_jalr, self).elaborate(platform) - - # JALR instruction - next_pc = Signal(32) - m.d.comb += next_pc.eq((self.rvfi_rs1_rdata + self.insn_imm) & ~1) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b000) & (self.insn_opcode == 0b1100111)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_pc_rdata + 4, 0)) - m.d.comb += self.spec_pc_wdata.eq(next_pc) - m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) - - return m diff --git a/insns/insn_lb.py b/insns/insn_lb.py deleted file mode 100644 index 4c3fba6..0000000 --- a/insns/insn_lb.py +++ /dev/null @@ -1,25 +0,0 @@ -from insn_I import * - -class rvfi_insn_lb(rvfi_insn_I): - def __init__(self): - super(rvfi_insn_lb, self).__init__() - def ports(self): - return super(rvfi_insn_lb, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_lb, self).elaborate(platform) - - # LB instruction - addr = Signal(32) - m.d.comb += addr.eq(self.rvfi_rs1_rdata + self.insn_imm) - result = Signal(8) - m.d.comb += result.eq(self.rvfi_mem_rdata) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (self.insn_funct3 == 0b000) & (self.insn_opcode == 0b0000011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_mem_addr.eq(addr) - m.d.comb += self.spec_mem_rmask.eq((1 << 1) - 1) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, Value.as_signed(result), 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - m.d.comb += self.spec_trap.eq(~self.misa_ok) - - return m diff --git a/insns/insn_lbu.py b/insns/insn_lbu.py deleted file mode 100644 index 3961c99..0000000 --- a/insns/insn_lbu.py +++ /dev/null @@ -1,25 +0,0 @@ -from insn_I import * - -class rvfi_insn_lbu(rvfi_insn_I): - def __init__(self): - super(rvfi_insn_lbu, self).__init__() - def ports(self): - return super(rvfi_insn_lbu, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_lbu, self).elaborate(platform) - - # LBU instruction - addr = Signal(32) - m.d.comb += addr.eq(self.rvfi_rs1_rdata + self.insn_imm) - result = Signal(8) - m.d.comb += result.eq(self.rvfi_mem_rdata) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (self.insn_funct3 == 0b100) & (self.insn_opcode == 0b0000011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_mem_addr.eq(addr) - m.d.comb += self.spec_mem_rmask.eq((1 << 1) - 1) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - m.d.comb += self.spec_trap.eq(~self.misa_ok) - - return m diff --git a/insns/insn_lh.py b/insns/insn_lh.py deleted file mode 100644 index 34c7f93..0000000 --- a/insns/insn_lh.py +++ /dev/null @@ -1,25 +0,0 @@ -from insn_I import * - -class rvfi_insn_lh(rvfi_insn_I): - def __init__(self): - super(rvfi_insn_lh, self).__init__() - def ports(self): - return super(rvfi_insn_lh, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_lh, self).elaborate(platform) - - # LH instruction - addr = Signal(32) - m.d.comb += addr.eq(self.rvfi_rs1_rdata + self.insn_imm) - result = Signal(16) - m.d.comb += result.eq(self.rvfi_mem_rdata) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (self.insn_funct3 == 0b001) & (self.insn_opcode == 0b0000011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_mem_addr.eq(addr) - m.d.comb += self.spec_mem_rmask.eq((1 << 2) - 1) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, Value.as_signed(result), 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - m.d.comb += self.spec_trap.eq(~self.misa_ok) - - return m diff --git a/insns/insn_lhu.py b/insns/insn_lhu.py deleted file mode 100644 index b050668..0000000 --- a/insns/insn_lhu.py +++ /dev/null @@ -1,25 +0,0 @@ -from insn_I import * - -class rvfi_insn_lhu(rvfi_insn_I): - def __init__(self): - super(rvfi_insn_lhu, self).__init__() - def ports(self): - return super(rvfi_insn_lhu, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_lhu, self).elaborate(platform) - - # LHU instruction - addr = Signal(32) - m.d.comb += addr.eq(self.rvfi_rs1_rdata + self.insn_imm) - result = Signal(16) - m.d.comb += result.eq(self.rvfi_mem_rdata) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (self.insn_funct3 == 0b101) & (self.insn_opcode == 0b0000011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_mem_addr.eq(addr) - m.d.comb += self.spec_mem_rmask.eq((1 << 2) - 1) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - m.d.comb += self.spec_trap.eq(~self.misa_ok) - - return m diff --git a/insns/insn_lui.py b/insns/insn_lui.py deleted file mode 100644 index 42aa764..0000000 --- a/insns/insn_lui.py +++ /dev/null @@ -1,17 +0,0 @@ -from insn_U import * - -class rvfi_insn_lui(rvfi_insn_U): - def __init__(self): - super(rvfi_insn_lui, self).__init__() - def ports(self): - return super(rvfi_insn_lui, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_lui, self).elaborate(platform) - - # LUI instruction - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_opcode == 0b0110111)) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.insn_imm, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - return m diff --git a/insns/insn_lw.py b/insns/insn_lw.py deleted file mode 100644 index 5e956e9..0000000 --- a/insns/insn_lw.py +++ /dev/null @@ -1,25 +0,0 @@ -from insn_I import * - -class rvfi_insn_lw(rvfi_insn_I): - def __init__(self): - super(rvfi_insn_lw, self).__init__() - def ports(self): - return super(rvfi_insn_lw, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_lw, self).elaborate(platform) - - # LW instruction - addr = Signal(32) - m.d.comb += addr.eq(self.rvfi_rs1_rdata + self.insn_imm) - result = Signal(32) - m.d.comb += result.eq(self.rvfi_mem_rdata) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (self.insn_funct3 == 0b010) & (self.insn_opcode == 0b0000011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_mem_addr.eq(addr) - m.d.comb += self.spec_mem_rmask.eq((1 << 4) - 1) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, Value.as_signed(result), 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - m.d.comb += self.spec_trap.eq(~self.misa_ok) - - return m diff --git a/insns/insn_mul.py b/insns/insn_mul.py deleted file mode 100644 index 5f250b1..0000000 --- a/insns/insn_mul.py +++ /dev/null @@ -1,23 +0,0 @@ -from insn_R import * - -class rvfi_insn_mul(rvfi_insn_R): - def __init__(self): - super(rvfi_insn_mul, self).__init__() - def ports(self): - return super(rvfi_insn_mul, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_mul, self).elaborate(platform) - - # MUL instruction - altops_bitmask = Signal(32) - m.d.comb += altops_bitmask.eq(0x2cdf52a55876063e) - result = Signal(32) - m.d.comb += result.eq((self.rvfi_rs1_rdata + self.rvfi_rs2_rdata) ^ altops_bitmask) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000001) & (self.insn_funct3 == 0b000) & (self.insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - return m diff --git a/insns/insn_mulh.py b/insns/insn_mulh.py deleted file mode 100644 index 81010c2..0000000 --- a/insns/insn_mulh.py +++ /dev/null @@ -1,23 +0,0 @@ -from insn_R import * - -class rvfi_insn_mulh(rvfi_insn_R): - def __init__(self): - super(rvfi_insn_mulh, self).__init__() - def ports(self): - return super(rvfi_insn_mulh, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_mulh, self).elaborate(platform) - - # MULH instruction - altops_bitmask = Signal(32) - m.d.comb += altops_bitmask.eq(0x15d01651f6583fb7) - result = Signal(32) - m.d.comb += result.eq((self.rvfi_rs1_rdata + self.rvfi_rs2_rdata) ^ altops_bitmask) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000001) & (self.insn_funct3 == 0b001) & (self.insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - return m diff --git a/insns/insn_mulhsu.py b/insns/insn_mulhsu.py deleted file mode 100644 index 18857d8..0000000 --- a/insns/insn_mulhsu.py +++ /dev/null @@ -1,23 +0,0 @@ -from insn_R import * - -class rvfi_insn_mulhsu(rvfi_insn_R): - def __init__(self): - super(rvfi_insn_mulhsu, self).__init__() - def ports(self): - return super(rvfi_insn_mulhsu, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_mulhsu, self).elaborate(platform) - - # MULHSU instruction - altops_bitmask = Signal(32) - m.d.comb += altops_bitmask.eq(0xea3969edecfbe137) - result = Signal(32) - m.d.comb += result.eq((self.rvfi_rs1_rdata - self.rvfi_rs2_rdata) ^ altops_bitmask) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000001) & (self.insn_funct3 == 0b010) & (self.insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - return m diff --git a/insns/insn_mulhu.py b/insns/insn_mulhu.py deleted file mode 100644 index efeaed4..0000000 --- a/insns/insn_mulhu.py +++ /dev/null @@ -1,23 +0,0 @@ -from insn_R import * - -class rvfi_insn_mulhu(rvfi_insn_R): - def __init__(self): - super(rvfi_insn_mulhu, self).__init__() - def ports(self): - return super(rvfi_insn_mulhu, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_mulhu, self).elaborate(platform) - - # MULHU instruction - altops_bitmask = Signal(32) - m.d.comb += altops_bitmask.eq(0xd13db50d949ce5e8) - result = Signal(32) - m.d.comb += result.eq((self.rvfi_rs1_rdata + self.rvfi_rs2_rdata) ^ altops_bitmask) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000001) & (self.insn_funct3 == 0b011) & (self.insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - return m diff --git a/insns/insn_or.py b/insns/insn_or.py deleted file mode 100644 index ad09251..0000000 --- a/insns/insn_or.py +++ /dev/null @@ -1,21 +0,0 @@ -from insn_R import * - -class rvfi_insn_or(rvfi_insn_R): - def __init__(self): - super(rvfi_insn_or, self).__init__() - def ports(self): - return super(rvfi_insn_or, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_or, self).elaborate(platform) - - # OR instruction - result = Signal(32) - m.d.comb += result.eq(self.rvfi_rs1_rdata | self.rvfi_rs2_rdata) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000000) & (self.insn_funct3 == 0b110) & (self.insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - return m diff --git a/insns/insn_ori.py b/insns/insn_ori.py deleted file mode 100644 index 3d4bb82..0000000 --- a/insns/insn_ori.py +++ /dev/null @@ -1,20 +0,0 @@ -from insn_I import * - -class rvfi_insn_ori(rvfi_insn_I): - def __init__(self): - super(rvfi_insn_ori, self).__init__() - def ports(self): - return super(rvfi_insn_ori, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_ori, self).elaborate(platform) - - # ORI instruction - result = Signal(32) - m.d.comb += result.eq(self.rvfi_rs1_rdata | self.insn_imm) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b110) & (self.insn_opcode == 0b0010011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - return m diff --git a/insns/insn_rem.py b/insns/insn_rem.py deleted file mode 100644 index b2efb57..0000000 --- a/insns/insn_rem.py +++ /dev/null @@ -1,23 +0,0 @@ -from insn_R import * - -class rvfi_insn_rem(rvfi_insn_R): - def __init__(self): - super(rvfi_insn_rem, self).__init__() - def ports(self): - return super(rvfi_insn_rem, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_rem, self).elaborate(platform) - - # REM instruction - altops_bitmask = Signal(32) - m.d.comb += altops_bitmask.eq(0xf5b7d8538da68fa5) - result = Signal(32) - m.d.comb += result.eq((self.rvfi_rs1_rdata - self.rvfi_rs2_rdata) ^ altops_bitmask) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000001) & (self.insn_funct3 == 0b110) & (self.insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - return m diff --git a/insns/insn_remu.py b/insns/insn_remu.py deleted file mode 100644 index eb50e4d..0000000 --- a/insns/insn_remu.py +++ /dev/null @@ -1,23 +0,0 @@ -from insn_R import * - -class rvfi_insn_remu(rvfi_insn_R): - def __init__(self): - super(rvfi_insn_remu, self).__init__() - def ports(self): - return super(rvfi_insn_remu, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_remu, self).elaborate(platform) - - # REMU instruction - altops_bitmask = Signal(32) - m.d.comb += altops_bitmask.eq(0xbc4402413138d0e1) - result = Signal(32) - m.d.comb += result.eq((self.rvfi_rs1_rdata - self.rvfi_rs2_rdata) ^ altops_bitmask) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000001) & (self.insn_funct3 == 0b111) & (self.insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - return m diff --git a/insns/insn_sb.py b/insns/insn_sb.py deleted file mode 100644 index a423dc4..0000000 --- a/insns/insn_sb.py +++ /dev/null @@ -1,23 +0,0 @@ -from insn_S import * - -class rvfi_insn_sb(rvfi_insn_S): - def __init__(self): - super(rvfi_insn_sb, self).__init__() - def ports(self): - return super(rvfi_insn_sb, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_sb, self).elaborate(platform) - - # SB instruction - addr = Signal(32) - m.d.comb += addr.eq(self.rvfi_rs1_rdata + self.insn_imm) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b000) & (self.insn_opcode == 0b0100011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_mem_addr.eq(addr) - m.d.comb += self.spec_mem_wmask.eq((1 << 1) - 1) - m.d.comb += self.spec_mem_wdata.eq(self.rvfi_rs2_rdata) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - m.d.comb += self.spec_trap.eq(~self.misa_ok) - - return m diff --git a/insns/insn_sh.py b/insns/insn_sh.py deleted file mode 100644 index 1a246c5..0000000 --- a/insns/insn_sh.py +++ /dev/null @@ -1,23 +0,0 @@ -from insn_S import * - -class rvfi_insn_sh(rvfi_insn_S): - def __init__(self): - super(rvfi_insn_sh, self).__init__() - def ports(self): - return super(rvfi_insn_sh, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_sh, self).elaborate(platform) - - # SH instruction - addr = Signal(32) - m.d.comb += addr.eq(self.rvfi_rs1_rdata + self.insn_imm) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b001) & (self.insn_opcode == 0b0100011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_mem_addr.eq(addr) - m.d.comb += self.spec_mem_wmask.eq((1 << 2) - 1) - m.d.comb += self.spec_mem_wdata.eq(self.rvfi_rs2_rdata) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - m.d.comb += self.spec_trap.eq(~self.misa_ok) - - return m diff --git a/insns/insn_sll.py b/insns/insn_sll.py deleted file mode 100644 index 5158983..0000000 --- a/insns/insn_sll.py +++ /dev/null @@ -1,23 +0,0 @@ -from insn_R import * - -class rvfi_insn_sll(rvfi_insn_R): - def __init__(self): - super(rvfi_insn_sll, self).__init__() - def ports(self): - return super(rvfi_insn_sll, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_sll, self).elaborate(platform) - - # SLL instruction - shamt = Signal(6) - m.d.comb += shamt.eq(self.rvfi_rs2_rdata[:5]) - result = Signal(32) - m.d.comb += result.eq(self.rvfi_rs1_rdata << shamt) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000000) & (self.insn_funct3 == 0b001) & (self.insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - return m diff --git a/insns/insn_slli.py b/insns/insn_slli.py deleted file mode 100644 index 6d18539..0000000 --- a/insns/insn_slli.py +++ /dev/null @@ -1,20 +0,0 @@ -from insn_I_shift import * - -class rvfi_insn_slli(rvfi_insn_I_shift): - def __init__(self): - super(rvfi_insn_slli, self).__init__() - def ports(self): - return super(rvfi_insn_slli, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_slli, self).elaborate(platform) - - # SLLI instruction - result = Signal(32) - m.d.comb += result.eq(self.rvfi_rs1_rdata << self.insn_shamt) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct6 == 0b000000) & (self.insn_funct3 == 0b001) & (self.insn_opcode == 0b0010011) & (~self.insn_shamt[5])) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - return m diff --git a/insns/insn_slt.py b/insns/insn_slt.py deleted file mode 100644 index 667255c..0000000 --- a/insns/insn_slt.py +++ /dev/null @@ -1,21 +0,0 @@ -from insn_R import * - -class rvfi_insn_slt(rvfi_insn_R): - def __init__(self): - super(rvfi_insn_slt, self).__init__() - def ports(self): - return super(rvfi_insn_slt, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_slt, self).elaborate(platform) - - # SLT instruction - result = Signal(32) - m.d.comb += result.eq(Value.as_signed(self.rvfi_rs1_rdata) < Value.as_signed(self.rvfi_rs2_rdata)) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000000) & (self.insn_funct3 == 0b010) & (self.insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - return m diff --git a/insns/insn_slti.py b/insns/insn_slti.py deleted file mode 100644 index a84f502..0000000 --- a/insns/insn_slti.py +++ /dev/null @@ -1,20 +0,0 @@ -from insn_I import * - -class rvfi_insn_slti(rvfi_insn_I): - def __init__(self): - super(rvfi_insn_slti, self).__init__() - def ports(self): - return super(rvfi_insn_slti, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_slti, self).elaborate(platform) - - # SLTI instruction - result = Signal(32) - m.d.comb += result.eq(Value.as_signed(self.rvfi_rs1_rdata) < Value.as_signed(self.insn_imm)) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b010) & (self.insn_opcode == 0b0010011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - return m diff --git a/insns/insn_sltiu.py b/insns/insn_sltiu.py deleted file mode 100644 index 717dfef..0000000 --- a/insns/insn_sltiu.py +++ /dev/null @@ -1,20 +0,0 @@ -from insn_I import * - -class rvfi_insn_sltiu(rvfi_insn_I): - def __init__(self): - super(rvfi_insn_sltiu, self).__init__() - def ports(self): - return super(rvfi_insn_sltiu, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_sltiu, self).elaborate(platform) - - # SLTIU instruction - result = Signal(32) - m.d.comb += result.eq(self.rvfi_rs1_rdata < self.insn_imm) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b011) & (self.insn_opcode == 0b0010011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - return m diff --git a/insns/insn_sltu.py b/insns/insn_sltu.py deleted file mode 100644 index 4f45aa4..0000000 --- a/insns/insn_sltu.py +++ /dev/null @@ -1,21 +0,0 @@ -from insn_R import * - -class rvfi_insn_sltu(rvfi_insn_R): - def __init__(self): - super(rvfi_insn_sltu, self).__init__() - def ports(self): - return super(rvfi_insn_sltu, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_sltu, self).elaborate(platform) - - # SLTU instruction - result = Signal(32) - m.d.comb += result.eq(self.rvfi_rs1_rdata < self.rvfi_rs2_rdata) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000000) & (self.insn_funct3 == 0b011) & (self.insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - return m diff --git a/insns/insn_sra.py b/insns/insn_sra.py deleted file mode 100644 index c3075d9..0000000 --- a/insns/insn_sra.py +++ /dev/null @@ -1,23 +0,0 @@ -from insn_R import * - -class rvfi_insn_sra(rvfi_insn_R): - def __init__(self): - super(rvfi_insn_sra, self).__init__() - def ports(self): - return super(rvfi_insn_sra, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_sra, self).elaborate(platform) - - # SRA instruction - shamt = Signal(6) - m.d.comb += shamt.eq(self.rvfi_rs2_rdata[:5]) - result = Signal(32) - m.d.comb += result.eq((self.rvfi_rs1_rdata >> shamt) | (-(self.rvfi_rs1_rdata < 0) << (32 - shamt))) # https://stackoverflow.com/a/25207042 - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0100000) & (self.insn_funct3 == 0b101) & (self.insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - return m diff --git a/insns/insn_srai.py b/insns/insn_srai.py deleted file mode 100644 index ad17861..0000000 --- a/insns/insn_srai.py +++ /dev/null @@ -1,20 +0,0 @@ -from insn_I_shift import * - -class rvfi_insn_srai(rvfi_insn_I_shift): - def __init__(self): - super(rvfi_insn_srai, self).__init__() - def ports(self): - return super(rvfi_insn_srai, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_srai, self).elaborate(platform) - - # SRAI instruction - result = Signal(32) - m.d.comb += result.eq((self.rvfi_rs1_rdata >> self.insn_shamt) | (-(self.rvfi_rs1_rdata < 0) << (32 - self.insn_shamt))) # https://stackoverflow.com/a/25207042 - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct6 == 0b010000) & (self.insn_funct3 == 0b101) & (self.insn_opcode == 0b0010011) & (~self.insn_shamt[5])) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - return m diff --git a/insns/insn_srl.py b/insns/insn_srl.py deleted file mode 100644 index a03f8f1..0000000 --- a/insns/insn_srl.py +++ /dev/null @@ -1,23 +0,0 @@ -from insn_R import * - -class rvfi_insn_srl(rvfi_insn_R): - def __init__(self): - super(rvfi_insn_srl, self).__init__() - def ports(self): - return super(rvfi_insn_srl, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_srl, self).elaborate(platform) - - # SRL instruction - shamt = Signal(6) - m.d.comb += shamt.eq(self.rvfi_rs2_rdata[:5]) - result = Signal(32) - m.d.comb += result.eq(self.rvfi_rs1_rdata >> shamt) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000000) & (self.insn_funct3 == 0b101) & (self.insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - return m diff --git a/insns/insn_srli.py b/insns/insn_srli.py deleted file mode 100644 index f239860..0000000 --- a/insns/insn_srli.py +++ /dev/null @@ -1,20 +0,0 @@ -from insn_I_shift import * - -class rvfi_insn_srli(rvfi_insn_I_shift): - def __init__(self): - super(rvfi_insn_srli, self).__init__() - def ports(self): - return super(rvfi_insn_srli, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_srli, self).elaborate(platform) - - # SRLI instruction - result = Signal(32) - m.d.comb += result.eq(self.rvfi_rs1_rdata >> self.insn_shamt) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct6 == 0b000000) & (self.insn_funct3 == 0b101) & (self.insn_opcode == 0b0010011) & (~self.insn_shamt[5])) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - return m diff --git a/insns/insn_sub.py b/insns/insn_sub.py deleted file mode 100644 index 20c394a..0000000 --- a/insns/insn_sub.py +++ /dev/null @@ -1,21 +0,0 @@ -from insn_R import * - -class rvfi_insn_sub(rvfi_insn_R): - def __init__(self): - super(rvfi_insn_sub, self).__init__() - def ports(self): - return super(rvfi_insn_sub, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_sub, self).elaborate(platform) - - # SUB instruction - result = Signal(32) - m.d.comb += result.eq(self.rvfi_rs1_rdata - self.rvfi_rs2_rdata) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0100000) & (self.insn_funct3 == 0b000) & (self.insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - return m diff --git a/insns/insn_sw.py b/insns/insn_sw.py deleted file mode 100644 index cb02983..0000000 --- a/insns/insn_sw.py +++ /dev/null @@ -1,23 +0,0 @@ -from insn_S import * - -class rvfi_insn_sw(rvfi_insn_S): - def __init__(self): - super(rvfi_insn_sw, self).__init__() - def ports(self): - return super(rvfi_insn_sw, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_sw, self).elaborate(platform) - - # SW instruction - addr = Signal(32) - m.d.comb += addr.eq(self.rvfi_rs1_rdata + self.insn_imm) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b010) & (self.insn_opcode == 0b0100011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_mem_addr.eq(addr) - m.d.comb += self.spec_mem_wmask.eq((1 << 4) - 1) - m.d.comb += self.spec_mem_wdata.eq(self.rvfi_rs2_rdata) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - m.d.comb += self.spec_trap.eq(~self.misa_ok) - - return m diff --git a/insns/insn_types.md b/insns/insn_types.md deleted file mode 100644 index 5228a1f..0000000 --- a/insns/insn_types.md +++ /dev/null @@ -1,11 +0,0 @@ -# RV32IM Instruction Types - -| Instruction type | Instructions | -| --- | --- | -| U-type | lui, auipc | -| UJ-type | jal | -| I-type | jalr, lb, lh, lw, lbu, lhu, addi, slti, sltiu, xori, ori, andi | -| SB-type | beq, bne, blt, bge, bltu, bgeu | -| S-type | sb, sh, sw | -| I-type (shift variation) | slli, srli, srai | -| R-type | add, sub, sll, slt, sltu, xor, srl, sra, or, and, mul, mulh, mulhsu, mulhu, div, divu, rem, remu | diff --git a/insns/insn_xor.py b/insns/insn_xor.py deleted file mode 100644 index c332429..0000000 --- a/insns/insn_xor.py +++ /dev/null @@ -1,21 +0,0 @@ -from insn_R import * - -class rvfi_insn_xor(rvfi_insn_R): - def __init__(self): - super(rvfi_insn_xor, self).__init__() - def ports(self): - return super(rvfi_insn_xor, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_xor, self).elaborate(platform) - - # XOR instruction - result = Signal(32) - m.d.comb += result.eq(self.rvfi_rs1_rdata ^ self.rvfi_rs2_rdata) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000000) & (self.insn_funct3 == 0b100) & (self.insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - return m diff --git a/insns/insn_xori.py b/insns/insn_xori.py deleted file mode 100644 index 647067d..0000000 --- a/insns/insn_xori.py +++ /dev/null @@ -1,20 +0,0 @@ -from insn_I import * - -class rvfi_insn_xori(rvfi_insn_I): - def __init__(self): - super(rvfi_insn_xori, self).__init__() - def ports(self): - return super(rvfi_insn_xori, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_xori, self).elaborate(platform) - - # XORI instruction - result = Signal(32) - m.d.comb += result.eq(self.rvfi_rs1_rdata ^ self.insn_imm) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b100) & (self.insn_opcode == 0b0010011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - return m diff --git a/insns/isa_rv32i.py b/insns/isa_rv32i.py deleted file mode 100644 index 3ef25e4..0000000 --- a/insns/isa_rv32i.py +++ /dev/null @@ -1,1211 +0,0 @@ -# Generated by isa_rv32i_gen.py -from nmigen import * -from insn_lui import * -from insn_auipc import * -from insn_jal import * -from insn_jalr import * -from insn_beq import * -from insn_bne import * -from insn_blt import * -from insn_bge import * -from insn_bltu import * -from insn_bgeu import * -from insn_lb import * -from insn_lh import * -from insn_lw import * -from insn_lbu import * -from insn_lhu import * -from insn_sb import * -from insn_sh import * -from insn_sw import * -from insn_addi import * -from insn_slti import * -from insn_sltiu import * -from insn_xori import * -from insn_ori import * -from insn_andi import * -from insn_slli import * -from insn_srli import * -from insn_srai import * -from insn_add import * -from insn_sub import * -from insn_sll import * -from insn_slt import * -from insn_sltu import * -from insn_xor import * -from insn_srl import * -from insn_sra import * -from insn_or import * -from insn_and import * - -class rvfi_isa_rv32i(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - spec_insn_lui_valid = Signal(1) - spec_insn_lui_trap = Signal(1) - spec_insn_lui_rs1_addr = Signal(5) - spec_insn_lui_rs2_addr = Signal(5) - spec_insn_lui_rd_addr = Signal(5) - spec_insn_lui_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lui_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lui_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lui_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_lui_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_lui_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_lui = insn_lui = rvfi_insn_lui() - m.d.comb += insn_lui.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_lui.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_lui.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_lui.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_lui.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_lui.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_lui_valid.eq(insn_lui.spec_valid) - m.d.comb += spec_insn_lui_trap.eq(insn_lui.spec_trap) - m.d.comb += spec_insn_lui_rs1_addr.eq(insn_lui.spec_rs1_addr) - m.d.comb += spec_insn_lui_rs2_addr.eq(insn_lui.spec_rs2_addr) - m.d.comb += spec_insn_lui_rd_addr.eq(insn_lui.spec_rd_addr) - m.d.comb += spec_insn_lui_rd_wdata.eq(insn_lui.spec_rd_wdata) - m.d.comb += spec_insn_lui_pc_wdata.eq(insn_lui.spec_pc_wdata) - m.d.comb += spec_insn_lui_mem_addr.eq(insn_lui.spec_mem_addr) - m.d.comb += spec_insn_lui_mem_rmask.eq(insn_lui.spec_mem_rmask) - m.d.comb += spec_insn_lui_mem_wmask.eq(insn_lui.spec_mem_wmask) - m.d.comb += spec_insn_lui_mem_wdata.eq(insn_lui.spec_mem_wdata) - - spec_insn_auipc_valid = Signal(1) - spec_insn_auipc_trap = Signal(1) - spec_insn_auipc_rs1_addr = Signal(5) - spec_insn_auipc_rs2_addr = Signal(5) - spec_insn_auipc_rd_addr = Signal(5) - spec_insn_auipc_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_auipc_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_auipc_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_auipc_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_auipc_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_auipc_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_auipc = insn_auipc = rvfi_insn_auipc() - m.d.comb += insn_auipc.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_auipc.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_auipc.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_auipc.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_auipc.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_auipc.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_auipc_valid.eq(insn_auipc.spec_valid) - m.d.comb += spec_insn_auipc_trap.eq(insn_auipc.spec_trap) - m.d.comb += spec_insn_auipc_rs1_addr.eq(insn_auipc.spec_rs1_addr) - m.d.comb += spec_insn_auipc_rs2_addr.eq(insn_auipc.spec_rs2_addr) - m.d.comb += spec_insn_auipc_rd_addr.eq(insn_auipc.spec_rd_addr) - m.d.comb += spec_insn_auipc_rd_wdata.eq(insn_auipc.spec_rd_wdata) - m.d.comb += spec_insn_auipc_pc_wdata.eq(insn_auipc.spec_pc_wdata) - m.d.comb += spec_insn_auipc_mem_addr.eq(insn_auipc.spec_mem_addr) - m.d.comb += spec_insn_auipc_mem_rmask.eq(insn_auipc.spec_mem_rmask) - m.d.comb += spec_insn_auipc_mem_wmask.eq(insn_auipc.spec_mem_wmask) - m.d.comb += spec_insn_auipc_mem_wdata.eq(insn_auipc.spec_mem_wdata) - - spec_insn_jal_valid = Signal(1) - spec_insn_jal_trap = Signal(1) - spec_insn_jal_rs1_addr = Signal(5) - spec_insn_jal_rs2_addr = Signal(5) - spec_insn_jal_rd_addr = Signal(5) - spec_insn_jal_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_jal_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_jal_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_jal_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_jal_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_jal_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_jal = insn_jal = rvfi_insn_jal() - m.d.comb += insn_jal.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_jal.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_jal.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_jal.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_jal.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_jal.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_jal_valid.eq(insn_jal.spec_valid) - m.d.comb += spec_insn_jal_trap.eq(insn_jal.spec_trap) - m.d.comb += spec_insn_jal_rs1_addr.eq(insn_jal.spec_rs1_addr) - m.d.comb += spec_insn_jal_rs2_addr.eq(insn_jal.spec_rs2_addr) - m.d.comb += spec_insn_jal_rd_addr.eq(insn_jal.spec_rd_addr) - m.d.comb += spec_insn_jal_rd_wdata.eq(insn_jal.spec_rd_wdata) - m.d.comb += spec_insn_jal_pc_wdata.eq(insn_jal.spec_pc_wdata) - m.d.comb += spec_insn_jal_mem_addr.eq(insn_jal.spec_mem_addr) - m.d.comb += spec_insn_jal_mem_rmask.eq(insn_jal.spec_mem_rmask) - m.d.comb += spec_insn_jal_mem_wmask.eq(insn_jal.spec_mem_wmask) - m.d.comb += spec_insn_jal_mem_wdata.eq(insn_jal.spec_mem_wdata) - - spec_insn_jalr_valid = Signal(1) - spec_insn_jalr_trap = Signal(1) - spec_insn_jalr_rs1_addr = Signal(5) - spec_insn_jalr_rs2_addr = Signal(5) - spec_insn_jalr_rd_addr = Signal(5) - spec_insn_jalr_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_jalr_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_jalr_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_jalr_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_jalr_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_jalr_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_jalr = insn_jalr = rvfi_insn_jalr() - m.d.comb += insn_jalr.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_jalr.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_jalr.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_jalr.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_jalr.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_jalr.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_jalr_valid.eq(insn_jalr.spec_valid) - m.d.comb += spec_insn_jalr_trap.eq(insn_jalr.spec_trap) - m.d.comb += spec_insn_jalr_rs1_addr.eq(insn_jalr.spec_rs1_addr) - m.d.comb += spec_insn_jalr_rs2_addr.eq(insn_jalr.spec_rs2_addr) - m.d.comb += spec_insn_jalr_rd_addr.eq(insn_jalr.spec_rd_addr) - m.d.comb += spec_insn_jalr_rd_wdata.eq(insn_jalr.spec_rd_wdata) - m.d.comb += spec_insn_jalr_pc_wdata.eq(insn_jalr.spec_pc_wdata) - m.d.comb += spec_insn_jalr_mem_addr.eq(insn_jalr.spec_mem_addr) - m.d.comb += spec_insn_jalr_mem_rmask.eq(insn_jalr.spec_mem_rmask) - m.d.comb += spec_insn_jalr_mem_wmask.eq(insn_jalr.spec_mem_wmask) - m.d.comb += spec_insn_jalr_mem_wdata.eq(insn_jalr.spec_mem_wdata) - - spec_insn_beq_valid = Signal(1) - spec_insn_beq_trap = Signal(1) - spec_insn_beq_rs1_addr = Signal(5) - spec_insn_beq_rs2_addr = Signal(5) - spec_insn_beq_rd_addr = Signal(5) - spec_insn_beq_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_beq_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_beq_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_beq_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_beq_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_beq_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_beq = insn_beq = rvfi_insn_beq() - m.d.comb += insn_beq.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_beq.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_beq.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_beq.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_beq.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_beq.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_beq_valid.eq(insn_beq.spec_valid) - m.d.comb += spec_insn_beq_trap.eq(insn_beq.spec_trap) - m.d.comb += spec_insn_beq_rs1_addr.eq(insn_beq.spec_rs1_addr) - m.d.comb += spec_insn_beq_rs2_addr.eq(insn_beq.spec_rs2_addr) - m.d.comb += spec_insn_beq_rd_addr.eq(insn_beq.spec_rd_addr) - m.d.comb += spec_insn_beq_rd_wdata.eq(insn_beq.spec_rd_wdata) - m.d.comb += spec_insn_beq_pc_wdata.eq(insn_beq.spec_pc_wdata) - m.d.comb += spec_insn_beq_mem_addr.eq(insn_beq.spec_mem_addr) - m.d.comb += spec_insn_beq_mem_rmask.eq(insn_beq.spec_mem_rmask) - m.d.comb += spec_insn_beq_mem_wmask.eq(insn_beq.spec_mem_wmask) - m.d.comb += spec_insn_beq_mem_wdata.eq(insn_beq.spec_mem_wdata) - - spec_insn_bne_valid = Signal(1) - spec_insn_bne_trap = Signal(1) - spec_insn_bne_rs1_addr = Signal(5) - spec_insn_bne_rs2_addr = Signal(5) - spec_insn_bne_rd_addr = Signal(5) - spec_insn_bne_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_bne_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_bne_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_bne_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_bne_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_bne_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_bne = insn_bne = rvfi_insn_bne() - m.d.comb += insn_bne.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_bne.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_bne.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_bne.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_bne.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_bne.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_bne_valid.eq(insn_bne.spec_valid) - m.d.comb += spec_insn_bne_trap.eq(insn_bne.spec_trap) - m.d.comb += spec_insn_bne_rs1_addr.eq(insn_bne.spec_rs1_addr) - m.d.comb += spec_insn_bne_rs2_addr.eq(insn_bne.spec_rs2_addr) - m.d.comb += spec_insn_bne_rd_addr.eq(insn_bne.spec_rd_addr) - m.d.comb += spec_insn_bne_rd_wdata.eq(insn_bne.spec_rd_wdata) - m.d.comb += spec_insn_bne_pc_wdata.eq(insn_bne.spec_pc_wdata) - m.d.comb += spec_insn_bne_mem_addr.eq(insn_bne.spec_mem_addr) - m.d.comb += spec_insn_bne_mem_rmask.eq(insn_bne.spec_mem_rmask) - m.d.comb += spec_insn_bne_mem_wmask.eq(insn_bne.spec_mem_wmask) - m.d.comb += spec_insn_bne_mem_wdata.eq(insn_bne.spec_mem_wdata) - - spec_insn_blt_valid = Signal(1) - spec_insn_blt_trap = Signal(1) - spec_insn_blt_rs1_addr = Signal(5) - spec_insn_blt_rs2_addr = Signal(5) - spec_insn_blt_rd_addr = Signal(5) - spec_insn_blt_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_blt_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_blt_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_blt_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_blt_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_blt_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_blt = insn_blt = rvfi_insn_blt() - m.d.comb += insn_blt.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_blt.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_blt.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_blt.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_blt.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_blt.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_blt_valid.eq(insn_blt.spec_valid) - m.d.comb += spec_insn_blt_trap.eq(insn_blt.spec_trap) - m.d.comb += spec_insn_blt_rs1_addr.eq(insn_blt.spec_rs1_addr) - m.d.comb += spec_insn_blt_rs2_addr.eq(insn_blt.spec_rs2_addr) - m.d.comb += spec_insn_blt_rd_addr.eq(insn_blt.spec_rd_addr) - m.d.comb += spec_insn_blt_rd_wdata.eq(insn_blt.spec_rd_wdata) - m.d.comb += spec_insn_blt_pc_wdata.eq(insn_blt.spec_pc_wdata) - m.d.comb += spec_insn_blt_mem_addr.eq(insn_blt.spec_mem_addr) - m.d.comb += spec_insn_blt_mem_rmask.eq(insn_blt.spec_mem_rmask) - m.d.comb += spec_insn_blt_mem_wmask.eq(insn_blt.spec_mem_wmask) - m.d.comb += spec_insn_blt_mem_wdata.eq(insn_blt.spec_mem_wdata) - - spec_insn_bge_valid = Signal(1) - spec_insn_bge_trap = Signal(1) - spec_insn_bge_rs1_addr = Signal(5) - spec_insn_bge_rs2_addr = Signal(5) - spec_insn_bge_rd_addr = Signal(5) - spec_insn_bge_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_bge_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_bge_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_bge_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_bge_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_bge_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_bge = insn_bge = rvfi_insn_bge() - m.d.comb += insn_bge.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_bge.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_bge.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_bge.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_bge.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_bge.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_bge_valid.eq(insn_bge.spec_valid) - m.d.comb += spec_insn_bge_trap.eq(insn_bge.spec_trap) - m.d.comb += spec_insn_bge_rs1_addr.eq(insn_bge.spec_rs1_addr) - m.d.comb += spec_insn_bge_rs2_addr.eq(insn_bge.spec_rs2_addr) - m.d.comb += spec_insn_bge_rd_addr.eq(insn_bge.spec_rd_addr) - m.d.comb += spec_insn_bge_rd_wdata.eq(insn_bge.spec_rd_wdata) - m.d.comb += spec_insn_bge_pc_wdata.eq(insn_bge.spec_pc_wdata) - m.d.comb += spec_insn_bge_mem_addr.eq(insn_bge.spec_mem_addr) - m.d.comb += spec_insn_bge_mem_rmask.eq(insn_bge.spec_mem_rmask) - m.d.comb += spec_insn_bge_mem_wmask.eq(insn_bge.spec_mem_wmask) - m.d.comb += spec_insn_bge_mem_wdata.eq(insn_bge.spec_mem_wdata) - - spec_insn_bltu_valid = Signal(1) - spec_insn_bltu_trap = Signal(1) - spec_insn_bltu_rs1_addr = Signal(5) - spec_insn_bltu_rs2_addr = Signal(5) - spec_insn_bltu_rd_addr = Signal(5) - spec_insn_bltu_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_bltu_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_bltu_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_bltu_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_bltu_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_bltu_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_bltu = insn_bltu = rvfi_insn_bltu() - m.d.comb += insn_bltu.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_bltu.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_bltu.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_bltu.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_bltu.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_bltu.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_bltu_valid.eq(insn_bltu.spec_valid) - m.d.comb += spec_insn_bltu_trap.eq(insn_bltu.spec_trap) - m.d.comb += spec_insn_bltu_rs1_addr.eq(insn_bltu.spec_rs1_addr) - m.d.comb += spec_insn_bltu_rs2_addr.eq(insn_bltu.spec_rs2_addr) - m.d.comb += spec_insn_bltu_rd_addr.eq(insn_bltu.spec_rd_addr) - m.d.comb += spec_insn_bltu_rd_wdata.eq(insn_bltu.spec_rd_wdata) - m.d.comb += spec_insn_bltu_pc_wdata.eq(insn_bltu.spec_pc_wdata) - m.d.comb += spec_insn_bltu_mem_addr.eq(insn_bltu.spec_mem_addr) - m.d.comb += spec_insn_bltu_mem_rmask.eq(insn_bltu.spec_mem_rmask) - m.d.comb += spec_insn_bltu_mem_wmask.eq(insn_bltu.spec_mem_wmask) - m.d.comb += spec_insn_bltu_mem_wdata.eq(insn_bltu.spec_mem_wdata) - - spec_insn_bgeu_valid = Signal(1) - spec_insn_bgeu_trap = Signal(1) - spec_insn_bgeu_rs1_addr = Signal(5) - spec_insn_bgeu_rs2_addr = Signal(5) - spec_insn_bgeu_rd_addr = Signal(5) - spec_insn_bgeu_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_bgeu_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_bgeu_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_bgeu_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_bgeu_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_bgeu_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_bgeu = insn_bgeu = rvfi_insn_bgeu() - m.d.comb += insn_bgeu.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_bgeu.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_bgeu.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_bgeu.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_bgeu.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_bgeu.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_bgeu_valid.eq(insn_bgeu.spec_valid) - m.d.comb += spec_insn_bgeu_trap.eq(insn_bgeu.spec_trap) - m.d.comb += spec_insn_bgeu_rs1_addr.eq(insn_bgeu.spec_rs1_addr) - m.d.comb += spec_insn_bgeu_rs2_addr.eq(insn_bgeu.spec_rs2_addr) - m.d.comb += spec_insn_bgeu_rd_addr.eq(insn_bgeu.spec_rd_addr) - m.d.comb += spec_insn_bgeu_rd_wdata.eq(insn_bgeu.spec_rd_wdata) - m.d.comb += spec_insn_bgeu_pc_wdata.eq(insn_bgeu.spec_pc_wdata) - m.d.comb += spec_insn_bgeu_mem_addr.eq(insn_bgeu.spec_mem_addr) - m.d.comb += spec_insn_bgeu_mem_rmask.eq(insn_bgeu.spec_mem_rmask) - m.d.comb += spec_insn_bgeu_mem_wmask.eq(insn_bgeu.spec_mem_wmask) - m.d.comb += spec_insn_bgeu_mem_wdata.eq(insn_bgeu.spec_mem_wdata) - - spec_insn_lb_valid = Signal(1) - spec_insn_lb_trap = Signal(1) - spec_insn_lb_rs1_addr = Signal(5) - spec_insn_lb_rs2_addr = Signal(5) - spec_insn_lb_rd_addr = Signal(5) - spec_insn_lb_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lb_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lb_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lb_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_lb_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_lb_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_lb = insn_lb = rvfi_insn_lb() - m.d.comb += insn_lb.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_lb.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_lb.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_lb.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_lb.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_lb.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_lb_valid.eq(insn_lb.spec_valid) - m.d.comb += spec_insn_lb_trap.eq(insn_lb.spec_trap) - m.d.comb += spec_insn_lb_rs1_addr.eq(insn_lb.spec_rs1_addr) - m.d.comb += spec_insn_lb_rs2_addr.eq(insn_lb.spec_rs2_addr) - m.d.comb += spec_insn_lb_rd_addr.eq(insn_lb.spec_rd_addr) - m.d.comb += spec_insn_lb_rd_wdata.eq(insn_lb.spec_rd_wdata) - m.d.comb += spec_insn_lb_pc_wdata.eq(insn_lb.spec_pc_wdata) - m.d.comb += spec_insn_lb_mem_addr.eq(insn_lb.spec_mem_addr) - m.d.comb += spec_insn_lb_mem_rmask.eq(insn_lb.spec_mem_rmask) - m.d.comb += spec_insn_lb_mem_wmask.eq(insn_lb.spec_mem_wmask) - m.d.comb += spec_insn_lb_mem_wdata.eq(insn_lb.spec_mem_wdata) - - spec_insn_lh_valid = Signal(1) - spec_insn_lh_trap = Signal(1) - spec_insn_lh_rs1_addr = Signal(5) - spec_insn_lh_rs2_addr = Signal(5) - spec_insn_lh_rd_addr = Signal(5) - spec_insn_lh_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lh_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lh_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lh_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_lh_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_lh_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_lh = insn_lh = rvfi_insn_lh() - m.d.comb += insn_lh.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_lh.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_lh.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_lh.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_lh.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_lh.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_lh_valid.eq(insn_lh.spec_valid) - m.d.comb += spec_insn_lh_trap.eq(insn_lh.spec_trap) - m.d.comb += spec_insn_lh_rs1_addr.eq(insn_lh.spec_rs1_addr) - m.d.comb += spec_insn_lh_rs2_addr.eq(insn_lh.spec_rs2_addr) - m.d.comb += spec_insn_lh_rd_addr.eq(insn_lh.spec_rd_addr) - m.d.comb += spec_insn_lh_rd_wdata.eq(insn_lh.spec_rd_wdata) - m.d.comb += spec_insn_lh_pc_wdata.eq(insn_lh.spec_pc_wdata) - m.d.comb += spec_insn_lh_mem_addr.eq(insn_lh.spec_mem_addr) - m.d.comb += spec_insn_lh_mem_rmask.eq(insn_lh.spec_mem_rmask) - m.d.comb += spec_insn_lh_mem_wmask.eq(insn_lh.spec_mem_wmask) - m.d.comb += spec_insn_lh_mem_wdata.eq(insn_lh.spec_mem_wdata) - - spec_insn_lw_valid = Signal(1) - spec_insn_lw_trap = Signal(1) - spec_insn_lw_rs1_addr = Signal(5) - spec_insn_lw_rs2_addr = Signal(5) - spec_insn_lw_rd_addr = Signal(5) - spec_insn_lw_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lw_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lw_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lw_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_lw_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_lw_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_lw = insn_lw = rvfi_insn_lw() - m.d.comb += insn_lw.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_lw.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_lw.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_lw.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_lw.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_lw.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_lw_valid.eq(insn_lw.spec_valid) - m.d.comb += spec_insn_lw_trap.eq(insn_lw.spec_trap) - m.d.comb += spec_insn_lw_rs1_addr.eq(insn_lw.spec_rs1_addr) - m.d.comb += spec_insn_lw_rs2_addr.eq(insn_lw.spec_rs2_addr) - m.d.comb += spec_insn_lw_rd_addr.eq(insn_lw.spec_rd_addr) - m.d.comb += spec_insn_lw_rd_wdata.eq(insn_lw.spec_rd_wdata) - m.d.comb += spec_insn_lw_pc_wdata.eq(insn_lw.spec_pc_wdata) - m.d.comb += spec_insn_lw_mem_addr.eq(insn_lw.spec_mem_addr) - m.d.comb += spec_insn_lw_mem_rmask.eq(insn_lw.spec_mem_rmask) - m.d.comb += spec_insn_lw_mem_wmask.eq(insn_lw.spec_mem_wmask) - m.d.comb += spec_insn_lw_mem_wdata.eq(insn_lw.spec_mem_wdata) - - spec_insn_lbu_valid = Signal(1) - spec_insn_lbu_trap = Signal(1) - spec_insn_lbu_rs1_addr = Signal(5) - spec_insn_lbu_rs2_addr = Signal(5) - spec_insn_lbu_rd_addr = Signal(5) - spec_insn_lbu_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lbu_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lbu_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lbu_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_lbu_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_lbu_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_lbu = insn_lbu = rvfi_insn_lbu() - m.d.comb += insn_lbu.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_lbu.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_lbu.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_lbu.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_lbu.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_lbu.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_lbu_valid.eq(insn_lbu.spec_valid) - m.d.comb += spec_insn_lbu_trap.eq(insn_lbu.spec_trap) - m.d.comb += spec_insn_lbu_rs1_addr.eq(insn_lbu.spec_rs1_addr) - m.d.comb += spec_insn_lbu_rs2_addr.eq(insn_lbu.spec_rs2_addr) - m.d.comb += spec_insn_lbu_rd_addr.eq(insn_lbu.spec_rd_addr) - m.d.comb += spec_insn_lbu_rd_wdata.eq(insn_lbu.spec_rd_wdata) - m.d.comb += spec_insn_lbu_pc_wdata.eq(insn_lbu.spec_pc_wdata) - m.d.comb += spec_insn_lbu_mem_addr.eq(insn_lbu.spec_mem_addr) - m.d.comb += spec_insn_lbu_mem_rmask.eq(insn_lbu.spec_mem_rmask) - m.d.comb += spec_insn_lbu_mem_wmask.eq(insn_lbu.spec_mem_wmask) - m.d.comb += spec_insn_lbu_mem_wdata.eq(insn_lbu.spec_mem_wdata) - - spec_insn_lhu_valid = Signal(1) - spec_insn_lhu_trap = Signal(1) - spec_insn_lhu_rs1_addr = Signal(5) - spec_insn_lhu_rs2_addr = Signal(5) - spec_insn_lhu_rd_addr = Signal(5) - spec_insn_lhu_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lhu_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lhu_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lhu_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_lhu_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_lhu_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_lhu = insn_lhu = rvfi_insn_lhu() - m.d.comb += insn_lhu.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_lhu.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_lhu.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_lhu.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_lhu.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_lhu.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_lhu_valid.eq(insn_lhu.spec_valid) - m.d.comb += spec_insn_lhu_trap.eq(insn_lhu.spec_trap) - m.d.comb += spec_insn_lhu_rs1_addr.eq(insn_lhu.spec_rs1_addr) - m.d.comb += spec_insn_lhu_rs2_addr.eq(insn_lhu.spec_rs2_addr) - m.d.comb += spec_insn_lhu_rd_addr.eq(insn_lhu.spec_rd_addr) - m.d.comb += spec_insn_lhu_rd_wdata.eq(insn_lhu.spec_rd_wdata) - m.d.comb += spec_insn_lhu_pc_wdata.eq(insn_lhu.spec_pc_wdata) - m.d.comb += spec_insn_lhu_mem_addr.eq(insn_lhu.spec_mem_addr) - m.d.comb += spec_insn_lhu_mem_rmask.eq(insn_lhu.spec_mem_rmask) - m.d.comb += spec_insn_lhu_mem_wmask.eq(insn_lhu.spec_mem_wmask) - m.d.comb += spec_insn_lhu_mem_wdata.eq(insn_lhu.spec_mem_wdata) - - spec_insn_sb_valid = Signal(1) - spec_insn_sb_trap = Signal(1) - spec_insn_sb_rs1_addr = Signal(5) - spec_insn_sb_rs2_addr = Signal(5) - spec_insn_sb_rd_addr = Signal(5) - spec_insn_sb_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sb_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sb_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sb_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sb_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sb_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_sb = insn_sb = rvfi_insn_sb() - m.d.comb += insn_sb.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_sb.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_sb.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_sb.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_sb.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_sb.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_sb_valid.eq(insn_sb.spec_valid) - m.d.comb += spec_insn_sb_trap.eq(insn_sb.spec_trap) - m.d.comb += spec_insn_sb_rs1_addr.eq(insn_sb.spec_rs1_addr) - m.d.comb += spec_insn_sb_rs2_addr.eq(insn_sb.spec_rs2_addr) - m.d.comb += spec_insn_sb_rd_addr.eq(insn_sb.spec_rd_addr) - m.d.comb += spec_insn_sb_rd_wdata.eq(insn_sb.spec_rd_wdata) - m.d.comb += spec_insn_sb_pc_wdata.eq(insn_sb.spec_pc_wdata) - m.d.comb += spec_insn_sb_mem_addr.eq(insn_sb.spec_mem_addr) - m.d.comb += spec_insn_sb_mem_rmask.eq(insn_sb.spec_mem_rmask) - m.d.comb += spec_insn_sb_mem_wmask.eq(insn_sb.spec_mem_wmask) - m.d.comb += spec_insn_sb_mem_wdata.eq(insn_sb.spec_mem_wdata) - - spec_insn_sh_valid = Signal(1) - spec_insn_sh_trap = Signal(1) - spec_insn_sh_rs1_addr = Signal(5) - spec_insn_sh_rs2_addr = Signal(5) - spec_insn_sh_rd_addr = Signal(5) - spec_insn_sh_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sh_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sh_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sh_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sh_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sh_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_sh = insn_sh = rvfi_insn_sh() - m.d.comb += insn_sh.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_sh.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_sh.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_sh.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_sh.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_sh.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_sh_valid.eq(insn_sh.spec_valid) - m.d.comb += spec_insn_sh_trap.eq(insn_sh.spec_trap) - m.d.comb += spec_insn_sh_rs1_addr.eq(insn_sh.spec_rs1_addr) - m.d.comb += spec_insn_sh_rs2_addr.eq(insn_sh.spec_rs2_addr) - m.d.comb += spec_insn_sh_rd_addr.eq(insn_sh.spec_rd_addr) - m.d.comb += spec_insn_sh_rd_wdata.eq(insn_sh.spec_rd_wdata) - m.d.comb += spec_insn_sh_pc_wdata.eq(insn_sh.spec_pc_wdata) - m.d.comb += spec_insn_sh_mem_addr.eq(insn_sh.spec_mem_addr) - m.d.comb += spec_insn_sh_mem_rmask.eq(insn_sh.spec_mem_rmask) - m.d.comb += spec_insn_sh_mem_wmask.eq(insn_sh.spec_mem_wmask) - m.d.comb += spec_insn_sh_mem_wdata.eq(insn_sh.spec_mem_wdata) - - spec_insn_sw_valid = Signal(1) - spec_insn_sw_trap = Signal(1) - spec_insn_sw_rs1_addr = Signal(5) - spec_insn_sw_rs2_addr = Signal(5) - spec_insn_sw_rd_addr = Signal(5) - spec_insn_sw_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sw_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sw_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sw_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sw_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sw_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_sw = insn_sw = rvfi_insn_sw() - m.d.comb += insn_sw.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_sw.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_sw.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_sw.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_sw.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_sw.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_sw_valid.eq(insn_sw.spec_valid) - m.d.comb += spec_insn_sw_trap.eq(insn_sw.spec_trap) - m.d.comb += spec_insn_sw_rs1_addr.eq(insn_sw.spec_rs1_addr) - m.d.comb += spec_insn_sw_rs2_addr.eq(insn_sw.spec_rs2_addr) - m.d.comb += spec_insn_sw_rd_addr.eq(insn_sw.spec_rd_addr) - m.d.comb += spec_insn_sw_rd_wdata.eq(insn_sw.spec_rd_wdata) - m.d.comb += spec_insn_sw_pc_wdata.eq(insn_sw.spec_pc_wdata) - m.d.comb += spec_insn_sw_mem_addr.eq(insn_sw.spec_mem_addr) - m.d.comb += spec_insn_sw_mem_rmask.eq(insn_sw.spec_mem_rmask) - m.d.comb += spec_insn_sw_mem_wmask.eq(insn_sw.spec_mem_wmask) - m.d.comb += spec_insn_sw_mem_wdata.eq(insn_sw.spec_mem_wdata) - - spec_insn_addi_valid = Signal(1) - spec_insn_addi_trap = Signal(1) - spec_insn_addi_rs1_addr = Signal(5) - spec_insn_addi_rs2_addr = Signal(5) - spec_insn_addi_rd_addr = Signal(5) - spec_insn_addi_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_addi_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_addi_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_addi_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_addi_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_addi_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_addi = insn_addi = rvfi_insn_addi() - m.d.comb += insn_addi.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_addi.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_addi.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_addi.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_addi.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_addi.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_addi_valid.eq(insn_addi.spec_valid) - m.d.comb += spec_insn_addi_trap.eq(insn_addi.spec_trap) - m.d.comb += spec_insn_addi_rs1_addr.eq(insn_addi.spec_rs1_addr) - m.d.comb += spec_insn_addi_rs2_addr.eq(insn_addi.spec_rs2_addr) - m.d.comb += spec_insn_addi_rd_addr.eq(insn_addi.spec_rd_addr) - m.d.comb += spec_insn_addi_rd_wdata.eq(insn_addi.spec_rd_wdata) - m.d.comb += spec_insn_addi_pc_wdata.eq(insn_addi.spec_pc_wdata) - m.d.comb += spec_insn_addi_mem_addr.eq(insn_addi.spec_mem_addr) - m.d.comb += spec_insn_addi_mem_rmask.eq(insn_addi.spec_mem_rmask) - m.d.comb += spec_insn_addi_mem_wmask.eq(insn_addi.spec_mem_wmask) - m.d.comb += spec_insn_addi_mem_wdata.eq(insn_addi.spec_mem_wdata) - - spec_insn_slti_valid = Signal(1) - spec_insn_slti_trap = Signal(1) - spec_insn_slti_rs1_addr = Signal(5) - spec_insn_slti_rs2_addr = Signal(5) - spec_insn_slti_rd_addr = Signal(5) - spec_insn_slti_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_slti_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_slti_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_slti_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_slti_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_slti_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_slti = insn_slti = rvfi_insn_slti() - m.d.comb += insn_slti.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_slti.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_slti.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_slti.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_slti.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_slti.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_slti_valid.eq(insn_slti.spec_valid) - m.d.comb += spec_insn_slti_trap.eq(insn_slti.spec_trap) - m.d.comb += spec_insn_slti_rs1_addr.eq(insn_slti.spec_rs1_addr) - m.d.comb += spec_insn_slti_rs2_addr.eq(insn_slti.spec_rs2_addr) - m.d.comb += spec_insn_slti_rd_addr.eq(insn_slti.spec_rd_addr) - m.d.comb += spec_insn_slti_rd_wdata.eq(insn_slti.spec_rd_wdata) - m.d.comb += spec_insn_slti_pc_wdata.eq(insn_slti.spec_pc_wdata) - m.d.comb += spec_insn_slti_mem_addr.eq(insn_slti.spec_mem_addr) - m.d.comb += spec_insn_slti_mem_rmask.eq(insn_slti.spec_mem_rmask) - m.d.comb += spec_insn_slti_mem_wmask.eq(insn_slti.spec_mem_wmask) - m.d.comb += spec_insn_slti_mem_wdata.eq(insn_slti.spec_mem_wdata) - - spec_insn_sltiu_valid = Signal(1) - spec_insn_sltiu_trap = Signal(1) - spec_insn_sltiu_rs1_addr = Signal(5) - spec_insn_sltiu_rs2_addr = Signal(5) - spec_insn_sltiu_rd_addr = Signal(5) - spec_insn_sltiu_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sltiu_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sltiu_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sltiu_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sltiu_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sltiu_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_sltiu = insn_sltiu = rvfi_insn_sltiu() - m.d.comb += insn_sltiu.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_sltiu.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_sltiu.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_sltiu.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_sltiu.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_sltiu.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_sltiu_valid.eq(insn_sltiu.spec_valid) - m.d.comb += spec_insn_sltiu_trap.eq(insn_sltiu.spec_trap) - m.d.comb += spec_insn_sltiu_rs1_addr.eq(insn_sltiu.spec_rs1_addr) - m.d.comb += spec_insn_sltiu_rs2_addr.eq(insn_sltiu.spec_rs2_addr) - m.d.comb += spec_insn_sltiu_rd_addr.eq(insn_sltiu.spec_rd_addr) - m.d.comb += spec_insn_sltiu_rd_wdata.eq(insn_sltiu.spec_rd_wdata) - m.d.comb += spec_insn_sltiu_pc_wdata.eq(insn_sltiu.spec_pc_wdata) - m.d.comb += spec_insn_sltiu_mem_addr.eq(insn_sltiu.spec_mem_addr) - m.d.comb += spec_insn_sltiu_mem_rmask.eq(insn_sltiu.spec_mem_rmask) - m.d.comb += spec_insn_sltiu_mem_wmask.eq(insn_sltiu.spec_mem_wmask) - m.d.comb += spec_insn_sltiu_mem_wdata.eq(insn_sltiu.spec_mem_wdata) - - spec_insn_xori_valid = Signal(1) - spec_insn_xori_trap = Signal(1) - spec_insn_xori_rs1_addr = Signal(5) - spec_insn_xori_rs2_addr = Signal(5) - spec_insn_xori_rd_addr = Signal(5) - spec_insn_xori_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_xori_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_xori_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_xori_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_xori_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_xori_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_xori = insn_xori = rvfi_insn_xori() - m.d.comb += insn_xori.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_xori.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_xori.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_xori.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_xori.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_xori.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_xori_valid.eq(insn_xori.spec_valid) - m.d.comb += spec_insn_xori_trap.eq(insn_xori.spec_trap) - m.d.comb += spec_insn_xori_rs1_addr.eq(insn_xori.spec_rs1_addr) - m.d.comb += spec_insn_xori_rs2_addr.eq(insn_xori.spec_rs2_addr) - m.d.comb += spec_insn_xori_rd_addr.eq(insn_xori.spec_rd_addr) - m.d.comb += spec_insn_xori_rd_wdata.eq(insn_xori.spec_rd_wdata) - m.d.comb += spec_insn_xori_pc_wdata.eq(insn_xori.spec_pc_wdata) - m.d.comb += spec_insn_xori_mem_addr.eq(insn_xori.spec_mem_addr) - m.d.comb += spec_insn_xori_mem_rmask.eq(insn_xori.spec_mem_rmask) - m.d.comb += spec_insn_xori_mem_wmask.eq(insn_xori.spec_mem_wmask) - m.d.comb += spec_insn_xori_mem_wdata.eq(insn_xori.spec_mem_wdata) - - spec_insn_ori_valid = Signal(1) - spec_insn_ori_trap = Signal(1) - spec_insn_ori_rs1_addr = Signal(5) - spec_insn_ori_rs2_addr = Signal(5) - spec_insn_ori_rd_addr = Signal(5) - spec_insn_ori_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_ori_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_ori_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_ori_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_ori_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_ori_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_ori = insn_ori = rvfi_insn_ori() - m.d.comb += insn_ori.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_ori.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_ori.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_ori.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_ori.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_ori.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_ori_valid.eq(insn_ori.spec_valid) - m.d.comb += spec_insn_ori_trap.eq(insn_ori.spec_trap) - m.d.comb += spec_insn_ori_rs1_addr.eq(insn_ori.spec_rs1_addr) - m.d.comb += spec_insn_ori_rs2_addr.eq(insn_ori.spec_rs2_addr) - m.d.comb += spec_insn_ori_rd_addr.eq(insn_ori.spec_rd_addr) - m.d.comb += spec_insn_ori_rd_wdata.eq(insn_ori.spec_rd_wdata) - m.d.comb += spec_insn_ori_pc_wdata.eq(insn_ori.spec_pc_wdata) - m.d.comb += spec_insn_ori_mem_addr.eq(insn_ori.spec_mem_addr) - m.d.comb += spec_insn_ori_mem_rmask.eq(insn_ori.spec_mem_rmask) - m.d.comb += spec_insn_ori_mem_wmask.eq(insn_ori.spec_mem_wmask) - m.d.comb += spec_insn_ori_mem_wdata.eq(insn_ori.spec_mem_wdata) - - spec_insn_andi_valid = Signal(1) - spec_insn_andi_trap = Signal(1) - spec_insn_andi_rs1_addr = Signal(5) - spec_insn_andi_rs2_addr = Signal(5) - spec_insn_andi_rd_addr = Signal(5) - spec_insn_andi_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_andi_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_andi_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_andi_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_andi_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_andi_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_andi = insn_andi = rvfi_insn_andi() - m.d.comb += insn_andi.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_andi.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_andi.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_andi.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_andi.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_andi.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_andi_valid.eq(insn_andi.spec_valid) - m.d.comb += spec_insn_andi_trap.eq(insn_andi.spec_trap) - m.d.comb += spec_insn_andi_rs1_addr.eq(insn_andi.spec_rs1_addr) - m.d.comb += spec_insn_andi_rs2_addr.eq(insn_andi.spec_rs2_addr) - m.d.comb += spec_insn_andi_rd_addr.eq(insn_andi.spec_rd_addr) - m.d.comb += spec_insn_andi_rd_wdata.eq(insn_andi.spec_rd_wdata) - m.d.comb += spec_insn_andi_pc_wdata.eq(insn_andi.spec_pc_wdata) - m.d.comb += spec_insn_andi_mem_addr.eq(insn_andi.spec_mem_addr) - m.d.comb += spec_insn_andi_mem_rmask.eq(insn_andi.spec_mem_rmask) - m.d.comb += spec_insn_andi_mem_wmask.eq(insn_andi.spec_mem_wmask) - m.d.comb += spec_insn_andi_mem_wdata.eq(insn_andi.spec_mem_wdata) - - spec_insn_slli_valid = Signal(1) - spec_insn_slli_trap = Signal(1) - spec_insn_slli_rs1_addr = Signal(5) - spec_insn_slli_rs2_addr = Signal(5) - spec_insn_slli_rd_addr = Signal(5) - spec_insn_slli_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_slli_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_slli_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_slli_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_slli_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_slli_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_slli = insn_slli = rvfi_insn_slli() - m.d.comb += insn_slli.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_slli.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_slli.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_slli.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_slli.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_slli.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_slli_valid.eq(insn_slli.spec_valid) - m.d.comb += spec_insn_slli_trap.eq(insn_slli.spec_trap) - m.d.comb += spec_insn_slli_rs1_addr.eq(insn_slli.spec_rs1_addr) - m.d.comb += spec_insn_slli_rs2_addr.eq(insn_slli.spec_rs2_addr) - m.d.comb += spec_insn_slli_rd_addr.eq(insn_slli.spec_rd_addr) - m.d.comb += spec_insn_slli_rd_wdata.eq(insn_slli.spec_rd_wdata) - m.d.comb += spec_insn_slli_pc_wdata.eq(insn_slli.spec_pc_wdata) - m.d.comb += spec_insn_slli_mem_addr.eq(insn_slli.spec_mem_addr) - m.d.comb += spec_insn_slli_mem_rmask.eq(insn_slli.spec_mem_rmask) - m.d.comb += spec_insn_slli_mem_wmask.eq(insn_slli.spec_mem_wmask) - m.d.comb += spec_insn_slli_mem_wdata.eq(insn_slli.spec_mem_wdata) - - spec_insn_srli_valid = Signal(1) - spec_insn_srli_trap = Signal(1) - spec_insn_srli_rs1_addr = Signal(5) - spec_insn_srli_rs2_addr = Signal(5) - spec_insn_srli_rd_addr = Signal(5) - spec_insn_srli_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_srli_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_srli_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_srli_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_srli_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_srli_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_srli = insn_srli = rvfi_insn_srli() - m.d.comb += insn_srli.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_srli.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_srli.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_srli.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_srli.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_srli.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_srli_valid.eq(insn_srli.spec_valid) - m.d.comb += spec_insn_srli_trap.eq(insn_srli.spec_trap) - m.d.comb += spec_insn_srli_rs1_addr.eq(insn_srli.spec_rs1_addr) - m.d.comb += spec_insn_srli_rs2_addr.eq(insn_srli.spec_rs2_addr) - m.d.comb += spec_insn_srli_rd_addr.eq(insn_srli.spec_rd_addr) - m.d.comb += spec_insn_srli_rd_wdata.eq(insn_srli.spec_rd_wdata) - m.d.comb += spec_insn_srli_pc_wdata.eq(insn_srli.spec_pc_wdata) - m.d.comb += spec_insn_srli_mem_addr.eq(insn_srli.spec_mem_addr) - m.d.comb += spec_insn_srli_mem_rmask.eq(insn_srli.spec_mem_rmask) - m.d.comb += spec_insn_srli_mem_wmask.eq(insn_srli.spec_mem_wmask) - m.d.comb += spec_insn_srli_mem_wdata.eq(insn_srli.spec_mem_wdata) - - spec_insn_srai_valid = Signal(1) - spec_insn_srai_trap = Signal(1) - spec_insn_srai_rs1_addr = Signal(5) - spec_insn_srai_rs2_addr = Signal(5) - spec_insn_srai_rd_addr = Signal(5) - spec_insn_srai_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_srai_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_srai_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_srai_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_srai_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_srai_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_srai = insn_srai = rvfi_insn_srai() - m.d.comb += insn_srai.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_srai.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_srai.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_srai.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_srai.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_srai.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_srai_valid.eq(insn_srai.spec_valid) - m.d.comb += spec_insn_srai_trap.eq(insn_srai.spec_trap) - m.d.comb += spec_insn_srai_rs1_addr.eq(insn_srai.spec_rs1_addr) - m.d.comb += spec_insn_srai_rs2_addr.eq(insn_srai.spec_rs2_addr) - m.d.comb += spec_insn_srai_rd_addr.eq(insn_srai.spec_rd_addr) - m.d.comb += spec_insn_srai_rd_wdata.eq(insn_srai.spec_rd_wdata) - m.d.comb += spec_insn_srai_pc_wdata.eq(insn_srai.spec_pc_wdata) - m.d.comb += spec_insn_srai_mem_addr.eq(insn_srai.spec_mem_addr) - m.d.comb += spec_insn_srai_mem_rmask.eq(insn_srai.spec_mem_rmask) - m.d.comb += spec_insn_srai_mem_wmask.eq(insn_srai.spec_mem_wmask) - m.d.comb += spec_insn_srai_mem_wdata.eq(insn_srai.spec_mem_wdata) - - spec_insn_add_valid = Signal(1) - spec_insn_add_trap = Signal(1) - spec_insn_add_rs1_addr = Signal(5) - spec_insn_add_rs2_addr = Signal(5) - spec_insn_add_rd_addr = Signal(5) - spec_insn_add_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_add_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_add_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_add_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_add_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_add_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_add = insn_add = rvfi_insn_add() - m.d.comb += insn_add.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_add.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_add.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_add.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_add.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_add.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_add_valid.eq(insn_add.spec_valid) - m.d.comb += spec_insn_add_trap.eq(insn_add.spec_trap) - m.d.comb += spec_insn_add_rs1_addr.eq(insn_add.spec_rs1_addr) - m.d.comb += spec_insn_add_rs2_addr.eq(insn_add.spec_rs2_addr) - m.d.comb += spec_insn_add_rd_addr.eq(insn_add.spec_rd_addr) - m.d.comb += spec_insn_add_rd_wdata.eq(insn_add.spec_rd_wdata) - m.d.comb += spec_insn_add_pc_wdata.eq(insn_add.spec_pc_wdata) - m.d.comb += spec_insn_add_mem_addr.eq(insn_add.spec_mem_addr) - m.d.comb += spec_insn_add_mem_rmask.eq(insn_add.spec_mem_rmask) - m.d.comb += spec_insn_add_mem_wmask.eq(insn_add.spec_mem_wmask) - m.d.comb += spec_insn_add_mem_wdata.eq(insn_add.spec_mem_wdata) - - spec_insn_sub_valid = Signal(1) - spec_insn_sub_trap = Signal(1) - spec_insn_sub_rs1_addr = Signal(5) - spec_insn_sub_rs2_addr = Signal(5) - spec_insn_sub_rd_addr = Signal(5) - spec_insn_sub_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sub_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sub_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sub_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sub_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sub_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_sub = insn_sub = rvfi_insn_sub() - m.d.comb += insn_sub.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_sub.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_sub.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_sub.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_sub.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_sub.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_sub_valid.eq(insn_sub.spec_valid) - m.d.comb += spec_insn_sub_trap.eq(insn_sub.spec_trap) - m.d.comb += spec_insn_sub_rs1_addr.eq(insn_sub.spec_rs1_addr) - m.d.comb += spec_insn_sub_rs2_addr.eq(insn_sub.spec_rs2_addr) - m.d.comb += spec_insn_sub_rd_addr.eq(insn_sub.spec_rd_addr) - m.d.comb += spec_insn_sub_rd_wdata.eq(insn_sub.spec_rd_wdata) - m.d.comb += spec_insn_sub_pc_wdata.eq(insn_sub.spec_pc_wdata) - m.d.comb += spec_insn_sub_mem_addr.eq(insn_sub.spec_mem_addr) - m.d.comb += spec_insn_sub_mem_rmask.eq(insn_sub.spec_mem_rmask) - m.d.comb += spec_insn_sub_mem_wmask.eq(insn_sub.spec_mem_wmask) - m.d.comb += spec_insn_sub_mem_wdata.eq(insn_sub.spec_mem_wdata) - - spec_insn_sll_valid = Signal(1) - spec_insn_sll_trap = Signal(1) - spec_insn_sll_rs1_addr = Signal(5) - spec_insn_sll_rs2_addr = Signal(5) - spec_insn_sll_rd_addr = Signal(5) - spec_insn_sll_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sll_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sll_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sll_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sll_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sll_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_sll = insn_sll = rvfi_insn_sll() - m.d.comb += insn_sll.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_sll.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_sll.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_sll.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_sll.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_sll.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_sll_valid.eq(insn_sll.spec_valid) - m.d.comb += spec_insn_sll_trap.eq(insn_sll.spec_trap) - m.d.comb += spec_insn_sll_rs1_addr.eq(insn_sll.spec_rs1_addr) - m.d.comb += spec_insn_sll_rs2_addr.eq(insn_sll.spec_rs2_addr) - m.d.comb += spec_insn_sll_rd_addr.eq(insn_sll.spec_rd_addr) - m.d.comb += spec_insn_sll_rd_wdata.eq(insn_sll.spec_rd_wdata) - m.d.comb += spec_insn_sll_pc_wdata.eq(insn_sll.spec_pc_wdata) - m.d.comb += spec_insn_sll_mem_addr.eq(insn_sll.spec_mem_addr) - m.d.comb += spec_insn_sll_mem_rmask.eq(insn_sll.spec_mem_rmask) - m.d.comb += spec_insn_sll_mem_wmask.eq(insn_sll.spec_mem_wmask) - m.d.comb += spec_insn_sll_mem_wdata.eq(insn_sll.spec_mem_wdata) - - spec_insn_slt_valid = Signal(1) - spec_insn_slt_trap = Signal(1) - spec_insn_slt_rs1_addr = Signal(5) - spec_insn_slt_rs2_addr = Signal(5) - spec_insn_slt_rd_addr = Signal(5) - spec_insn_slt_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_slt_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_slt_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_slt_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_slt_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_slt_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_slt = insn_slt = rvfi_insn_slt() - m.d.comb += insn_slt.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_slt.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_slt.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_slt.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_slt.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_slt.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_slt_valid.eq(insn_slt.spec_valid) - m.d.comb += spec_insn_slt_trap.eq(insn_slt.spec_trap) - m.d.comb += spec_insn_slt_rs1_addr.eq(insn_slt.spec_rs1_addr) - m.d.comb += spec_insn_slt_rs2_addr.eq(insn_slt.spec_rs2_addr) - m.d.comb += spec_insn_slt_rd_addr.eq(insn_slt.spec_rd_addr) - m.d.comb += spec_insn_slt_rd_wdata.eq(insn_slt.spec_rd_wdata) - m.d.comb += spec_insn_slt_pc_wdata.eq(insn_slt.spec_pc_wdata) - m.d.comb += spec_insn_slt_mem_addr.eq(insn_slt.spec_mem_addr) - m.d.comb += spec_insn_slt_mem_rmask.eq(insn_slt.spec_mem_rmask) - m.d.comb += spec_insn_slt_mem_wmask.eq(insn_slt.spec_mem_wmask) - m.d.comb += spec_insn_slt_mem_wdata.eq(insn_slt.spec_mem_wdata) - - spec_insn_sltu_valid = Signal(1) - spec_insn_sltu_trap = Signal(1) - spec_insn_sltu_rs1_addr = Signal(5) - spec_insn_sltu_rs2_addr = Signal(5) - spec_insn_sltu_rd_addr = Signal(5) - spec_insn_sltu_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sltu_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sltu_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sltu_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sltu_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sltu_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_sltu = insn_sltu = rvfi_insn_sltu() - m.d.comb += insn_sltu.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_sltu.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_sltu.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_sltu.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_sltu.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_sltu.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_sltu_valid.eq(insn_sltu.spec_valid) - m.d.comb += spec_insn_sltu_trap.eq(insn_sltu.spec_trap) - m.d.comb += spec_insn_sltu_rs1_addr.eq(insn_sltu.spec_rs1_addr) - m.d.comb += spec_insn_sltu_rs2_addr.eq(insn_sltu.spec_rs2_addr) - m.d.comb += spec_insn_sltu_rd_addr.eq(insn_sltu.spec_rd_addr) - m.d.comb += spec_insn_sltu_rd_wdata.eq(insn_sltu.spec_rd_wdata) - m.d.comb += spec_insn_sltu_pc_wdata.eq(insn_sltu.spec_pc_wdata) - m.d.comb += spec_insn_sltu_mem_addr.eq(insn_sltu.spec_mem_addr) - m.d.comb += spec_insn_sltu_mem_rmask.eq(insn_sltu.spec_mem_rmask) - m.d.comb += spec_insn_sltu_mem_wmask.eq(insn_sltu.spec_mem_wmask) - m.d.comb += spec_insn_sltu_mem_wdata.eq(insn_sltu.spec_mem_wdata) - - spec_insn_xor_valid = Signal(1) - spec_insn_xor_trap = Signal(1) - spec_insn_xor_rs1_addr = Signal(5) - spec_insn_xor_rs2_addr = Signal(5) - spec_insn_xor_rd_addr = Signal(5) - spec_insn_xor_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_xor_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_xor_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_xor_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_xor_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_xor_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_xor = insn_xor = rvfi_insn_xor() - m.d.comb += insn_xor.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_xor.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_xor.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_xor.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_xor.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_xor.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_xor_valid.eq(insn_xor.spec_valid) - m.d.comb += spec_insn_xor_trap.eq(insn_xor.spec_trap) - m.d.comb += spec_insn_xor_rs1_addr.eq(insn_xor.spec_rs1_addr) - m.d.comb += spec_insn_xor_rs2_addr.eq(insn_xor.spec_rs2_addr) - m.d.comb += spec_insn_xor_rd_addr.eq(insn_xor.spec_rd_addr) - m.d.comb += spec_insn_xor_rd_wdata.eq(insn_xor.spec_rd_wdata) - m.d.comb += spec_insn_xor_pc_wdata.eq(insn_xor.spec_pc_wdata) - m.d.comb += spec_insn_xor_mem_addr.eq(insn_xor.spec_mem_addr) - m.d.comb += spec_insn_xor_mem_rmask.eq(insn_xor.spec_mem_rmask) - m.d.comb += spec_insn_xor_mem_wmask.eq(insn_xor.spec_mem_wmask) - m.d.comb += spec_insn_xor_mem_wdata.eq(insn_xor.spec_mem_wdata) - - spec_insn_srl_valid = Signal(1) - spec_insn_srl_trap = Signal(1) - spec_insn_srl_rs1_addr = Signal(5) - spec_insn_srl_rs2_addr = Signal(5) - spec_insn_srl_rd_addr = Signal(5) - spec_insn_srl_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_srl_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_srl_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_srl_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_srl_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_srl_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_srl = insn_srl = rvfi_insn_srl() - m.d.comb += insn_srl.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_srl.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_srl.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_srl.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_srl.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_srl.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_srl_valid.eq(insn_srl.spec_valid) - m.d.comb += spec_insn_srl_trap.eq(insn_srl.spec_trap) - m.d.comb += spec_insn_srl_rs1_addr.eq(insn_srl.spec_rs1_addr) - m.d.comb += spec_insn_srl_rs2_addr.eq(insn_srl.spec_rs2_addr) - m.d.comb += spec_insn_srl_rd_addr.eq(insn_srl.spec_rd_addr) - m.d.comb += spec_insn_srl_rd_wdata.eq(insn_srl.spec_rd_wdata) - m.d.comb += spec_insn_srl_pc_wdata.eq(insn_srl.spec_pc_wdata) - m.d.comb += spec_insn_srl_mem_addr.eq(insn_srl.spec_mem_addr) - m.d.comb += spec_insn_srl_mem_rmask.eq(insn_srl.spec_mem_rmask) - m.d.comb += spec_insn_srl_mem_wmask.eq(insn_srl.spec_mem_wmask) - m.d.comb += spec_insn_srl_mem_wdata.eq(insn_srl.spec_mem_wdata) - - spec_insn_sra_valid = Signal(1) - spec_insn_sra_trap = Signal(1) - spec_insn_sra_rs1_addr = Signal(5) - spec_insn_sra_rs2_addr = Signal(5) - spec_insn_sra_rd_addr = Signal(5) - spec_insn_sra_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sra_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sra_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sra_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sra_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sra_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_sra = insn_sra = rvfi_insn_sra() - m.d.comb += insn_sra.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_sra.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_sra.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_sra.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_sra.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_sra.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_sra_valid.eq(insn_sra.spec_valid) - m.d.comb += spec_insn_sra_trap.eq(insn_sra.spec_trap) - m.d.comb += spec_insn_sra_rs1_addr.eq(insn_sra.spec_rs1_addr) - m.d.comb += spec_insn_sra_rs2_addr.eq(insn_sra.spec_rs2_addr) - m.d.comb += spec_insn_sra_rd_addr.eq(insn_sra.spec_rd_addr) - m.d.comb += spec_insn_sra_rd_wdata.eq(insn_sra.spec_rd_wdata) - m.d.comb += spec_insn_sra_pc_wdata.eq(insn_sra.spec_pc_wdata) - m.d.comb += spec_insn_sra_mem_addr.eq(insn_sra.spec_mem_addr) - m.d.comb += spec_insn_sra_mem_rmask.eq(insn_sra.spec_mem_rmask) - m.d.comb += spec_insn_sra_mem_wmask.eq(insn_sra.spec_mem_wmask) - m.d.comb += spec_insn_sra_mem_wdata.eq(insn_sra.spec_mem_wdata) - - spec_insn_or_valid = Signal(1) - spec_insn_or_trap = Signal(1) - spec_insn_or_rs1_addr = Signal(5) - spec_insn_or_rs2_addr = Signal(5) - spec_insn_or_rd_addr = Signal(5) - spec_insn_or_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_or_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_or_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_or_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_or_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_or_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_or = insn_or = rvfi_insn_or() - m.d.comb += insn_or.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_or.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_or.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_or.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_or.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_or.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_or_valid.eq(insn_or.spec_valid) - m.d.comb += spec_insn_or_trap.eq(insn_or.spec_trap) - m.d.comb += spec_insn_or_rs1_addr.eq(insn_or.spec_rs1_addr) - m.d.comb += spec_insn_or_rs2_addr.eq(insn_or.spec_rs2_addr) - m.d.comb += spec_insn_or_rd_addr.eq(insn_or.spec_rd_addr) - m.d.comb += spec_insn_or_rd_wdata.eq(insn_or.spec_rd_wdata) - m.d.comb += spec_insn_or_pc_wdata.eq(insn_or.spec_pc_wdata) - m.d.comb += spec_insn_or_mem_addr.eq(insn_or.spec_mem_addr) - m.d.comb += spec_insn_or_mem_rmask.eq(insn_or.spec_mem_rmask) - m.d.comb += spec_insn_or_mem_wmask.eq(insn_or.spec_mem_wmask) - m.d.comb += spec_insn_or_mem_wdata.eq(insn_or.spec_mem_wdata) - - spec_insn_and_valid = Signal(1) - spec_insn_and_trap = Signal(1) - spec_insn_and_rs1_addr = Signal(5) - spec_insn_and_rs2_addr = Signal(5) - spec_insn_and_rd_addr = Signal(5) - spec_insn_and_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_and_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_and_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_and_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_and_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_and_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_and = insn_and = rvfi_insn_and() - m.d.comb += insn_and.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_and.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_and.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_and.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_and.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_and.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_and_valid.eq(insn_and.spec_valid) - m.d.comb += spec_insn_and_trap.eq(insn_and.spec_trap) - m.d.comb += spec_insn_and_rs1_addr.eq(insn_and.spec_rs1_addr) - m.d.comb += spec_insn_and_rs2_addr.eq(insn_and.spec_rs2_addr) - m.d.comb += spec_insn_and_rd_addr.eq(insn_and.spec_rd_addr) - m.d.comb += spec_insn_and_rd_wdata.eq(insn_and.spec_rd_wdata) - m.d.comb += spec_insn_and_pc_wdata.eq(insn_and.spec_pc_wdata) - m.d.comb += spec_insn_and_mem_addr.eq(insn_and.spec_mem_addr) - m.d.comb += spec_insn_and_mem_rmask.eq(insn_and.spec_mem_rmask) - m.d.comb += spec_insn_and_mem_wmask.eq(insn_and.spec_mem_wmask) - m.d.comb += spec_insn_and_mem_wdata.eq(insn_and.spec_mem_wdata) - - m.d.comb += self.spec_valid.eq(Mux(spec_insn_and_valid, spec_insn_and_valid, Mux(spec_insn_or_valid, spec_insn_or_valid, Mux(spec_insn_sra_valid, spec_insn_sra_valid, Mux(spec_insn_srl_valid, spec_insn_srl_valid, Mux(spec_insn_xor_valid, spec_insn_xor_valid, Mux(spec_insn_sltu_valid, spec_insn_sltu_valid, Mux(spec_insn_slt_valid, spec_insn_slt_valid, Mux(spec_insn_sll_valid, spec_insn_sll_valid, Mux(spec_insn_sub_valid, spec_insn_sub_valid, Mux(spec_insn_add_valid, spec_insn_add_valid, Mux(spec_insn_srai_valid, spec_insn_srai_valid, Mux(spec_insn_srli_valid, spec_insn_srli_valid, Mux(spec_insn_slli_valid, spec_insn_slli_valid, Mux(spec_insn_andi_valid, spec_insn_andi_valid, Mux(spec_insn_ori_valid, spec_insn_ori_valid, Mux(spec_insn_xori_valid, spec_insn_xori_valid, Mux(spec_insn_sltiu_valid, spec_insn_sltiu_valid, Mux(spec_insn_slti_valid, spec_insn_slti_valid, Mux(spec_insn_addi_valid, spec_insn_addi_valid, Mux(spec_insn_sw_valid, spec_insn_sw_valid, Mux(spec_insn_sh_valid, spec_insn_sh_valid, Mux(spec_insn_sb_valid, spec_insn_sb_valid, Mux(spec_insn_lhu_valid, spec_insn_lhu_valid, Mux(spec_insn_lbu_valid, spec_insn_lbu_valid, Mux(spec_insn_lw_valid, spec_insn_lw_valid, Mux(spec_insn_lh_valid, spec_insn_lh_valid, Mux(spec_insn_lb_valid, spec_insn_lb_valid, Mux(spec_insn_bgeu_valid, spec_insn_bgeu_valid, Mux(spec_insn_bltu_valid, spec_insn_bltu_valid, Mux(spec_insn_bge_valid, spec_insn_bge_valid, Mux(spec_insn_blt_valid, spec_insn_blt_valid, Mux(spec_insn_bne_valid, spec_insn_bne_valid, Mux(spec_insn_beq_valid, spec_insn_beq_valid, Mux(spec_insn_jalr_valid, spec_insn_jalr_valid, Mux(spec_insn_jal_valid, spec_insn_jal_valid, Mux(spec_insn_auipc_valid, spec_insn_auipc_valid, Mux(spec_insn_lui_valid, spec_insn_lui_valid, 0)))))))))))))))))))))))))))))))))))))) - m.d.comb += self.spec_trap.eq(Mux(spec_insn_and_valid, spec_insn_and_trap, Mux(spec_insn_or_valid, spec_insn_or_trap, Mux(spec_insn_sra_valid, spec_insn_sra_trap, Mux(spec_insn_srl_valid, spec_insn_srl_trap, Mux(spec_insn_xor_valid, spec_insn_xor_trap, Mux(spec_insn_sltu_valid, spec_insn_sltu_trap, Mux(spec_insn_slt_valid, spec_insn_slt_trap, Mux(spec_insn_sll_valid, spec_insn_sll_trap, Mux(spec_insn_sub_valid, spec_insn_sub_trap, Mux(spec_insn_add_valid, spec_insn_add_trap, Mux(spec_insn_srai_valid, spec_insn_srai_trap, Mux(spec_insn_srli_valid, spec_insn_srli_trap, Mux(spec_insn_slli_valid, spec_insn_slli_trap, Mux(spec_insn_andi_valid, spec_insn_andi_trap, Mux(spec_insn_ori_valid, spec_insn_ori_trap, Mux(spec_insn_xori_valid, spec_insn_xori_trap, Mux(spec_insn_sltiu_valid, spec_insn_sltiu_trap, Mux(spec_insn_slti_valid, spec_insn_slti_trap, Mux(spec_insn_addi_valid, spec_insn_addi_trap, Mux(spec_insn_sw_valid, spec_insn_sw_trap, Mux(spec_insn_sh_valid, spec_insn_sh_trap, Mux(spec_insn_sb_valid, spec_insn_sb_trap, Mux(spec_insn_lhu_valid, spec_insn_lhu_trap, Mux(spec_insn_lbu_valid, spec_insn_lbu_trap, Mux(spec_insn_lw_valid, spec_insn_lw_trap, Mux(spec_insn_lh_valid, spec_insn_lh_trap, Mux(spec_insn_lb_valid, spec_insn_lb_trap, Mux(spec_insn_bgeu_valid, spec_insn_bgeu_trap, Mux(spec_insn_bltu_valid, spec_insn_bltu_trap, Mux(spec_insn_bge_valid, spec_insn_bge_trap, Mux(spec_insn_blt_valid, spec_insn_blt_trap, Mux(spec_insn_bne_valid, spec_insn_bne_trap, Mux(spec_insn_beq_valid, spec_insn_beq_trap, Mux(spec_insn_jalr_valid, spec_insn_jalr_trap, Mux(spec_insn_jal_valid, spec_insn_jal_trap, Mux(spec_insn_auipc_valid, spec_insn_auipc_trap, Mux(spec_insn_lui_valid, spec_insn_lui_trap, 0)))))))))))))))))))))))))))))))))))))) - m.d.comb += self.spec_rs1_addr.eq(Mux(spec_insn_and_valid, spec_insn_and_rs1_addr, Mux(spec_insn_or_valid, spec_insn_or_rs1_addr, Mux(spec_insn_sra_valid, spec_insn_sra_rs1_addr, Mux(spec_insn_srl_valid, spec_insn_srl_rs1_addr, Mux(spec_insn_xor_valid, spec_insn_xor_rs1_addr, Mux(spec_insn_sltu_valid, spec_insn_sltu_rs1_addr, Mux(spec_insn_slt_valid, spec_insn_slt_rs1_addr, Mux(spec_insn_sll_valid, spec_insn_sll_rs1_addr, Mux(spec_insn_sub_valid, spec_insn_sub_rs1_addr, Mux(spec_insn_add_valid, spec_insn_add_rs1_addr, Mux(spec_insn_srai_valid, spec_insn_srai_rs1_addr, Mux(spec_insn_srli_valid, spec_insn_srli_rs1_addr, Mux(spec_insn_slli_valid, spec_insn_slli_rs1_addr, Mux(spec_insn_andi_valid, spec_insn_andi_rs1_addr, Mux(spec_insn_ori_valid, spec_insn_ori_rs1_addr, Mux(spec_insn_xori_valid, spec_insn_xori_rs1_addr, Mux(spec_insn_sltiu_valid, spec_insn_sltiu_rs1_addr, Mux(spec_insn_slti_valid, spec_insn_slti_rs1_addr, Mux(spec_insn_addi_valid, spec_insn_addi_rs1_addr, Mux(spec_insn_sw_valid, spec_insn_sw_rs1_addr, Mux(spec_insn_sh_valid, spec_insn_sh_rs1_addr, Mux(spec_insn_sb_valid, spec_insn_sb_rs1_addr, Mux(spec_insn_lhu_valid, spec_insn_lhu_rs1_addr, Mux(spec_insn_lbu_valid, spec_insn_lbu_rs1_addr, Mux(spec_insn_lw_valid, spec_insn_lw_rs1_addr, Mux(spec_insn_lh_valid, spec_insn_lh_rs1_addr, Mux(spec_insn_lb_valid, spec_insn_lb_rs1_addr, Mux(spec_insn_bgeu_valid, spec_insn_bgeu_rs1_addr, Mux(spec_insn_bltu_valid, spec_insn_bltu_rs1_addr, Mux(spec_insn_bge_valid, spec_insn_bge_rs1_addr, Mux(spec_insn_blt_valid, spec_insn_blt_rs1_addr, Mux(spec_insn_bne_valid, spec_insn_bne_rs1_addr, Mux(spec_insn_beq_valid, spec_insn_beq_rs1_addr, Mux(spec_insn_jalr_valid, spec_insn_jalr_rs1_addr, Mux(spec_insn_jal_valid, spec_insn_jal_rs1_addr, Mux(spec_insn_auipc_valid, spec_insn_auipc_rs1_addr, Mux(spec_insn_lui_valid, spec_insn_lui_rs1_addr, 0)))))))))))))))))))))))))))))))))))))) - m.d.comb += self.spec_rs2_addr.eq(Mux(spec_insn_and_valid, spec_insn_and_rs2_addr, Mux(spec_insn_or_valid, spec_insn_or_rs2_addr, Mux(spec_insn_sra_valid, spec_insn_sra_rs2_addr, Mux(spec_insn_srl_valid, spec_insn_srl_rs2_addr, Mux(spec_insn_xor_valid, spec_insn_xor_rs2_addr, Mux(spec_insn_sltu_valid, spec_insn_sltu_rs2_addr, Mux(spec_insn_slt_valid, spec_insn_slt_rs2_addr, Mux(spec_insn_sll_valid, spec_insn_sll_rs2_addr, Mux(spec_insn_sub_valid, spec_insn_sub_rs2_addr, Mux(spec_insn_add_valid, spec_insn_add_rs2_addr, Mux(spec_insn_srai_valid, spec_insn_srai_rs2_addr, Mux(spec_insn_srli_valid, spec_insn_srli_rs2_addr, Mux(spec_insn_slli_valid, spec_insn_slli_rs2_addr, Mux(spec_insn_andi_valid, spec_insn_andi_rs2_addr, Mux(spec_insn_ori_valid, spec_insn_ori_rs2_addr, Mux(spec_insn_xori_valid, spec_insn_xori_rs2_addr, Mux(spec_insn_sltiu_valid, spec_insn_sltiu_rs2_addr, Mux(spec_insn_slti_valid, spec_insn_slti_rs2_addr, Mux(spec_insn_addi_valid, spec_insn_addi_rs2_addr, Mux(spec_insn_sw_valid, spec_insn_sw_rs2_addr, Mux(spec_insn_sh_valid, spec_insn_sh_rs2_addr, Mux(spec_insn_sb_valid, spec_insn_sb_rs2_addr, Mux(spec_insn_lhu_valid, spec_insn_lhu_rs2_addr, Mux(spec_insn_lbu_valid, spec_insn_lbu_rs2_addr, Mux(spec_insn_lw_valid, spec_insn_lw_rs2_addr, Mux(spec_insn_lh_valid, spec_insn_lh_rs2_addr, Mux(spec_insn_lb_valid, spec_insn_lb_rs2_addr, Mux(spec_insn_bgeu_valid, spec_insn_bgeu_rs2_addr, Mux(spec_insn_bltu_valid, spec_insn_bltu_rs2_addr, Mux(spec_insn_bge_valid, spec_insn_bge_rs2_addr, Mux(spec_insn_blt_valid, spec_insn_blt_rs2_addr, Mux(spec_insn_bne_valid, spec_insn_bne_rs2_addr, Mux(spec_insn_beq_valid, spec_insn_beq_rs2_addr, Mux(spec_insn_jalr_valid, spec_insn_jalr_rs2_addr, Mux(spec_insn_jal_valid, spec_insn_jal_rs2_addr, Mux(spec_insn_auipc_valid, spec_insn_auipc_rs2_addr, Mux(spec_insn_lui_valid, spec_insn_lui_rs2_addr, 0)))))))))))))))))))))))))))))))))))))) - m.d.comb += self.spec_rd_addr.eq(Mux(spec_insn_and_valid, spec_insn_and_rd_addr, Mux(spec_insn_or_valid, spec_insn_or_rd_addr, Mux(spec_insn_sra_valid, spec_insn_sra_rd_addr, Mux(spec_insn_srl_valid, spec_insn_srl_rd_addr, Mux(spec_insn_xor_valid, spec_insn_xor_rd_addr, Mux(spec_insn_sltu_valid, spec_insn_sltu_rd_addr, Mux(spec_insn_slt_valid, spec_insn_slt_rd_addr, Mux(spec_insn_sll_valid, spec_insn_sll_rd_addr, Mux(spec_insn_sub_valid, spec_insn_sub_rd_addr, Mux(spec_insn_add_valid, spec_insn_add_rd_addr, Mux(spec_insn_srai_valid, spec_insn_srai_rd_addr, Mux(spec_insn_srli_valid, spec_insn_srli_rd_addr, Mux(spec_insn_slli_valid, spec_insn_slli_rd_addr, Mux(spec_insn_andi_valid, spec_insn_andi_rd_addr, Mux(spec_insn_ori_valid, spec_insn_ori_rd_addr, Mux(spec_insn_xori_valid, spec_insn_xori_rd_addr, Mux(spec_insn_sltiu_valid, spec_insn_sltiu_rd_addr, Mux(spec_insn_slti_valid, spec_insn_slti_rd_addr, Mux(spec_insn_addi_valid, spec_insn_addi_rd_addr, Mux(spec_insn_sw_valid, spec_insn_sw_rd_addr, Mux(spec_insn_sh_valid, spec_insn_sh_rd_addr, Mux(spec_insn_sb_valid, spec_insn_sb_rd_addr, Mux(spec_insn_lhu_valid, spec_insn_lhu_rd_addr, Mux(spec_insn_lbu_valid, spec_insn_lbu_rd_addr, Mux(spec_insn_lw_valid, spec_insn_lw_rd_addr, Mux(spec_insn_lh_valid, spec_insn_lh_rd_addr, Mux(spec_insn_lb_valid, spec_insn_lb_rd_addr, Mux(spec_insn_bgeu_valid, spec_insn_bgeu_rd_addr, Mux(spec_insn_bltu_valid, spec_insn_bltu_rd_addr, Mux(spec_insn_bge_valid, spec_insn_bge_rd_addr, Mux(spec_insn_blt_valid, spec_insn_blt_rd_addr, Mux(spec_insn_bne_valid, spec_insn_bne_rd_addr, Mux(spec_insn_beq_valid, spec_insn_beq_rd_addr, Mux(spec_insn_jalr_valid, spec_insn_jalr_rd_addr, Mux(spec_insn_jal_valid, spec_insn_jal_rd_addr, Mux(spec_insn_auipc_valid, spec_insn_auipc_rd_addr, Mux(spec_insn_lui_valid, spec_insn_lui_rd_addr, 0)))))))))))))))))))))))))))))))))))))) - m.d.comb += self.spec_rd_wdata.eq(Mux(spec_insn_and_valid, spec_insn_and_rd_wdata, Mux(spec_insn_or_valid, spec_insn_or_rd_wdata, Mux(spec_insn_sra_valid, spec_insn_sra_rd_wdata, Mux(spec_insn_srl_valid, spec_insn_srl_rd_wdata, Mux(spec_insn_xor_valid, spec_insn_xor_rd_wdata, Mux(spec_insn_sltu_valid, spec_insn_sltu_rd_wdata, Mux(spec_insn_slt_valid, spec_insn_slt_rd_wdata, Mux(spec_insn_sll_valid, spec_insn_sll_rd_wdata, Mux(spec_insn_sub_valid, spec_insn_sub_rd_wdata, Mux(spec_insn_add_valid, spec_insn_add_rd_wdata, Mux(spec_insn_srai_valid, spec_insn_srai_rd_wdata, Mux(spec_insn_srli_valid, spec_insn_srli_rd_wdata, Mux(spec_insn_slli_valid, spec_insn_slli_rd_wdata, Mux(spec_insn_andi_valid, spec_insn_andi_rd_wdata, Mux(spec_insn_ori_valid, spec_insn_ori_rd_wdata, Mux(spec_insn_xori_valid, spec_insn_xori_rd_wdata, Mux(spec_insn_sltiu_valid, spec_insn_sltiu_rd_wdata, Mux(spec_insn_slti_valid, spec_insn_slti_rd_wdata, Mux(spec_insn_addi_valid, spec_insn_addi_rd_wdata, Mux(spec_insn_sw_valid, spec_insn_sw_rd_wdata, Mux(spec_insn_sh_valid, spec_insn_sh_rd_wdata, Mux(spec_insn_sb_valid, spec_insn_sb_rd_wdata, Mux(spec_insn_lhu_valid, spec_insn_lhu_rd_wdata, Mux(spec_insn_lbu_valid, spec_insn_lbu_rd_wdata, Mux(spec_insn_lw_valid, spec_insn_lw_rd_wdata, Mux(spec_insn_lh_valid, spec_insn_lh_rd_wdata, Mux(spec_insn_lb_valid, spec_insn_lb_rd_wdata, Mux(spec_insn_bgeu_valid, spec_insn_bgeu_rd_wdata, Mux(spec_insn_bltu_valid, spec_insn_bltu_rd_wdata, Mux(spec_insn_bge_valid, spec_insn_bge_rd_wdata, Mux(spec_insn_blt_valid, spec_insn_blt_rd_wdata, Mux(spec_insn_bne_valid, spec_insn_bne_rd_wdata, Mux(spec_insn_beq_valid, spec_insn_beq_rd_wdata, Mux(spec_insn_jalr_valid, spec_insn_jalr_rd_wdata, Mux(spec_insn_jal_valid, spec_insn_jal_rd_wdata, Mux(spec_insn_auipc_valid, spec_insn_auipc_rd_wdata, Mux(spec_insn_lui_valid, spec_insn_lui_rd_wdata, 0)))))))))))))))))))))))))))))))))))))) - m.d.comb += self.spec_pc_wdata.eq(Mux(spec_insn_and_valid, spec_insn_and_pc_wdata, Mux(spec_insn_or_valid, spec_insn_or_pc_wdata, Mux(spec_insn_sra_valid, spec_insn_sra_pc_wdata, Mux(spec_insn_srl_valid, spec_insn_srl_pc_wdata, Mux(spec_insn_xor_valid, spec_insn_xor_pc_wdata, Mux(spec_insn_sltu_valid, spec_insn_sltu_pc_wdata, Mux(spec_insn_slt_valid, spec_insn_slt_pc_wdata, Mux(spec_insn_sll_valid, spec_insn_sll_pc_wdata, Mux(spec_insn_sub_valid, spec_insn_sub_pc_wdata, Mux(spec_insn_add_valid, spec_insn_add_pc_wdata, Mux(spec_insn_srai_valid, spec_insn_srai_pc_wdata, Mux(spec_insn_srli_valid, spec_insn_srli_pc_wdata, Mux(spec_insn_slli_valid, spec_insn_slli_pc_wdata, Mux(spec_insn_andi_valid, spec_insn_andi_pc_wdata, Mux(spec_insn_ori_valid, spec_insn_ori_pc_wdata, Mux(spec_insn_xori_valid, spec_insn_xori_pc_wdata, Mux(spec_insn_sltiu_valid, spec_insn_sltiu_pc_wdata, Mux(spec_insn_slti_valid, spec_insn_slti_pc_wdata, Mux(spec_insn_addi_valid, spec_insn_addi_pc_wdata, Mux(spec_insn_sw_valid, spec_insn_sw_pc_wdata, Mux(spec_insn_sh_valid, spec_insn_sh_pc_wdata, Mux(spec_insn_sb_valid, spec_insn_sb_pc_wdata, Mux(spec_insn_lhu_valid, spec_insn_lhu_pc_wdata, Mux(spec_insn_lbu_valid, spec_insn_lbu_pc_wdata, Mux(spec_insn_lw_valid, spec_insn_lw_pc_wdata, Mux(spec_insn_lh_valid, spec_insn_lh_pc_wdata, Mux(spec_insn_lb_valid, spec_insn_lb_pc_wdata, Mux(spec_insn_bgeu_valid, spec_insn_bgeu_pc_wdata, Mux(spec_insn_bltu_valid, spec_insn_bltu_pc_wdata, Mux(spec_insn_bge_valid, spec_insn_bge_pc_wdata, Mux(spec_insn_blt_valid, spec_insn_blt_pc_wdata, Mux(spec_insn_bne_valid, spec_insn_bne_pc_wdata, Mux(spec_insn_beq_valid, spec_insn_beq_pc_wdata, Mux(spec_insn_jalr_valid, spec_insn_jalr_pc_wdata, Mux(spec_insn_jal_valid, spec_insn_jal_pc_wdata, Mux(spec_insn_auipc_valid, spec_insn_auipc_pc_wdata, Mux(spec_insn_lui_valid, spec_insn_lui_pc_wdata, 0)))))))))))))))))))))))))))))))))))))) - m.d.comb += self.spec_mem_addr.eq(Mux(spec_insn_and_valid, spec_insn_and_mem_addr, Mux(spec_insn_or_valid, spec_insn_or_mem_addr, Mux(spec_insn_sra_valid, spec_insn_sra_mem_addr, Mux(spec_insn_srl_valid, spec_insn_srl_mem_addr, Mux(spec_insn_xor_valid, spec_insn_xor_mem_addr, Mux(spec_insn_sltu_valid, spec_insn_sltu_mem_addr, Mux(spec_insn_slt_valid, spec_insn_slt_mem_addr, Mux(spec_insn_sll_valid, spec_insn_sll_mem_addr, Mux(spec_insn_sub_valid, spec_insn_sub_mem_addr, Mux(spec_insn_add_valid, spec_insn_add_mem_addr, Mux(spec_insn_srai_valid, spec_insn_srai_mem_addr, Mux(spec_insn_srli_valid, spec_insn_srli_mem_addr, Mux(spec_insn_slli_valid, spec_insn_slli_mem_addr, Mux(spec_insn_andi_valid, spec_insn_andi_mem_addr, Mux(spec_insn_ori_valid, spec_insn_ori_mem_addr, Mux(spec_insn_xori_valid, spec_insn_xori_mem_addr, Mux(spec_insn_sltiu_valid, spec_insn_sltiu_mem_addr, Mux(spec_insn_slti_valid, spec_insn_slti_mem_addr, Mux(spec_insn_addi_valid, spec_insn_addi_mem_addr, Mux(spec_insn_sw_valid, spec_insn_sw_mem_addr, Mux(spec_insn_sh_valid, spec_insn_sh_mem_addr, Mux(spec_insn_sb_valid, spec_insn_sb_mem_addr, Mux(spec_insn_lhu_valid, spec_insn_lhu_mem_addr, Mux(spec_insn_lbu_valid, spec_insn_lbu_mem_addr, Mux(spec_insn_lw_valid, spec_insn_lw_mem_addr, Mux(spec_insn_lh_valid, spec_insn_lh_mem_addr, Mux(spec_insn_lb_valid, spec_insn_lb_mem_addr, Mux(spec_insn_bgeu_valid, spec_insn_bgeu_mem_addr, Mux(spec_insn_bltu_valid, spec_insn_bltu_mem_addr, Mux(spec_insn_bge_valid, spec_insn_bge_mem_addr, Mux(spec_insn_blt_valid, spec_insn_blt_mem_addr, Mux(spec_insn_bne_valid, spec_insn_bne_mem_addr, Mux(spec_insn_beq_valid, spec_insn_beq_mem_addr, Mux(spec_insn_jalr_valid, spec_insn_jalr_mem_addr, Mux(spec_insn_jal_valid, spec_insn_jal_mem_addr, Mux(spec_insn_auipc_valid, spec_insn_auipc_mem_addr, Mux(spec_insn_lui_valid, spec_insn_lui_mem_addr, 0)))))))))))))))))))))))))))))))))))))) - m.d.comb += self.spec_mem_rmask.eq(Mux(spec_insn_and_valid, spec_insn_and_mem_rmask, Mux(spec_insn_or_valid, spec_insn_or_mem_rmask, Mux(spec_insn_sra_valid, spec_insn_sra_mem_rmask, Mux(spec_insn_srl_valid, spec_insn_srl_mem_rmask, Mux(spec_insn_xor_valid, spec_insn_xor_mem_rmask, Mux(spec_insn_sltu_valid, spec_insn_sltu_mem_rmask, Mux(spec_insn_slt_valid, spec_insn_slt_mem_rmask, Mux(spec_insn_sll_valid, spec_insn_sll_mem_rmask, Mux(spec_insn_sub_valid, spec_insn_sub_mem_rmask, Mux(spec_insn_add_valid, spec_insn_add_mem_rmask, Mux(spec_insn_srai_valid, spec_insn_srai_mem_rmask, Mux(spec_insn_srli_valid, spec_insn_srli_mem_rmask, Mux(spec_insn_slli_valid, spec_insn_slli_mem_rmask, Mux(spec_insn_andi_valid, spec_insn_andi_mem_rmask, Mux(spec_insn_ori_valid, spec_insn_ori_mem_rmask, Mux(spec_insn_xori_valid, spec_insn_xori_mem_rmask, Mux(spec_insn_sltiu_valid, spec_insn_sltiu_mem_rmask, Mux(spec_insn_slti_valid, spec_insn_slti_mem_rmask, Mux(spec_insn_addi_valid, spec_insn_addi_mem_rmask, Mux(spec_insn_sw_valid, spec_insn_sw_mem_rmask, Mux(spec_insn_sh_valid, spec_insn_sh_mem_rmask, Mux(spec_insn_sb_valid, spec_insn_sb_mem_rmask, Mux(spec_insn_lhu_valid, spec_insn_lhu_mem_rmask, Mux(spec_insn_lbu_valid, spec_insn_lbu_mem_rmask, Mux(spec_insn_lw_valid, spec_insn_lw_mem_rmask, Mux(spec_insn_lh_valid, spec_insn_lh_mem_rmask, Mux(spec_insn_lb_valid, spec_insn_lb_mem_rmask, Mux(spec_insn_bgeu_valid, spec_insn_bgeu_mem_rmask, Mux(spec_insn_bltu_valid, spec_insn_bltu_mem_rmask, Mux(spec_insn_bge_valid, spec_insn_bge_mem_rmask, Mux(spec_insn_blt_valid, spec_insn_blt_mem_rmask, Mux(spec_insn_bne_valid, spec_insn_bne_mem_rmask, Mux(spec_insn_beq_valid, spec_insn_beq_mem_rmask, Mux(spec_insn_jalr_valid, spec_insn_jalr_mem_rmask, Mux(spec_insn_jal_valid, spec_insn_jal_mem_rmask, Mux(spec_insn_auipc_valid, spec_insn_auipc_mem_rmask, Mux(spec_insn_lui_valid, spec_insn_lui_mem_rmask, 0)))))))))))))))))))))))))))))))))))))) - m.d.comb += self.spec_mem_wmask.eq(Mux(spec_insn_and_valid, spec_insn_and_mem_wmask, Mux(spec_insn_or_valid, spec_insn_or_mem_wmask, Mux(spec_insn_sra_valid, spec_insn_sra_mem_wmask, Mux(spec_insn_srl_valid, spec_insn_srl_mem_wmask, Mux(spec_insn_xor_valid, spec_insn_xor_mem_wmask, Mux(spec_insn_sltu_valid, spec_insn_sltu_mem_wmask, Mux(spec_insn_slt_valid, spec_insn_slt_mem_wmask, Mux(spec_insn_sll_valid, spec_insn_sll_mem_wmask, Mux(spec_insn_sub_valid, spec_insn_sub_mem_wmask, Mux(spec_insn_add_valid, spec_insn_add_mem_wmask, Mux(spec_insn_srai_valid, spec_insn_srai_mem_wmask, Mux(spec_insn_srli_valid, spec_insn_srli_mem_wmask, Mux(spec_insn_slli_valid, spec_insn_slli_mem_wmask, Mux(spec_insn_andi_valid, spec_insn_andi_mem_wmask, Mux(spec_insn_ori_valid, spec_insn_ori_mem_wmask, Mux(spec_insn_xori_valid, spec_insn_xori_mem_wmask, Mux(spec_insn_sltiu_valid, spec_insn_sltiu_mem_wmask, Mux(spec_insn_slti_valid, spec_insn_slti_mem_wmask, Mux(spec_insn_addi_valid, spec_insn_addi_mem_wmask, Mux(spec_insn_sw_valid, spec_insn_sw_mem_wmask, Mux(spec_insn_sh_valid, spec_insn_sh_mem_wmask, Mux(spec_insn_sb_valid, spec_insn_sb_mem_wmask, Mux(spec_insn_lhu_valid, spec_insn_lhu_mem_wmask, Mux(spec_insn_lbu_valid, spec_insn_lbu_mem_wmask, Mux(spec_insn_lw_valid, spec_insn_lw_mem_wmask, Mux(spec_insn_lh_valid, spec_insn_lh_mem_wmask, Mux(spec_insn_lb_valid, spec_insn_lb_mem_wmask, Mux(spec_insn_bgeu_valid, spec_insn_bgeu_mem_wmask, Mux(spec_insn_bltu_valid, spec_insn_bltu_mem_wmask, Mux(spec_insn_bge_valid, spec_insn_bge_mem_wmask, Mux(spec_insn_blt_valid, spec_insn_blt_mem_wmask, Mux(spec_insn_bne_valid, spec_insn_bne_mem_wmask, Mux(spec_insn_beq_valid, spec_insn_beq_mem_wmask, Mux(spec_insn_jalr_valid, spec_insn_jalr_mem_wmask, Mux(spec_insn_jal_valid, spec_insn_jal_mem_wmask, Mux(spec_insn_auipc_valid, spec_insn_auipc_mem_wmask, Mux(spec_insn_lui_valid, spec_insn_lui_mem_wmask, 0)))))))))))))))))))))))))))))))))))))) - m.d.comb += self.spec_mem_wdata.eq(Mux(spec_insn_and_valid, spec_insn_and_mem_wdata, Mux(spec_insn_or_valid, spec_insn_or_mem_wdata, Mux(spec_insn_sra_valid, spec_insn_sra_mem_wdata, Mux(spec_insn_srl_valid, spec_insn_srl_mem_wdata, Mux(spec_insn_xor_valid, spec_insn_xor_mem_wdata, Mux(spec_insn_sltu_valid, spec_insn_sltu_mem_wdata, Mux(spec_insn_slt_valid, spec_insn_slt_mem_wdata, Mux(spec_insn_sll_valid, spec_insn_sll_mem_wdata, Mux(spec_insn_sub_valid, spec_insn_sub_mem_wdata, Mux(spec_insn_add_valid, spec_insn_add_mem_wdata, Mux(spec_insn_srai_valid, spec_insn_srai_mem_wdata, Mux(spec_insn_srli_valid, spec_insn_srli_mem_wdata, Mux(spec_insn_slli_valid, spec_insn_slli_mem_wdata, Mux(spec_insn_andi_valid, spec_insn_andi_mem_wdata, Mux(spec_insn_ori_valid, spec_insn_ori_mem_wdata, Mux(spec_insn_xori_valid, spec_insn_xori_mem_wdata, Mux(spec_insn_sltiu_valid, spec_insn_sltiu_mem_wdata, Mux(spec_insn_slti_valid, spec_insn_slti_mem_wdata, Mux(spec_insn_addi_valid, spec_insn_addi_mem_wdata, Mux(spec_insn_sw_valid, spec_insn_sw_mem_wdata, Mux(spec_insn_sh_valid, spec_insn_sh_mem_wdata, Mux(spec_insn_sb_valid, spec_insn_sb_mem_wdata, Mux(spec_insn_lhu_valid, spec_insn_lhu_mem_wdata, Mux(spec_insn_lbu_valid, spec_insn_lbu_mem_wdata, Mux(spec_insn_lw_valid, spec_insn_lw_mem_wdata, Mux(spec_insn_lh_valid, spec_insn_lh_mem_wdata, Mux(spec_insn_lb_valid, spec_insn_lb_mem_wdata, Mux(spec_insn_bgeu_valid, spec_insn_bgeu_mem_wdata, Mux(spec_insn_bltu_valid, spec_insn_bltu_mem_wdata, Mux(spec_insn_bge_valid, spec_insn_bge_mem_wdata, Mux(spec_insn_blt_valid, spec_insn_blt_mem_wdata, Mux(spec_insn_bne_valid, spec_insn_bne_mem_wdata, Mux(spec_insn_beq_valid, spec_insn_beq_mem_wdata, Mux(spec_insn_jalr_valid, spec_insn_jalr_mem_wdata, Mux(spec_insn_jal_valid, spec_insn_jal_mem_wdata, Mux(spec_insn_auipc_valid, spec_insn_auipc_mem_wdata, Mux(spec_insn_lui_valid, spec_insn_lui_mem_wdata, 0)))))))))))))))))))))))))))))))))))))) - - return m diff --git a/insns/isa_rv32i.txt b/insns/isa_rv32i.txt deleted file mode 100644 index ad4c10b..0000000 --- a/insns/isa_rv32i.txt +++ /dev/null @@ -1,37 +0,0 @@ -lui -auipc -jal -jalr -beq -bne -blt -bge -bltu -bgeu -lb -lh -lw -lbu -lhu -sb -sh -sw -addi -slti -sltiu -xori -ori -andi -slli -srli -srai -add -sub -sll -slt -sltu -xor -srl -sra -or -and diff --git a/insns/isa_rv32i_gen.py b/insns/isa_rv32i_gen.py deleted file mode 100644 index 8c692b1..0000000 --- a/insns/isa_rv32i_gen.py +++ /dev/null @@ -1,107 +0,0 @@ -with open('isa_rv32i.py', 'w') as isa_rv32i: - def fprint(strng): - print(strng, file=isa_rv32i) - fprint("# Generated by isa_rv32i_gen.py") - fprint("from nmigen import *") - with open('isa_rv32i.txt', 'r') as isa_rv32i_txt_file: - isa_rv32i_insns = isa_rv32i_txt_file.read().split('\n')[:-1] - for isa_rv32i_insn in isa_rv32i_insns: - fprint("from insn_%s import *" % isa_rv32i_insn) - fprint("") - fprint("class rvfi_isa_rv32i(Elaboratable):") - fprint(" def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):") - fprint(" self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN") - fprint(" self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN") - fprint(" self.rvfi_valid = Signal(1)") - fprint(" self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)") - fprint(" self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)") - fprint(" self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)") - fprint(" self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)") - fprint(" self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)") - fprint("") - fprint(" self.spec_valid = Signal(1)") - fprint(" self.spec_trap = Signal(1)") - fprint(" self.spec_rs1_addr = Signal(5)") - fprint(" self.spec_rs2_addr = Signal(5)") - fprint(" self.spec_rd_addr = Signal(5)") - fprint(" self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)") - fprint(" self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)") - fprint(" self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)") - fprint(" self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))") - fprint(" self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))") - fprint(" self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)") - fprint(" def ports(self):") - fprint(" input_ports = [") - fprint(" self.rvfi_valid,") - fprint(" self.rvfi_insn,") - fprint(" self.rvfi_pc_rdata,") - fprint(" self.rvfi_rs1_rdata,") - fprint(" self.rvfi_rs2_rdata,") - fprint(" self.rvfi_mem_rdata") - fprint(" ]") - fprint(" output_ports = [") - fprint(" self.spec_valid,") - fprint(" self.spec_trap,") - fprint(" self.spec_rs1_addr,") - fprint(" self.spec_rs2_addr,") - fprint(" self.spec_rd_addr,") - fprint(" self.spec_rd_wdata,") - fprint(" self.spec_pc_wdata,") - fprint(" self.spec_mem_addr,") - fprint(" self.spec_mem_rmask,") - fprint(" self.spec_mem_wmask,") - fprint(" self.spec_mem_wdata") - fprint(" ]") - fprint(" return input_ports + output_ports") - fprint(" def elaborate(self, platform):") - fprint(" m = Module()") - fprint("") - for isa_rv32i_insn in isa_rv32i_insns: - fprint(" spec_insn_%s_valid = Signal(1)" % isa_rv32i_insn) - fprint(" spec_insn_%s_trap = Signal(1)" % isa_rv32i_insn) - fprint(" spec_insn_%s_rs1_addr = Signal(5)" % isa_rv32i_insn) - fprint(" spec_insn_%s_rs2_addr = Signal(5)" % isa_rv32i_insn) - fprint(" spec_insn_%s_rd_addr = Signal(5)" % isa_rv32i_insn) - fprint(" spec_insn_%s_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)" % isa_rv32i_insn) - fprint(" spec_insn_%s_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)" % isa_rv32i_insn) - fprint(" spec_insn_%s_mem_addr = Signal(self.RISCV_FORMAL_XLEN)" % isa_rv32i_insn) - fprint(" spec_insn_%s_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))" % isa_rv32i_insn) - fprint(" spec_insn_%s_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))" % isa_rv32i_insn) - fprint(" spec_insn_%s_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)" % isa_rv32i_insn) - fprint(" m.submodules.insn_%s = insn_%s = rvfi_insn_%s()" % (isa_rv32i_insn, isa_rv32i_insn, isa_rv32i_insn)) - fprint(" m.d.comb += insn_%s.rvfi_valid.eq(self.rvfi_valid)" % isa_rv32i_insn) - fprint(" m.d.comb += insn_%s.rvfi_insn.eq(self.rvfi_insn)" % isa_rv32i_insn) - fprint(" m.d.comb += insn_%s.rvfi_pc_rdata.eq(self.rvfi_pc_rdata)" % isa_rv32i_insn) - fprint(" m.d.comb += insn_%s.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata)" % isa_rv32i_insn) - fprint(" m.d.comb += insn_%s.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata)" % isa_rv32i_insn) - fprint(" m.d.comb += insn_%s.rvfi_mem_rdata.eq(self.rvfi_mem_rdata)" % isa_rv32i_insn) - fprint(" m.d.comb += spec_insn_%s_valid.eq(insn_%s.spec_valid)" % (isa_rv32i_insn, isa_rv32i_insn)) - fprint(" m.d.comb += spec_insn_%s_trap.eq(insn_%s.spec_trap)" % (isa_rv32i_insn, isa_rv32i_insn)) - fprint(" m.d.comb += spec_insn_%s_rs1_addr.eq(insn_%s.spec_rs1_addr)" % (isa_rv32i_insn, isa_rv32i_insn)) - fprint(" m.d.comb += spec_insn_%s_rs2_addr.eq(insn_%s.spec_rs2_addr)" % (isa_rv32i_insn, isa_rv32i_insn)) - fprint(" m.d.comb += spec_insn_%s_rd_addr.eq(insn_%s.spec_rd_addr)" % (isa_rv32i_insn, isa_rv32i_insn)) - fprint(" m.d.comb += spec_insn_%s_rd_wdata.eq(insn_%s.spec_rd_wdata)" % (isa_rv32i_insn, isa_rv32i_insn)) - fprint(" m.d.comb += spec_insn_%s_pc_wdata.eq(insn_%s.spec_pc_wdata)" % (isa_rv32i_insn, isa_rv32i_insn)) - fprint(" m.d.comb += spec_insn_%s_mem_addr.eq(insn_%s.spec_mem_addr)" % (isa_rv32i_insn, isa_rv32i_insn)) - fprint(" m.d.comb += spec_insn_%s_mem_rmask.eq(insn_%s.spec_mem_rmask)" % (isa_rv32i_insn, isa_rv32i_insn)) - fprint(" m.d.comb += spec_insn_%s_mem_wmask.eq(insn_%s.spec_mem_wmask)" % (isa_rv32i_insn, isa_rv32i_insn)) - fprint(" m.d.comb += spec_insn_%s_mem_wdata.eq(insn_%s.spec_mem_wdata)" % (isa_rv32i_insn, isa_rv32i_insn)) - fprint("") - def gen_spec(strng): - result = "0" - for isa_rv32i_insn in isa_rv32i_insns: - result = "Mux(spec_insn_%s_valid, spec_insn_%s_%s, %s)" % (isa_rv32i_insn, isa_rv32i_insn, strng, result) - fprint(" m.d.comb += self.spec_%s.eq(%s)" % (strng, result)) - gen_spec("valid") - gen_spec("trap") - gen_spec("rs1_addr") - gen_spec("rs2_addr") - gen_spec("rd_addr") - gen_spec("rd_wdata") - gen_spec("pc_wdata") - gen_spec("mem_addr") - gen_spec("mem_rmask") - gen_spec("mem_wmask") - gen_spec("mem_wdata") - fprint("") - fprint(" return m") diff --git a/insns/isa_rv32im.py b/insns/isa_rv32im.py deleted file mode 100644 index 40fba37..0000000 --- a/insns/isa_rv32im.py +++ /dev/null @@ -1,1459 +0,0 @@ -# Generated by isa_rv32im_gen.py -from nmigen import * -from insn_lui import * -from insn_auipc import * -from insn_jal import * -from insn_jalr import * -from insn_beq import * -from insn_bne import * -from insn_blt import * -from insn_bge import * -from insn_bltu import * -from insn_bgeu import * -from insn_lb import * -from insn_lh import * -from insn_lw import * -from insn_lbu import * -from insn_lhu import * -from insn_sb import * -from insn_sh import * -from insn_sw import * -from insn_addi import * -from insn_slti import * -from insn_sltiu import * -from insn_xori import * -from insn_ori import * -from insn_andi import * -from insn_slli import * -from insn_srli import * -from insn_srai import * -from insn_add import * -from insn_sub import * -from insn_sll import * -from insn_slt import * -from insn_sltu import * -from insn_xor import * -from insn_srl import * -from insn_sra import * -from insn_or import * -from insn_and import * -from insn_mul import * -from insn_mulh import * -from insn_mulhsu import * -from insn_mulhu import * -from insn_div import * -from insn_divu import * -from insn_rem import * -from insn_remu import * - -class rvfi_isa_rv32im(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - spec_insn_lui_valid = Signal(1) - spec_insn_lui_trap = Signal(1) - spec_insn_lui_rs1_addr = Signal(5) - spec_insn_lui_rs2_addr = Signal(5) - spec_insn_lui_rd_addr = Signal(5) - spec_insn_lui_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lui_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lui_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lui_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_lui_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_lui_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_lui = insn_lui = rvfi_insn_lui() - m.d.comb += insn_lui.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_lui.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_lui.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_lui.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_lui.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_lui.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_lui_valid.eq(insn_lui.spec_valid) - m.d.comb += spec_insn_lui_trap.eq(insn_lui.spec_trap) - m.d.comb += spec_insn_lui_rs1_addr.eq(insn_lui.spec_rs1_addr) - m.d.comb += spec_insn_lui_rs2_addr.eq(insn_lui.spec_rs2_addr) - m.d.comb += spec_insn_lui_rd_addr.eq(insn_lui.spec_rd_addr) - m.d.comb += spec_insn_lui_rd_wdata.eq(insn_lui.spec_rd_wdata) - m.d.comb += spec_insn_lui_pc_wdata.eq(insn_lui.spec_pc_wdata) - m.d.comb += spec_insn_lui_mem_addr.eq(insn_lui.spec_mem_addr) - m.d.comb += spec_insn_lui_mem_rmask.eq(insn_lui.spec_mem_rmask) - m.d.comb += spec_insn_lui_mem_wmask.eq(insn_lui.spec_mem_wmask) - m.d.comb += spec_insn_lui_mem_wdata.eq(insn_lui.spec_mem_wdata) - - spec_insn_auipc_valid = Signal(1) - spec_insn_auipc_trap = Signal(1) - spec_insn_auipc_rs1_addr = Signal(5) - spec_insn_auipc_rs2_addr = Signal(5) - spec_insn_auipc_rd_addr = Signal(5) - spec_insn_auipc_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_auipc_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_auipc_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_auipc_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_auipc_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_auipc_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_auipc = insn_auipc = rvfi_insn_auipc() - m.d.comb += insn_auipc.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_auipc.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_auipc.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_auipc.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_auipc.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_auipc.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_auipc_valid.eq(insn_auipc.spec_valid) - m.d.comb += spec_insn_auipc_trap.eq(insn_auipc.spec_trap) - m.d.comb += spec_insn_auipc_rs1_addr.eq(insn_auipc.spec_rs1_addr) - m.d.comb += spec_insn_auipc_rs2_addr.eq(insn_auipc.spec_rs2_addr) - m.d.comb += spec_insn_auipc_rd_addr.eq(insn_auipc.spec_rd_addr) - m.d.comb += spec_insn_auipc_rd_wdata.eq(insn_auipc.spec_rd_wdata) - m.d.comb += spec_insn_auipc_pc_wdata.eq(insn_auipc.spec_pc_wdata) - m.d.comb += spec_insn_auipc_mem_addr.eq(insn_auipc.spec_mem_addr) - m.d.comb += spec_insn_auipc_mem_rmask.eq(insn_auipc.spec_mem_rmask) - m.d.comb += spec_insn_auipc_mem_wmask.eq(insn_auipc.spec_mem_wmask) - m.d.comb += spec_insn_auipc_mem_wdata.eq(insn_auipc.spec_mem_wdata) - - spec_insn_jal_valid = Signal(1) - spec_insn_jal_trap = Signal(1) - spec_insn_jal_rs1_addr = Signal(5) - spec_insn_jal_rs2_addr = Signal(5) - spec_insn_jal_rd_addr = Signal(5) - spec_insn_jal_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_jal_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_jal_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_jal_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_jal_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_jal_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_jal = insn_jal = rvfi_insn_jal() - m.d.comb += insn_jal.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_jal.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_jal.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_jal.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_jal.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_jal.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_jal_valid.eq(insn_jal.spec_valid) - m.d.comb += spec_insn_jal_trap.eq(insn_jal.spec_trap) - m.d.comb += spec_insn_jal_rs1_addr.eq(insn_jal.spec_rs1_addr) - m.d.comb += spec_insn_jal_rs2_addr.eq(insn_jal.spec_rs2_addr) - m.d.comb += spec_insn_jal_rd_addr.eq(insn_jal.spec_rd_addr) - m.d.comb += spec_insn_jal_rd_wdata.eq(insn_jal.spec_rd_wdata) - m.d.comb += spec_insn_jal_pc_wdata.eq(insn_jal.spec_pc_wdata) - m.d.comb += spec_insn_jal_mem_addr.eq(insn_jal.spec_mem_addr) - m.d.comb += spec_insn_jal_mem_rmask.eq(insn_jal.spec_mem_rmask) - m.d.comb += spec_insn_jal_mem_wmask.eq(insn_jal.spec_mem_wmask) - m.d.comb += spec_insn_jal_mem_wdata.eq(insn_jal.spec_mem_wdata) - - spec_insn_jalr_valid = Signal(1) - spec_insn_jalr_trap = Signal(1) - spec_insn_jalr_rs1_addr = Signal(5) - spec_insn_jalr_rs2_addr = Signal(5) - spec_insn_jalr_rd_addr = Signal(5) - spec_insn_jalr_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_jalr_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_jalr_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_jalr_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_jalr_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_jalr_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_jalr = insn_jalr = rvfi_insn_jalr() - m.d.comb += insn_jalr.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_jalr.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_jalr.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_jalr.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_jalr.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_jalr.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_jalr_valid.eq(insn_jalr.spec_valid) - m.d.comb += spec_insn_jalr_trap.eq(insn_jalr.spec_trap) - m.d.comb += spec_insn_jalr_rs1_addr.eq(insn_jalr.spec_rs1_addr) - m.d.comb += spec_insn_jalr_rs2_addr.eq(insn_jalr.spec_rs2_addr) - m.d.comb += spec_insn_jalr_rd_addr.eq(insn_jalr.spec_rd_addr) - m.d.comb += spec_insn_jalr_rd_wdata.eq(insn_jalr.spec_rd_wdata) - m.d.comb += spec_insn_jalr_pc_wdata.eq(insn_jalr.spec_pc_wdata) - m.d.comb += spec_insn_jalr_mem_addr.eq(insn_jalr.spec_mem_addr) - m.d.comb += spec_insn_jalr_mem_rmask.eq(insn_jalr.spec_mem_rmask) - m.d.comb += spec_insn_jalr_mem_wmask.eq(insn_jalr.spec_mem_wmask) - m.d.comb += spec_insn_jalr_mem_wdata.eq(insn_jalr.spec_mem_wdata) - - spec_insn_beq_valid = Signal(1) - spec_insn_beq_trap = Signal(1) - spec_insn_beq_rs1_addr = Signal(5) - spec_insn_beq_rs2_addr = Signal(5) - spec_insn_beq_rd_addr = Signal(5) - spec_insn_beq_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_beq_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_beq_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_beq_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_beq_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_beq_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_beq = insn_beq = rvfi_insn_beq() - m.d.comb += insn_beq.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_beq.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_beq.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_beq.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_beq.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_beq.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_beq_valid.eq(insn_beq.spec_valid) - m.d.comb += spec_insn_beq_trap.eq(insn_beq.spec_trap) - m.d.comb += spec_insn_beq_rs1_addr.eq(insn_beq.spec_rs1_addr) - m.d.comb += spec_insn_beq_rs2_addr.eq(insn_beq.spec_rs2_addr) - m.d.comb += spec_insn_beq_rd_addr.eq(insn_beq.spec_rd_addr) - m.d.comb += spec_insn_beq_rd_wdata.eq(insn_beq.spec_rd_wdata) - m.d.comb += spec_insn_beq_pc_wdata.eq(insn_beq.spec_pc_wdata) - m.d.comb += spec_insn_beq_mem_addr.eq(insn_beq.spec_mem_addr) - m.d.comb += spec_insn_beq_mem_rmask.eq(insn_beq.spec_mem_rmask) - m.d.comb += spec_insn_beq_mem_wmask.eq(insn_beq.spec_mem_wmask) - m.d.comb += spec_insn_beq_mem_wdata.eq(insn_beq.spec_mem_wdata) - - spec_insn_bne_valid = Signal(1) - spec_insn_bne_trap = Signal(1) - spec_insn_bne_rs1_addr = Signal(5) - spec_insn_bne_rs2_addr = Signal(5) - spec_insn_bne_rd_addr = Signal(5) - spec_insn_bne_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_bne_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_bne_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_bne_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_bne_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_bne_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_bne = insn_bne = rvfi_insn_bne() - m.d.comb += insn_bne.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_bne.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_bne.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_bne.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_bne.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_bne.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_bne_valid.eq(insn_bne.spec_valid) - m.d.comb += spec_insn_bne_trap.eq(insn_bne.spec_trap) - m.d.comb += spec_insn_bne_rs1_addr.eq(insn_bne.spec_rs1_addr) - m.d.comb += spec_insn_bne_rs2_addr.eq(insn_bne.spec_rs2_addr) - m.d.comb += spec_insn_bne_rd_addr.eq(insn_bne.spec_rd_addr) - m.d.comb += spec_insn_bne_rd_wdata.eq(insn_bne.spec_rd_wdata) - m.d.comb += spec_insn_bne_pc_wdata.eq(insn_bne.spec_pc_wdata) - m.d.comb += spec_insn_bne_mem_addr.eq(insn_bne.spec_mem_addr) - m.d.comb += spec_insn_bne_mem_rmask.eq(insn_bne.spec_mem_rmask) - m.d.comb += spec_insn_bne_mem_wmask.eq(insn_bne.spec_mem_wmask) - m.d.comb += spec_insn_bne_mem_wdata.eq(insn_bne.spec_mem_wdata) - - spec_insn_blt_valid = Signal(1) - spec_insn_blt_trap = Signal(1) - spec_insn_blt_rs1_addr = Signal(5) - spec_insn_blt_rs2_addr = Signal(5) - spec_insn_blt_rd_addr = Signal(5) - spec_insn_blt_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_blt_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_blt_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_blt_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_blt_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_blt_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_blt = insn_blt = rvfi_insn_blt() - m.d.comb += insn_blt.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_blt.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_blt.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_blt.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_blt.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_blt.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_blt_valid.eq(insn_blt.spec_valid) - m.d.comb += spec_insn_blt_trap.eq(insn_blt.spec_trap) - m.d.comb += spec_insn_blt_rs1_addr.eq(insn_blt.spec_rs1_addr) - m.d.comb += spec_insn_blt_rs2_addr.eq(insn_blt.spec_rs2_addr) - m.d.comb += spec_insn_blt_rd_addr.eq(insn_blt.spec_rd_addr) - m.d.comb += spec_insn_blt_rd_wdata.eq(insn_blt.spec_rd_wdata) - m.d.comb += spec_insn_blt_pc_wdata.eq(insn_blt.spec_pc_wdata) - m.d.comb += spec_insn_blt_mem_addr.eq(insn_blt.spec_mem_addr) - m.d.comb += spec_insn_blt_mem_rmask.eq(insn_blt.spec_mem_rmask) - m.d.comb += spec_insn_blt_mem_wmask.eq(insn_blt.spec_mem_wmask) - m.d.comb += spec_insn_blt_mem_wdata.eq(insn_blt.spec_mem_wdata) - - spec_insn_bge_valid = Signal(1) - spec_insn_bge_trap = Signal(1) - spec_insn_bge_rs1_addr = Signal(5) - spec_insn_bge_rs2_addr = Signal(5) - spec_insn_bge_rd_addr = Signal(5) - spec_insn_bge_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_bge_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_bge_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_bge_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_bge_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_bge_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_bge = insn_bge = rvfi_insn_bge() - m.d.comb += insn_bge.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_bge.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_bge.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_bge.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_bge.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_bge.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_bge_valid.eq(insn_bge.spec_valid) - m.d.comb += spec_insn_bge_trap.eq(insn_bge.spec_trap) - m.d.comb += spec_insn_bge_rs1_addr.eq(insn_bge.spec_rs1_addr) - m.d.comb += spec_insn_bge_rs2_addr.eq(insn_bge.spec_rs2_addr) - m.d.comb += spec_insn_bge_rd_addr.eq(insn_bge.spec_rd_addr) - m.d.comb += spec_insn_bge_rd_wdata.eq(insn_bge.spec_rd_wdata) - m.d.comb += spec_insn_bge_pc_wdata.eq(insn_bge.spec_pc_wdata) - m.d.comb += spec_insn_bge_mem_addr.eq(insn_bge.spec_mem_addr) - m.d.comb += spec_insn_bge_mem_rmask.eq(insn_bge.spec_mem_rmask) - m.d.comb += spec_insn_bge_mem_wmask.eq(insn_bge.spec_mem_wmask) - m.d.comb += spec_insn_bge_mem_wdata.eq(insn_bge.spec_mem_wdata) - - spec_insn_bltu_valid = Signal(1) - spec_insn_bltu_trap = Signal(1) - spec_insn_bltu_rs1_addr = Signal(5) - spec_insn_bltu_rs2_addr = Signal(5) - spec_insn_bltu_rd_addr = Signal(5) - spec_insn_bltu_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_bltu_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_bltu_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_bltu_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_bltu_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_bltu_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_bltu = insn_bltu = rvfi_insn_bltu() - m.d.comb += insn_bltu.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_bltu.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_bltu.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_bltu.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_bltu.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_bltu.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_bltu_valid.eq(insn_bltu.spec_valid) - m.d.comb += spec_insn_bltu_trap.eq(insn_bltu.spec_trap) - m.d.comb += spec_insn_bltu_rs1_addr.eq(insn_bltu.spec_rs1_addr) - m.d.comb += spec_insn_bltu_rs2_addr.eq(insn_bltu.spec_rs2_addr) - m.d.comb += spec_insn_bltu_rd_addr.eq(insn_bltu.spec_rd_addr) - m.d.comb += spec_insn_bltu_rd_wdata.eq(insn_bltu.spec_rd_wdata) - m.d.comb += spec_insn_bltu_pc_wdata.eq(insn_bltu.spec_pc_wdata) - m.d.comb += spec_insn_bltu_mem_addr.eq(insn_bltu.spec_mem_addr) - m.d.comb += spec_insn_bltu_mem_rmask.eq(insn_bltu.spec_mem_rmask) - m.d.comb += spec_insn_bltu_mem_wmask.eq(insn_bltu.spec_mem_wmask) - m.d.comb += spec_insn_bltu_mem_wdata.eq(insn_bltu.spec_mem_wdata) - - spec_insn_bgeu_valid = Signal(1) - spec_insn_bgeu_trap = Signal(1) - spec_insn_bgeu_rs1_addr = Signal(5) - spec_insn_bgeu_rs2_addr = Signal(5) - spec_insn_bgeu_rd_addr = Signal(5) - spec_insn_bgeu_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_bgeu_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_bgeu_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_bgeu_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_bgeu_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_bgeu_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_bgeu = insn_bgeu = rvfi_insn_bgeu() - m.d.comb += insn_bgeu.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_bgeu.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_bgeu.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_bgeu.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_bgeu.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_bgeu.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_bgeu_valid.eq(insn_bgeu.spec_valid) - m.d.comb += spec_insn_bgeu_trap.eq(insn_bgeu.spec_trap) - m.d.comb += spec_insn_bgeu_rs1_addr.eq(insn_bgeu.spec_rs1_addr) - m.d.comb += spec_insn_bgeu_rs2_addr.eq(insn_bgeu.spec_rs2_addr) - m.d.comb += spec_insn_bgeu_rd_addr.eq(insn_bgeu.spec_rd_addr) - m.d.comb += spec_insn_bgeu_rd_wdata.eq(insn_bgeu.spec_rd_wdata) - m.d.comb += spec_insn_bgeu_pc_wdata.eq(insn_bgeu.spec_pc_wdata) - m.d.comb += spec_insn_bgeu_mem_addr.eq(insn_bgeu.spec_mem_addr) - m.d.comb += spec_insn_bgeu_mem_rmask.eq(insn_bgeu.spec_mem_rmask) - m.d.comb += spec_insn_bgeu_mem_wmask.eq(insn_bgeu.spec_mem_wmask) - m.d.comb += spec_insn_bgeu_mem_wdata.eq(insn_bgeu.spec_mem_wdata) - - spec_insn_lb_valid = Signal(1) - spec_insn_lb_trap = Signal(1) - spec_insn_lb_rs1_addr = Signal(5) - spec_insn_lb_rs2_addr = Signal(5) - spec_insn_lb_rd_addr = Signal(5) - spec_insn_lb_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lb_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lb_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lb_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_lb_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_lb_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_lb = insn_lb = rvfi_insn_lb() - m.d.comb += insn_lb.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_lb.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_lb.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_lb.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_lb.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_lb.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_lb_valid.eq(insn_lb.spec_valid) - m.d.comb += spec_insn_lb_trap.eq(insn_lb.spec_trap) - m.d.comb += spec_insn_lb_rs1_addr.eq(insn_lb.spec_rs1_addr) - m.d.comb += spec_insn_lb_rs2_addr.eq(insn_lb.spec_rs2_addr) - m.d.comb += spec_insn_lb_rd_addr.eq(insn_lb.spec_rd_addr) - m.d.comb += spec_insn_lb_rd_wdata.eq(insn_lb.spec_rd_wdata) - m.d.comb += spec_insn_lb_pc_wdata.eq(insn_lb.spec_pc_wdata) - m.d.comb += spec_insn_lb_mem_addr.eq(insn_lb.spec_mem_addr) - m.d.comb += spec_insn_lb_mem_rmask.eq(insn_lb.spec_mem_rmask) - m.d.comb += spec_insn_lb_mem_wmask.eq(insn_lb.spec_mem_wmask) - m.d.comb += spec_insn_lb_mem_wdata.eq(insn_lb.spec_mem_wdata) - - spec_insn_lh_valid = Signal(1) - spec_insn_lh_trap = Signal(1) - spec_insn_lh_rs1_addr = Signal(5) - spec_insn_lh_rs2_addr = Signal(5) - spec_insn_lh_rd_addr = Signal(5) - spec_insn_lh_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lh_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lh_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lh_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_lh_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_lh_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_lh = insn_lh = rvfi_insn_lh() - m.d.comb += insn_lh.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_lh.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_lh.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_lh.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_lh.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_lh.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_lh_valid.eq(insn_lh.spec_valid) - m.d.comb += spec_insn_lh_trap.eq(insn_lh.spec_trap) - m.d.comb += spec_insn_lh_rs1_addr.eq(insn_lh.spec_rs1_addr) - m.d.comb += spec_insn_lh_rs2_addr.eq(insn_lh.spec_rs2_addr) - m.d.comb += spec_insn_lh_rd_addr.eq(insn_lh.spec_rd_addr) - m.d.comb += spec_insn_lh_rd_wdata.eq(insn_lh.spec_rd_wdata) - m.d.comb += spec_insn_lh_pc_wdata.eq(insn_lh.spec_pc_wdata) - m.d.comb += spec_insn_lh_mem_addr.eq(insn_lh.spec_mem_addr) - m.d.comb += spec_insn_lh_mem_rmask.eq(insn_lh.spec_mem_rmask) - m.d.comb += spec_insn_lh_mem_wmask.eq(insn_lh.spec_mem_wmask) - m.d.comb += spec_insn_lh_mem_wdata.eq(insn_lh.spec_mem_wdata) - - spec_insn_lw_valid = Signal(1) - spec_insn_lw_trap = Signal(1) - spec_insn_lw_rs1_addr = Signal(5) - spec_insn_lw_rs2_addr = Signal(5) - spec_insn_lw_rd_addr = Signal(5) - spec_insn_lw_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lw_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lw_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lw_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_lw_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_lw_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_lw = insn_lw = rvfi_insn_lw() - m.d.comb += insn_lw.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_lw.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_lw.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_lw.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_lw.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_lw.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_lw_valid.eq(insn_lw.spec_valid) - m.d.comb += spec_insn_lw_trap.eq(insn_lw.spec_trap) - m.d.comb += spec_insn_lw_rs1_addr.eq(insn_lw.spec_rs1_addr) - m.d.comb += spec_insn_lw_rs2_addr.eq(insn_lw.spec_rs2_addr) - m.d.comb += spec_insn_lw_rd_addr.eq(insn_lw.spec_rd_addr) - m.d.comb += spec_insn_lw_rd_wdata.eq(insn_lw.spec_rd_wdata) - m.d.comb += spec_insn_lw_pc_wdata.eq(insn_lw.spec_pc_wdata) - m.d.comb += spec_insn_lw_mem_addr.eq(insn_lw.spec_mem_addr) - m.d.comb += spec_insn_lw_mem_rmask.eq(insn_lw.spec_mem_rmask) - m.d.comb += spec_insn_lw_mem_wmask.eq(insn_lw.spec_mem_wmask) - m.d.comb += spec_insn_lw_mem_wdata.eq(insn_lw.spec_mem_wdata) - - spec_insn_lbu_valid = Signal(1) - spec_insn_lbu_trap = Signal(1) - spec_insn_lbu_rs1_addr = Signal(5) - spec_insn_lbu_rs2_addr = Signal(5) - spec_insn_lbu_rd_addr = Signal(5) - spec_insn_lbu_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lbu_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lbu_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lbu_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_lbu_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_lbu_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_lbu = insn_lbu = rvfi_insn_lbu() - m.d.comb += insn_lbu.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_lbu.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_lbu.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_lbu.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_lbu.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_lbu.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_lbu_valid.eq(insn_lbu.spec_valid) - m.d.comb += spec_insn_lbu_trap.eq(insn_lbu.spec_trap) - m.d.comb += spec_insn_lbu_rs1_addr.eq(insn_lbu.spec_rs1_addr) - m.d.comb += spec_insn_lbu_rs2_addr.eq(insn_lbu.spec_rs2_addr) - m.d.comb += spec_insn_lbu_rd_addr.eq(insn_lbu.spec_rd_addr) - m.d.comb += spec_insn_lbu_rd_wdata.eq(insn_lbu.spec_rd_wdata) - m.d.comb += spec_insn_lbu_pc_wdata.eq(insn_lbu.spec_pc_wdata) - m.d.comb += spec_insn_lbu_mem_addr.eq(insn_lbu.spec_mem_addr) - m.d.comb += spec_insn_lbu_mem_rmask.eq(insn_lbu.spec_mem_rmask) - m.d.comb += spec_insn_lbu_mem_wmask.eq(insn_lbu.spec_mem_wmask) - m.d.comb += spec_insn_lbu_mem_wdata.eq(insn_lbu.spec_mem_wdata) - - spec_insn_lhu_valid = Signal(1) - spec_insn_lhu_trap = Signal(1) - spec_insn_lhu_rs1_addr = Signal(5) - spec_insn_lhu_rs2_addr = Signal(5) - spec_insn_lhu_rd_addr = Signal(5) - spec_insn_lhu_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lhu_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lhu_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lhu_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_lhu_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_lhu_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_lhu = insn_lhu = rvfi_insn_lhu() - m.d.comb += insn_lhu.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_lhu.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_lhu.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_lhu.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_lhu.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_lhu.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_lhu_valid.eq(insn_lhu.spec_valid) - m.d.comb += spec_insn_lhu_trap.eq(insn_lhu.spec_trap) - m.d.comb += spec_insn_lhu_rs1_addr.eq(insn_lhu.spec_rs1_addr) - m.d.comb += spec_insn_lhu_rs2_addr.eq(insn_lhu.spec_rs2_addr) - m.d.comb += spec_insn_lhu_rd_addr.eq(insn_lhu.spec_rd_addr) - m.d.comb += spec_insn_lhu_rd_wdata.eq(insn_lhu.spec_rd_wdata) - m.d.comb += spec_insn_lhu_pc_wdata.eq(insn_lhu.spec_pc_wdata) - m.d.comb += spec_insn_lhu_mem_addr.eq(insn_lhu.spec_mem_addr) - m.d.comb += spec_insn_lhu_mem_rmask.eq(insn_lhu.spec_mem_rmask) - m.d.comb += spec_insn_lhu_mem_wmask.eq(insn_lhu.spec_mem_wmask) - m.d.comb += spec_insn_lhu_mem_wdata.eq(insn_lhu.spec_mem_wdata) - - spec_insn_sb_valid = Signal(1) - spec_insn_sb_trap = Signal(1) - spec_insn_sb_rs1_addr = Signal(5) - spec_insn_sb_rs2_addr = Signal(5) - spec_insn_sb_rd_addr = Signal(5) - spec_insn_sb_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sb_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sb_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sb_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sb_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sb_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_sb = insn_sb = rvfi_insn_sb() - m.d.comb += insn_sb.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_sb.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_sb.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_sb.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_sb.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_sb.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_sb_valid.eq(insn_sb.spec_valid) - m.d.comb += spec_insn_sb_trap.eq(insn_sb.spec_trap) - m.d.comb += spec_insn_sb_rs1_addr.eq(insn_sb.spec_rs1_addr) - m.d.comb += spec_insn_sb_rs2_addr.eq(insn_sb.spec_rs2_addr) - m.d.comb += spec_insn_sb_rd_addr.eq(insn_sb.spec_rd_addr) - m.d.comb += spec_insn_sb_rd_wdata.eq(insn_sb.spec_rd_wdata) - m.d.comb += spec_insn_sb_pc_wdata.eq(insn_sb.spec_pc_wdata) - m.d.comb += spec_insn_sb_mem_addr.eq(insn_sb.spec_mem_addr) - m.d.comb += spec_insn_sb_mem_rmask.eq(insn_sb.spec_mem_rmask) - m.d.comb += spec_insn_sb_mem_wmask.eq(insn_sb.spec_mem_wmask) - m.d.comb += spec_insn_sb_mem_wdata.eq(insn_sb.spec_mem_wdata) - - spec_insn_sh_valid = Signal(1) - spec_insn_sh_trap = Signal(1) - spec_insn_sh_rs1_addr = Signal(5) - spec_insn_sh_rs2_addr = Signal(5) - spec_insn_sh_rd_addr = Signal(5) - spec_insn_sh_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sh_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sh_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sh_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sh_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sh_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_sh = insn_sh = rvfi_insn_sh() - m.d.comb += insn_sh.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_sh.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_sh.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_sh.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_sh.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_sh.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_sh_valid.eq(insn_sh.spec_valid) - m.d.comb += spec_insn_sh_trap.eq(insn_sh.spec_trap) - m.d.comb += spec_insn_sh_rs1_addr.eq(insn_sh.spec_rs1_addr) - m.d.comb += spec_insn_sh_rs2_addr.eq(insn_sh.spec_rs2_addr) - m.d.comb += spec_insn_sh_rd_addr.eq(insn_sh.spec_rd_addr) - m.d.comb += spec_insn_sh_rd_wdata.eq(insn_sh.spec_rd_wdata) - m.d.comb += spec_insn_sh_pc_wdata.eq(insn_sh.spec_pc_wdata) - m.d.comb += spec_insn_sh_mem_addr.eq(insn_sh.spec_mem_addr) - m.d.comb += spec_insn_sh_mem_rmask.eq(insn_sh.spec_mem_rmask) - m.d.comb += spec_insn_sh_mem_wmask.eq(insn_sh.spec_mem_wmask) - m.d.comb += spec_insn_sh_mem_wdata.eq(insn_sh.spec_mem_wdata) - - spec_insn_sw_valid = Signal(1) - spec_insn_sw_trap = Signal(1) - spec_insn_sw_rs1_addr = Signal(5) - spec_insn_sw_rs2_addr = Signal(5) - spec_insn_sw_rd_addr = Signal(5) - spec_insn_sw_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sw_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sw_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sw_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sw_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sw_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_sw = insn_sw = rvfi_insn_sw() - m.d.comb += insn_sw.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_sw.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_sw.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_sw.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_sw.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_sw.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_sw_valid.eq(insn_sw.spec_valid) - m.d.comb += spec_insn_sw_trap.eq(insn_sw.spec_trap) - m.d.comb += spec_insn_sw_rs1_addr.eq(insn_sw.spec_rs1_addr) - m.d.comb += spec_insn_sw_rs2_addr.eq(insn_sw.spec_rs2_addr) - m.d.comb += spec_insn_sw_rd_addr.eq(insn_sw.spec_rd_addr) - m.d.comb += spec_insn_sw_rd_wdata.eq(insn_sw.spec_rd_wdata) - m.d.comb += spec_insn_sw_pc_wdata.eq(insn_sw.spec_pc_wdata) - m.d.comb += spec_insn_sw_mem_addr.eq(insn_sw.spec_mem_addr) - m.d.comb += spec_insn_sw_mem_rmask.eq(insn_sw.spec_mem_rmask) - m.d.comb += spec_insn_sw_mem_wmask.eq(insn_sw.spec_mem_wmask) - m.d.comb += spec_insn_sw_mem_wdata.eq(insn_sw.spec_mem_wdata) - - spec_insn_addi_valid = Signal(1) - spec_insn_addi_trap = Signal(1) - spec_insn_addi_rs1_addr = Signal(5) - spec_insn_addi_rs2_addr = Signal(5) - spec_insn_addi_rd_addr = Signal(5) - spec_insn_addi_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_addi_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_addi_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_addi_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_addi_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_addi_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_addi = insn_addi = rvfi_insn_addi() - m.d.comb += insn_addi.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_addi.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_addi.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_addi.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_addi.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_addi.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_addi_valid.eq(insn_addi.spec_valid) - m.d.comb += spec_insn_addi_trap.eq(insn_addi.spec_trap) - m.d.comb += spec_insn_addi_rs1_addr.eq(insn_addi.spec_rs1_addr) - m.d.comb += spec_insn_addi_rs2_addr.eq(insn_addi.spec_rs2_addr) - m.d.comb += spec_insn_addi_rd_addr.eq(insn_addi.spec_rd_addr) - m.d.comb += spec_insn_addi_rd_wdata.eq(insn_addi.spec_rd_wdata) - m.d.comb += spec_insn_addi_pc_wdata.eq(insn_addi.spec_pc_wdata) - m.d.comb += spec_insn_addi_mem_addr.eq(insn_addi.spec_mem_addr) - m.d.comb += spec_insn_addi_mem_rmask.eq(insn_addi.spec_mem_rmask) - m.d.comb += spec_insn_addi_mem_wmask.eq(insn_addi.spec_mem_wmask) - m.d.comb += spec_insn_addi_mem_wdata.eq(insn_addi.spec_mem_wdata) - - spec_insn_slti_valid = Signal(1) - spec_insn_slti_trap = Signal(1) - spec_insn_slti_rs1_addr = Signal(5) - spec_insn_slti_rs2_addr = Signal(5) - spec_insn_slti_rd_addr = Signal(5) - spec_insn_slti_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_slti_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_slti_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_slti_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_slti_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_slti_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_slti = insn_slti = rvfi_insn_slti() - m.d.comb += insn_slti.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_slti.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_slti.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_slti.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_slti.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_slti.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_slti_valid.eq(insn_slti.spec_valid) - m.d.comb += spec_insn_slti_trap.eq(insn_slti.spec_trap) - m.d.comb += spec_insn_slti_rs1_addr.eq(insn_slti.spec_rs1_addr) - m.d.comb += spec_insn_slti_rs2_addr.eq(insn_slti.spec_rs2_addr) - m.d.comb += spec_insn_slti_rd_addr.eq(insn_slti.spec_rd_addr) - m.d.comb += spec_insn_slti_rd_wdata.eq(insn_slti.spec_rd_wdata) - m.d.comb += spec_insn_slti_pc_wdata.eq(insn_slti.spec_pc_wdata) - m.d.comb += spec_insn_slti_mem_addr.eq(insn_slti.spec_mem_addr) - m.d.comb += spec_insn_slti_mem_rmask.eq(insn_slti.spec_mem_rmask) - m.d.comb += spec_insn_slti_mem_wmask.eq(insn_slti.spec_mem_wmask) - m.d.comb += spec_insn_slti_mem_wdata.eq(insn_slti.spec_mem_wdata) - - spec_insn_sltiu_valid = Signal(1) - spec_insn_sltiu_trap = Signal(1) - spec_insn_sltiu_rs1_addr = Signal(5) - spec_insn_sltiu_rs2_addr = Signal(5) - spec_insn_sltiu_rd_addr = Signal(5) - spec_insn_sltiu_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sltiu_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sltiu_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sltiu_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sltiu_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sltiu_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_sltiu = insn_sltiu = rvfi_insn_sltiu() - m.d.comb += insn_sltiu.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_sltiu.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_sltiu.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_sltiu.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_sltiu.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_sltiu.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_sltiu_valid.eq(insn_sltiu.spec_valid) - m.d.comb += spec_insn_sltiu_trap.eq(insn_sltiu.spec_trap) - m.d.comb += spec_insn_sltiu_rs1_addr.eq(insn_sltiu.spec_rs1_addr) - m.d.comb += spec_insn_sltiu_rs2_addr.eq(insn_sltiu.spec_rs2_addr) - m.d.comb += spec_insn_sltiu_rd_addr.eq(insn_sltiu.spec_rd_addr) - m.d.comb += spec_insn_sltiu_rd_wdata.eq(insn_sltiu.spec_rd_wdata) - m.d.comb += spec_insn_sltiu_pc_wdata.eq(insn_sltiu.spec_pc_wdata) - m.d.comb += spec_insn_sltiu_mem_addr.eq(insn_sltiu.spec_mem_addr) - m.d.comb += spec_insn_sltiu_mem_rmask.eq(insn_sltiu.spec_mem_rmask) - m.d.comb += spec_insn_sltiu_mem_wmask.eq(insn_sltiu.spec_mem_wmask) - m.d.comb += spec_insn_sltiu_mem_wdata.eq(insn_sltiu.spec_mem_wdata) - - spec_insn_xori_valid = Signal(1) - spec_insn_xori_trap = Signal(1) - spec_insn_xori_rs1_addr = Signal(5) - spec_insn_xori_rs2_addr = Signal(5) - spec_insn_xori_rd_addr = Signal(5) - spec_insn_xori_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_xori_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_xori_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_xori_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_xori_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_xori_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_xori = insn_xori = rvfi_insn_xori() - m.d.comb += insn_xori.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_xori.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_xori.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_xori.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_xori.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_xori.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_xori_valid.eq(insn_xori.spec_valid) - m.d.comb += spec_insn_xori_trap.eq(insn_xori.spec_trap) - m.d.comb += spec_insn_xori_rs1_addr.eq(insn_xori.spec_rs1_addr) - m.d.comb += spec_insn_xori_rs2_addr.eq(insn_xori.spec_rs2_addr) - m.d.comb += spec_insn_xori_rd_addr.eq(insn_xori.spec_rd_addr) - m.d.comb += spec_insn_xori_rd_wdata.eq(insn_xori.spec_rd_wdata) - m.d.comb += spec_insn_xori_pc_wdata.eq(insn_xori.spec_pc_wdata) - m.d.comb += spec_insn_xori_mem_addr.eq(insn_xori.spec_mem_addr) - m.d.comb += spec_insn_xori_mem_rmask.eq(insn_xori.spec_mem_rmask) - m.d.comb += spec_insn_xori_mem_wmask.eq(insn_xori.spec_mem_wmask) - m.d.comb += spec_insn_xori_mem_wdata.eq(insn_xori.spec_mem_wdata) - - spec_insn_ori_valid = Signal(1) - spec_insn_ori_trap = Signal(1) - spec_insn_ori_rs1_addr = Signal(5) - spec_insn_ori_rs2_addr = Signal(5) - spec_insn_ori_rd_addr = Signal(5) - spec_insn_ori_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_ori_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_ori_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_ori_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_ori_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_ori_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_ori = insn_ori = rvfi_insn_ori() - m.d.comb += insn_ori.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_ori.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_ori.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_ori.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_ori.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_ori.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_ori_valid.eq(insn_ori.spec_valid) - m.d.comb += spec_insn_ori_trap.eq(insn_ori.spec_trap) - m.d.comb += spec_insn_ori_rs1_addr.eq(insn_ori.spec_rs1_addr) - m.d.comb += spec_insn_ori_rs2_addr.eq(insn_ori.spec_rs2_addr) - m.d.comb += spec_insn_ori_rd_addr.eq(insn_ori.spec_rd_addr) - m.d.comb += spec_insn_ori_rd_wdata.eq(insn_ori.spec_rd_wdata) - m.d.comb += spec_insn_ori_pc_wdata.eq(insn_ori.spec_pc_wdata) - m.d.comb += spec_insn_ori_mem_addr.eq(insn_ori.spec_mem_addr) - m.d.comb += spec_insn_ori_mem_rmask.eq(insn_ori.spec_mem_rmask) - m.d.comb += spec_insn_ori_mem_wmask.eq(insn_ori.spec_mem_wmask) - m.d.comb += spec_insn_ori_mem_wdata.eq(insn_ori.spec_mem_wdata) - - spec_insn_andi_valid = Signal(1) - spec_insn_andi_trap = Signal(1) - spec_insn_andi_rs1_addr = Signal(5) - spec_insn_andi_rs2_addr = Signal(5) - spec_insn_andi_rd_addr = Signal(5) - spec_insn_andi_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_andi_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_andi_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_andi_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_andi_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_andi_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_andi = insn_andi = rvfi_insn_andi() - m.d.comb += insn_andi.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_andi.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_andi.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_andi.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_andi.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_andi.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_andi_valid.eq(insn_andi.spec_valid) - m.d.comb += spec_insn_andi_trap.eq(insn_andi.spec_trap) - m.d.comb += spec_insn_andi_rs1_addr.eq(insn_andi.spec_rs1_addr) - m.d.comb += spec_insn_andi_rs2_addr.eq(insn_andi.spec_rs2_addr) - m.d.comb += spec_insn_andi_rd_addr.eq(insn_andi.spec_rd_addr) - m.d.comb += spec_insn_andi_rd_wdata.eq(insn_andi.spec_rd_wdata) - m.d.comb += spec_insn_andi_pc_wdata.eq(insn_andi.spec_pc_wdata) - m.d.comb += spec_insn_andi_mem_addr.eq(insn_andi.spec_mem_addr) - m.d.comb += spec_insn_andi_mem_rmask.eq(insn_andi.spec_mem_rmask) - m.d.comb += spec_insn_andi_mem_wmask.eq(insn_andi.spec_mem_wmask) - m.d.comb += spec_insn_andi_mem_wdata.eq(insn_andi.spec_mem_wdata) - - spec_insn_slli_valid = Signal(1) - spec_insn_slli_trap = Signal(1) - spec_insn_slli_rs1_addr = Signal(5) - spec_insn_slli_rs2_addr = Signal(5) - spec_insn_slli_rd_addr = Signal(5) - spec_insn_slli_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_slli_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_slli_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_slli_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_slli_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_slli_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_slli = insn_slli = rvfi_insn_slli() - m.d.comb += insn_slli.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_slli.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_slli.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_slli.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_slli.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_slli.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_slli_valid.eq(insn_slli.spec_valid) - m.d.comb += spec_insn_slli_trap.eq(insn_slli.spec_trap) - m.d.comb += spec_insn_slli_rs1_addr.eq(insn_slli.spec_rs1_addr) - m.d.comb += spec_insn_slli_rs2_addr.eq(insn_slli.spec_rs2_addr) - m.d.comb += spec_insn_slli_rd_addr.eq(insn_slli.spec_rd_addr) - m.d.comb += spec_insn_slli_rd_wdata.eq(insn_slli.spec_rd_wdata) - m.d.comb += spec_insn_slli_pc_wdata.eq(insn_slli.spec_pc_wdata) - m.d.comb += spec_insn_slli_mem_addr.eq(insn_slli.spec_mem_addr) - m.d.comb += spec_insn_slli_mem_rmask.eq(insn_slli.spec_mem_rmask) - m.d.comb += spec_insn_slli_mem_wmask.eq(insn_slli.spec_mem_wmask) - m.d.comb += spec_insn_slli_mem_wdata.eq(insn_slli.spec_mem_wdata) - - spec_insn_srli_valid = Signal(1) - spec_insn_srli_trap = Signal(1) - spec_insn_srli_rs1_addr = Signal(5) - spec_insn_srli_rs2_addr = Signal(5) - spec_insn_srli_rd_addr = Signal(5) - spec_insn_srli_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_srli_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_srli_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_srli_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_srli_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_srli_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_srli = insn_srli = rvfi_insn_srli() - m.d.comb += insn_srli.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_srli.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_srli.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_srli.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_srli.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_srli.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_srli_valid.eq(insn_srli.spec_valid) - m.d.comb += spec_insn_srli_trap.eq(insn_srli.spec_trap) - m.d.comb += spec_insn_srli_rs1_addr.eq(insn_srli.spec_rs1_addr) - m.d.comb += spec_insn_srli_rs2_addr.eq(insn_srli.spec_rs2_addr) - m.d.comb += spec_insn_srli_rd_addr.eq(insn_srli.spec_rd_addr) - m.d.comb += spec_insn_srli_rd_wdata.eq(insn_srli.spec_rd_wdata) - m.d.comb += spec_insn_srli_pc_wdata.eq(insn_srli.spec_pc_wdata) - m.d.comb += spec_insn_srli_mem_addr.eq(insn_srli.spec_mem_addr) - m.d.comb += spec_insn_srli_mem_rmask.eq(insn_srli.spec_mem_rmask) - m.d.comb += spec_insn_srli_mem_wmask.eq(insn_srli.spec_mem_wmask) - m.d.comb += spec_insn_srli_mem_wdata.eq(insn_srli.spec_mem_wdata) - - spec_insn_srai_valid = Signal(1) - spec_insn_srai_trap = Signal(1) - spec_insn_srai_rs1_addr = Signal(5) - spec_insn_srai_rs2_addr = Signal(5) - spec_insn_srai_rd_addr = Signal(5) - spec_insn_srai_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_srai_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_srai_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_srai_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_srai_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_srai_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_srai = insn_srai = rvfi_insn_srai() - m.d.comb += insn_srai.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_srai.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_srai.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_srai.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_srai.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_srai.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_srai_valid.eq(insn_srai.spec_valid) - m.d.comb += spec_insn_srai_trap.eq(insn_srai.spec_trap) - m.d.comb += spec_insn_srai_rs1_addr.eq(insn_srai.spec_rs1_addr) - m.d.comb += spec_insn_srai_rs2_addr.eq(insn_srai.spec_rs2_addr) - m.d.comb += spec_insn_srai_rd_addr.eq(insn_srai.spec_rd_addr) - m.d.comb += spec_insn_srai_rd_wdata.eq(insn_srai.spec_rd_wdata) - m.d.comb += spec_insn_srai_pc_wdata.eq(insn_srai.spec_pc_wdata) - m.d.comb += spec_insn_srai_mem_addr.eq(insn_srai.spec_mem_addr) - m.d.comb += spec_insn_srai_mem_rmask.eq(insn_srai.spec_mem_rmask) - m.d.comb += spec_insn_srai_mem_wmask.eq(insn_srai.spec_mem_wmask) - m.d.comb += spec_insn_srai_mem_wdata.eq(insn_srai.spec_mem_wdata) - - spec_insn_add_valid = Signal(1) - spec_insn_add_trap = Signal(1) - spec_insn_add_rs1_addr = Signal(5) - spec_insn_add_rs2_addr = Signal(5) - spec_insn_add_rd_addr = Signal(5) - spec_insn_add_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_add_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_add_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_add_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_add_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_add_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_add = insn_add = rvfi_insn_add() - m.d.comb += insn_add.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_add.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_add.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_add.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_add.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_add.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_add_valid.eq(insn_add.spec_valid) - m.d.comb += spec_insn_add_trap.eq(insn_add.spec_trap) - m.d.comb += spec_insn_add_rs1_addr.eq(insn_add.spec_rs1_addr) - m.d.comb += spec_insn_add_rs2_addr.eq(insn_add.spec_rs2_addr) - m.d.comb += spec_insn_add_rd_addr.eq(insn_add.spec_rd_addr) - m.d.comb += spec_insn_add_rd_wdata.eq(insn_add.spec_rd_wdata) - m.d.comb += spec_insn_add_pc_wdata.eq(insn_add.spec_pc_wdata) - m.d.comb += spec_insn_add_mem_addr.eq(insn_add.spec_mem_addr) - m.d.comb += spec_insn_add_mem_rmask.eq(insn_add.spec_mem_rmask) - m.d.comb += spec_insn_add_mem_wmask.eq(insn_add.spec_mem_wmask) - m.d.comb += spec_insn_add_mem_wdata.eq(insn_add.spec_mem_wdata) - - spec_insn_sub_valid = Signal(1) - spec_insn_sub_trap = Signal(1) - spec_insn_sub_rs1_addr = Signal(5) - spec_insn_sub_rs2_addr = Signal(5) - spec_insn_sub_rd_addr = Signal(5) - spec_insn_sub_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sub_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sub_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sub_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sub_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sub_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_sub = insn_sub = rvfi_insn_sub() - m.d.comb += insn_sub.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_sub.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_sub.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_sub.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_sub.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_sub.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_sub_valid.eq(insn_sub.spec_valid) - m.d.comb += spec_insn_sub_trap.eq(insn_sub.spec_trap) - m.d.comb += spec_insn_sub_rs1_addr.eq(insn_sub.spec_rs1_addr) - m.d.comb += spec_insn_sub_rs2_addr.eq(insn_sub.spec_rs2_addr) - m.d.comb += spec_insn_sub_rd_addr.eq(insn_sub.spec_rd_addr) - m.d.comb += spec_insn_sub_rd_wdata.eq(insn_sub.spec_rd_wdata) - m.d.comb += spec_insn_sub_pc_wdata.eq(insn_sub.spec_pc_wdata) - m.d.comb += spec_insn_sub_mem_addr.eq(insn_sub.spec_mem_addr) - m.d.comb += spec_insn_sub_mem_rmask.eq(insn_sub.spec_mem_rmask) - m.d.comb += spec_insn_sub_mem_wmask.eq(insn_sub.spec_mem_wmask) - m.d.comb += spec_insn_sub_mem_wdata.eq(insn_sub.spec_mem_wdata) - - spec_insn_sll_valid = Signal(1) - spec_insn_sll_trap = Signal(1) - spec_insn_sll_rs1_addr = Signal(5) - spec_insn_sll_rs2_addr = Signal(5) - spec_insn_sll_rd_addr = Signal(5) - spec_insn_sll_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sll_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sll_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sll_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sll_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sll_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_sll = insn_sll = rvfi_insn_sll() - m.d.comb += insn_sll.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_sll.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_sll.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_sll.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_sll.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_sll.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_sll_valid.eq(insn_sll.spec_valid) - m.d.comb += spec_insn_sll_trap.eq(insn_sll.spec_trap) - m.d.comb += spec_insn_sll_rs1_addr.eq(insn_sll.spec_rs1_addr) - m.d.comb += spec_insn_sll_rs2_addr.eq(insn_sll.spec_rs2_addr) - m.d.comb += spec_insn_sll_rd_addr.eq(insn_sll.spec_rd_addr) - m.d.comb += spec_insn_sll_rd_wdata.eq(insn_sll.spec_rd_wdata) - m.d.comb += spec_insn_sll_pc_wdata.eq(insn_sll.spec_pc_wdata) - m.d.comb += spec_insn_sll_mem_addr.eq(insn_sll.spec_mem_addr) - m.d.comb += spec_insn_sll_mem_rmask.eq(insn_sll.spec_mem_rmask) - m.d.comb += spec_insn_sll_mem_wmask.eq(insn_sll.spec_mem_wmask) - m.d.comb += spec_insn_sll_mem_wdata.eq(insn_sll.spec_mem_wdata) - - spec_insn_slt_valid = Signal(1) - spec_insn_slt_trap = Signal(1) - spec_insn_slt_rs1_addr = Signal(5) - spec_insn_slt_rs2_addr = Signal(5) - spec_insn_slt_rd_addr = Signal(5) - spec_insn_slt_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_slt_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_slt_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_slt_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_slt_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_slt_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_slt = insn_slt = rvfi_insn_slt() - m.d.comb += insn_slt.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_slt.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_slt.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_slt.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_slt.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_slt.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_slt_valid.eq(insn_slt.spec_valid) - m.d.comb += spec_insn_slt_trap.eq(insn_slt.spec_trap) - m.d.comb += spec_insn_slt_rs1_addr.eq(insn_slt.spec_rs1_addr) - m.d.comb += spec_insn_slt_rs2_addr.eq(insn_slt.spec_rs2_addr) - m.d.comb += spec_insn_slt_rd_addr.eq(insn_slt.spec_rd_addr) - m.d.comb += spec_insn_slt_rd_wdata.eq(insn_slt.spec_rd_wdata) - m.d.comb += spec_insn_slt_pc_wdata.eq(insn_slt.spec_pc_wdata) - m.d.comb += spec_insn_slt_mem_addr.eq(insn_slt.spec_mem_addr) - m.d.comb += spec_insn_slt_mem_rmask.eq(insn_slt.spec_mem_rmask) - m.d.comb += spec_insn_slt_mem_wmask.eq(insn_slt.spec_mem_wmask) - m.d.comb += spec_insn_slt_mem_wdata.eq(insn_slt.spec_mem_wdata) - - spec_insn_sltu_valid = Signal(1) - spec_insn_sltu_trap = Signal(1) - spec_insn_sltu_rs1_addr = Signal(5) - spec_insn_sltu_rs2_addr = Signal(5) - spec_insn_sltu_rd_addr = Signal(5) - spec_insn_sltu_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sltu_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sltu_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sltu_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sltu_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sltu_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_sltu = insn_sltu = rvfi_insn_sltu() - m.d.comb += insn_sltu.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_sltu.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_sltu.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_sltu.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_sltu.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_sltu.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_sltu_valid.eq(insn_sltu.spec_valid) - m.d.comb += spec_insn_sltu_trap.eq(insn_sltu.spec_trap) - m.d.comb += spec_insn_sltu_rs1_addr.eq(insn_sltu.spec_rs1_addr) - m.d.comb += spec_insn_sltu_rs2_addr.eq(insn_sltu.spec_rs2_addr) - m.d.comb += spec_insn_sltu_rd_addr.eq(insn_sltu.spec_rd_addr) - m.d.comb += spec_insn_sltu_rd_wdata.eq(insn_sltu.spec_rd_wdata) - m.d.comb += spec_insn_sltu_pc_wdata.eq(insn_sltu.spec_pc_wdata) - m.d.comb += spec_insn_sltu_mem_addr.eq(insn_sltu.spec_mem_addr) - m.d.comb += spec_insn_sltu_mem_rmask.eq(insn_sltu.spec_mem_rmask) - m.d.comb += spec_insn_sltu_mem_wmask.eq(insn_sltu.spec_mem_wmask) - m.d.comb += spec_insn_sltu_mem_wdata.eq(insn_sltu.spec_mem_wdata) - - spec_insn_xor_valid = Signal(1) - spec_insn_xor_trap = Signal(1) - spec_insn_xor_rs1_addr = Signal(5) - spec_insn_xor_rs2_addr = Signal(5) - spec_insn_xor_rd_addr = Signal(5) - spec_insn_xor_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_xor_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_xor_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_xor_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_xor_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_xor_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_xor = insn_xor = rvfi_insn_xor() - m.d.comb += insn_xor.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_xor.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_xor.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_xor.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_xor.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_xor.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_xor_valid.eq(insn_xor.spec_valid) - m.d.comb += spec_insn_xor_trap.eq(insn_xor.spec_trap) - m.d.comb += spec_insn_xor_rs1_addr.eq(insn_xor.spec_rs1_addr) - m.d.comb += spec_insn_xor_rs2_addr.eq(insn_xor.spec_rs2_addr) - m.d.comb += spec_insn_xor_rd_addr.eq(insn_xor.spec_rd_addr) - m.d.comb += spec_insn_xor_rd_wdata.eq(insn_xor.spec_rd_wdata) - m.d.comb += spec_insn_xor_pc_wdata.eq(insn_xor.spec_pc_wdata) - m.d.comb += spec_insn_xor_mem_addr.eq(insn_xor.spec_mem_addr) - m.d.comb += spec_insn_xor_mem_rmask.eq(insn_xor.spec_mem_rmask) - m.d.comb += spec_insn_xor_mem_wmask.eq(insn_xor.spec_mem_wmask) - m.d.comb += spec_insn_xor_mem_wdata.eq(insn_xor.spec_mem_wdata) - - spec_insn_srl_valid = Signal(1) - spec_insn_srl_trap = Signal(1) - spec_insn_srl_rs1_addr = Signal(5) - spec_insn_srl_rs2_addr = Signal(5) - spec_insn_srl_rd_addr = Signal(5) - spec_insn_srl_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_srl_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_srl_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_srl_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_srl_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_srl_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_srl = insn_srl = rvfi_insn_srl() - m.d.comb += insn_srl.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_srl.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_srl.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_srl.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_srl.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_srl.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_srl_valid.eq(insn_srl.spec_valid) - m.d.comb += spec_insn_srl_trap.eq(insn_srl.spec_trap) - m.d.comb += spec_insn_srl_rs1_addr.eq(insn_srl.spec_rs1_addr) - m.d.comb += spec_insn_srl_rs2_addr.eq(insn_srl.spec_rs2_addr) - m.d.comb += spec_insn_srl_rd_addr.eq(insn_srl.spec_rd_addr) - m.d.comb += spec_insn_srl_rd_wdata.eq(insn_srl.spec_rd_wdata) - m.d.comb += spec_insn_srl_pc_wdata.eq(insn_srl.spec_pc_wdata) - m.d.comb += spec_insn_srl_mem_addr.eq(insn_srl.spec_mem_addr) - m.d.comb += spec_insn_srl_mem_rmask.eq(insn_srl.spec_mem_rmask) - m.d.comb += spec_insn_srl_mem_wmask.eq(insn_srl.spec_mem_wmask) - m.d.comb += spec_insn_srl_mem_wdata.eq(insn_srl.spec_mem_wdata) - - spec_insn_sra_valid = Signal(1) - spec_insn_sra_trap = Signal(1) - spec_insn_sra_rs1_addr = Signal(5) - spec_insn_sra_rs2_addr = Signal(5) - spec_insn_sra_rd_addr = Signal(5) - spec_insn_sra_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sra_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sra_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sra_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sra_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sra_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_sra = insn_sra = rvfi_insn_sra() - m.d.comb += insn_sra.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_sra.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_sra.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_sra.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_sra.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_sra.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_sra_valid.eq(insn_sra.spec_valid) - m.d.comb += spec_insn_sra_trap.eq(insn_sra.spec_trap) - m.d.comb += spec_insn_sra_rs1_addr.eq(insn_sra.spec_rs1_addr) - m.d.comb += spec_insn_sra_rs2_addr.eq(insn_sra.spec_rs2_addr) - m.d.comb += spec_insn_sra_rd_addr.eq(insn_sra.spec_rd_addr) - m.d.comb += spec_insn_sra_rd_wdata.eq(insn_sra.spec_rd_wdata) - m.d.comb += spec_insn_sra_pc_wdata.eq(insn_sra.spec_pc_wdata) - m.d.comb += spec_insn_sra_mem_addr.eq(insn_sra.spec_mem_addr) - m.d.comb += spec_insn_sra_mem_rmask.eq(insn_sra.spec_mem_rmask) - m.d.comb += spec_insn_sra_mem_wmask.eq(insn_sra.spec_mem_wmask) - m.d.comb += spec_insn_sra_mem_wdata.eq(insn_sra.spec_mem_wdata) - - spec_insn_or_valid = Signal(1) - spec_insn_or_trap = Signal(1) - spec_insn_or_rs1_addr = Signal(5) - spec_insn_or_rs2_addr = Signal(5) - spec_insn_or_rd_addr = Signal(5) - spec_insn_or_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_or_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_or_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_or_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_or_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_or_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_or = insn_or = rvfi_insn_or() - m.d.comb += insn_or.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_or.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_or.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_or.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_or.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_or.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_or_valid.eq(insn_or.spec_valid) - m.d.comb += spec_insn_or_trap.eq(insn_or.spec_trap) - m.d.comb += spec_insn_or_rs1_addr.eq(insn_or.spec_rs1_addr) - m.d.comb += spec_insn_or_rs2_addr.eq(insn_or.spec_rs2_addr) - m.d.comb += spec_insn_or_rd_addr.eq(insn_or.spec_rd_addr) - m.d.comb += spec_insn_or_rd_wdata.eq(insn_or.spec_rd_wdata) - m.d.comb += spec_insn_or_pc_wdata.eq(insn_or.spec_pc_wdata) - m.d.comb += spec_insn_or_mem_addr.eq(insn_or.spec_mem_addr) - m.d.comb += spec_insn_or_mem_rmask.eq(insn_or.spec_mem_rmask) - m.d.comb += spec_insn_or_mem_wmask.eq(insn_or.spec_mem_wmask) - m.d.comb += spec_insn_or_mem_wdata.eq(insn_or.spec_mem_wdata) - - spec_insn_and_valid = Signal(1) - spec_insn_and_trap = Signal(1) - spec_insn_and_rs1_addr = Signal(5) - spec_insn_and_rs2_addr = Signal(5) - spec_insn_and_rd_addr = Signal(5) - spec_insn_and_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_and_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_and_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_and_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_and_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_and_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_and = insn_and = rvfi_insn_and() - m.d.comb += insn_and.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_and.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_and.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_and.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_and.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_and.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_and_valid.eq(insn_and.spec_valid) - m.d.comb += spec_insn_and_trap.eq(insn_and.spec_trap) - m.d.comb += spec_insn_and_rs1_addr.eq(insn_and.spec_rs1_addr) - m.d.comb += spec_insn_and_rs2_addr.eq(insn_and.spec_rs2_addr) - m.d.comb += spec_insn_and_rd_addr.eq(insn_and.spec_rd_addr) - m.d.comb += spec_insn_and_rd_wdata.eq(insn_and.spec_rd_wdata) - m.d.comb += spec_insn_and_pc_wdata.eq(insn_and.spec_pc_wdata) - m.d.comb += spec_insn_and_mem_addr.eq(insn_and.spec_mem_addr) - m.d.comb += spec_insn_and_mem_rmask.eq(insn_and.spec_mem_rmask) - m.d.comb += spec_insn_and_mem_wmask.eq(insn_and.spec_mem_wmask) - m.d.comb += spec_insn_and_mem_wdata.eq(insn_and.spec_mem_wdata) - - spec_insn_mul_valid = Signal(1) - spec_insn_mul_trap = Signal(1) - spec_insn_mul_rs1_addr = Signal(5) - spec_insn_mul_rs2_addr = Signal(5) - spec_insn_mul_rd_addr = Signal(5) - spec_insn_mul_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_mul_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_mul_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_mul_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_mul_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_mul_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_mul = insn_mul = rvfi_insn_mul() - m.d.comb += insn_mul.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_mul.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_mul.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_mul.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_mul.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_mul.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_mul_valid.eq(insn_mul.spec_valid) - m.d.comb += spec_insn_mul_trap.eq(insn_mul.spec_trap) - m.d.comb += spec_insn_mul_rs1_addr.eq(insn_mul.spec_rs1_addr) - m.d.comb += spec_insn_mul_rs2_addr.eq(insn_mul.spec_rs2_addr) - m.d.comb += spec_insn_mul_rd_addr.eq(insn_mul.spec_rd_addr) - m.d.comb += spec_insn_mul_rd_wdata.eq(insn_mul.spec_rd_wdata) - m.d.comb += spec_insn_mul_pc_wdata.eq(insn_mul.spec_pc_wdata) - m.d.comb += spec_insn_mul_mem_addr.eq(insn_mul.spec_mem_addr) - m.d.comb += spec_insn_mul_mem_rmask.eq(insn_mul.spec_mem_rmask) - m.d.comb += spec_insn_mul_mem_wmask.eq(insn_mul.spec_mem_wmask) - m.d.comb += spec_insn_mul_mem_wdata.eq(insn_mul.spec_mem_wdata) - - spec_insn_mulh_valid = Signal(1) - spec_insn_mulh_trap = Signal(1) - spec_insn_mulh_rs1_addr = Signal(5) - spec_insn_mulh_rs2_addr = Signal(5) - spec_insn_mulh_rd_addr = Signal(5) - spec_insn_mulh_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_mulh_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_mulh_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_mulh_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_mulh_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_mulh_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_mulh = insn_mulh = rvfi_insn_mulh() - m.d.comb += insn_mulh.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_mulh.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_mulh.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_mulh.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_mulh.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_mulh.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_mulh_valid.eq(insn_mulh.spec_valid) - m.d.comb += spec_insn_mulh_trap.eq(insn_mulh.spec_trap) - m.d.comb += spec_insn_mulh_rs1_addr.eq(insn_mulh.spec_rs1_addr) - m.d.comb += spec_insn_mulh_rs2_addr.eq(insn_mulh.spec_rs2_addr) - m.d.comb += spec_insn_mulh_rd_addr.eq(insn_mulh.spec_rd_addr) - m.d.comb += spec_insn_mulh_rd_wdata.eq(insn_mulh.spec_rd_wdata) - m.d.comb += spec_insn_mulh_pc_wdata.eq(insn_mulh.spec_pc_wdata) - m.d.comb += spec_insn_mulh_mem_addr.eq(insn_mulh.spec_mem_addr) - m.d.comb += spec_insn_mulh_mem_rmask.eq(insn_mulh.spec_mem_rmask) - m.d.comb += spec_insn_mulh_mem_wmask.eq(insn_mulh.spec_mem_wmask) - m.d.comb += spec_insn_mulh_mem_wdata.eq(insn_mulh.spec_mem_wdata) - - spec_insn_mulhsu_valid = Signal(1) - spec_insn_mulhsu_trap = Signal(1) - spec_insn_mulhsu_rs1_addr = Signal(5) - spec_insn_mulhsu_rs2_addr = Signal(5) - spec_insn_mulhsu_rd_addr = Signal(5) - spec_insn_mulhsu_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_mulhsu_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_mulhsu_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_mulhsu_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_mulhsu_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_mulhsu_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_mulhsu = insn_mulhsu = rvfi_insn_mulhsu() - m.d.comb += insn_mulhsu.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_mulhsu.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_mulhsu.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_mulhsu.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_mulhsu.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_mulhsu.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_mulhsu_valid.eq(insn_mulhsu.spec_valid) - m.d.comb += spec_insn_mulhsu_trap.eq(insn_mulhsu.spec_trap) - m.d.comb += spec_insn_mulhsu_rs1_addr.eq(insn_mulhsu.spec_rs1_addr) - m.d.comb += spec_insn_mulhsu_rs2_addr.eq(insn_mulhsu.spec_rs2_addr) - m.d.comb += spec_insn_mulhsu_rd_addr.eq(insn_mulhsu.spec_rd_addr) - m.d.comb += spec_insn_mulhsu_rd_wdata.eq(insn_mulhsu.spec_rd_wdata) - m.d.comb += spec_insn_mulhsu_pc_wdata.eq(insn_mulhsu.spec_pc_wdata) - m.d.comb += spec_insn_mulhsu_mem_addr.eq(insn_mulhsu.spec_mem_addr) - m.d.comb += spec_insn_mulhsu_mem_rmask.eq(insn_mulhsu.spec_mem_rmask) - m.d.comb += spec_insn_mulhsu_mem_wmask.eq(insn_mulhsu.spec_mem_wmask) - m.d.comb += spec_insn_mulhsu_mem_wdata.eq(insn_mulhsu.spec_mem_wdata) - - spec_insn_mulhu_valid = Signal(1) - spec_insn_mulhu_trap = Signal(1) - spec_insn_mulhu_rs1_addr = Signal(5) - spec_insn_mulhu_rs2_addr = Signal(5) - spec_insn_mulhu_rd_addr = Signal(5) - spec_insn_mulhu_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_mulhu_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_mulhu_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_mulhu_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_mulhu_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_mulhu_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_mulhu = insn_mulhu = rvfi_insn_mulhu() - m.d.comb += insn_mulhu.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_mulhu.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_mulhu.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_mulhu.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_mulhu.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_mulhu.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_mulhu_valid.eq(insn_mulhu.spec_valid) - m.d.comb += spec_insn_mulhu_trap.eq(insn_mulhu.spec_trap) - m.d.comb += spec_insn_mulhu_rs1_addr.eq(insn_mulhu.spec_rs1_addr) - m.d.comb += spec_insn_mulhu_rs2_addr.eq(insn_mulhu.spec_rs2_addr) - m.d.comb += spec_insn_mulhu_rd_addr.eq(insn_mulhu.spec_rd_addr) - m.d.comb += spec_insn_mulhu_rd_wdata.eq(insn_mulhu.spec_rd_wdata) - m.d.comb += spec_insn_mulhu_pc_wdata.eq(insn_mulhu.spec_pc_wdata) - m.d.comb += spec_insn_mulhu_mem_addr.eq(insn_mulhu.spec_mem_addr) - m.d.comb += spec_insn_mulhu_mem_rmask.eq(insn_mulhu.spec_mem_rmask) - m.d.comb += spec_insn_mulhu_mem_wmask.eq(insn_mulhu.spec_mem_wmask) - m.d.comb += spec_insn_mulhu_mem_wdata.eq(insn_mulhu.spec_mem_wdata) - - spec_insn_div_valid = Signal(1) - spec_insn_div_trap = Signal(1) - spec_insn_div_rs1_addr = Signal(5) - spec_insn_div_rs2_addr = Signal(5) - spec_insn_div_rd_addr = Signal(5) - spec_insn_div_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_div_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_div_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_div_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_div_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_div_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_div = insn_div = rvfi_insn_div() - m.d.comb += insn_div.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_div.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_div.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_div.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_div.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_div.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_div_valid.eq(insn_div.spec_valid) - m.d.comb += spec_insn_div_trap.eq(insn_div.spec_trap) - m.d.comb += spec_insn_div_rs1_addr.eq(insn_div.spec_rs1_addr) - m.d.comb += spec_insn_div_rs2_addr.eq(insn_div.spec_rs2_addr) - m.d.comb += spec_insn_div_rd_addr.eq(insn_div.spec_rd_addr) - m.d.comb += spec_insn_div_rd_wdata.eq(insn_div.spec_rd_wdata) - m.d.comb += spec_insn_div_pc_wdata.eq(insn_div.spec_pc_wdata) - m.d.comb += spec_insn_div_mem_addr.eq(insn_div.spec_mem_addr) - m.d.comb += spec_insn_div_mem_rmask.eq(insn_div.spec_mem_rmask) - m.d.comb += spec_insn_div_mem_wmask.eq(insn_div.spec_mem_wmask) - m.d.comb += spec_insn_div_mem_wdata.eq(insn_div.spec_mem_wdata) - - spec_insn_divu_valid = Signal(1) - spec_insn_divu_trap = Signal(1) - spec_insn_divu_rs1_addr = Signal(5) - spec_insn_divu_rs2_addr = Signal(5) - spec_insn_divu_rd_addr = Signal(5) - spec_insn_divu_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_divu_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_divu_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_divu_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_divu_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_divu_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_divu = insn_divu = rvfi_insn_divu() - m.d.comb += insn_divu.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_divu.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_divu.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_divu.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_divu.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_divu.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_divu_valid.eq(insn_divu.spec_valid) - m.d.comb += spec_insn_divu_trap.eq(insn_divu.spec_trap) - m.d.comb += spec_insn_divu_rs1_addr.eq(insn_divu.spec_rs1_addr) - m.d.comb += spec_insn_divu_rs2_addr.eq(insn_divu.spec_rs2_addr) - m.d.comb += spec_insn_divu_rd_addr.eq(insn_divu.spec_rd_addr) - m.d.comb += spec_insn_divu_rd_wdata.eq(insn_divu.spec_rd_wdata) - m.d.comb += spec_insn_divu_pc_wdata.eq(insn_divu.spec_pc_wdata) - m.d.comb += spec_insn_divu_mem_addr.eq(insn_divu.spec_mem_addr) - m.d.comb += spec_insn_divu_mem_rmask.eq(insn_divu.spec_mem_rmask) - m.d.comb += spec_insn_divu_mem_wmask.eq(insn_divu.spec_mem_wmask) - m.d.comb += spec_insn_divu_mem_wdata.eq(insn_divu.spec_mem_wdata) - - spec_insn_rem_valid = Signal(1) - spec_insn_rem_trap = Signal(1) - spec_insn_rem_rs1_addr = Signal(5) - spec_insn_rem_rs2_addr = Signal(5) - spec_insn_rem_rd_addr = Signal(5) - spec_insn_rem_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_rem_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_rem_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_rem_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_rem_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_rem_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_rem = insn_rem = rvfi_insn_rem() - m.d.comb += insn_rem.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_rem.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_rem.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_rem.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_rem.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_rem.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_rem_valid.eq(insn_rem.spec_valid) - m.d.comb += spec_insn_rem_trap.eq(insn_rem.spec_trap) - m.d.comb += spec_insn_rem_rs1_addr.eq(insn_rem.spec_rs1_addr) - m.d.comb += spec_insn_rem_rs2_addr.eq(insn_rem.spec_rs2_addr) - m.d.comb += spec_insn_rem_rd_addr.eq(insn_rem.spec_rd_addr) - m.d.comb += spec_insn_rem_rd_wdata.eq(insn_rem.spec_rd_wdata) - m.d.comb += spec_insn_rem_pc_wdata.eq(insn_rem.spec_pc_wdata) - m.d.comb += spec_insn_rem_mem_addr.eq(insn_rem.spec_mem_addr) - m.d.comb += spec_insn_rem_mem_rmask.eq(insn_rem.spec_mem_rmask) - m.d.comb += spec_insn_rem_mem_wmask.eq(insn_rem.spec_mem_wmask) - m.d.comb += spec_insn_rem_mem_wdata.eq(insn_rem.spec_mem_wdata) - - spec_insn_remu_valid = Signal(1) - spec_insn_remu_trap = Signal(1) - spec_insn_remu_rs1_addr = Signal(5) - spec_insn_remu_rs2_addr = Signal(5) - spec_insn_remu_rd_addr = Signal(5) - spec_insn_remu_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_remu_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_remu_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_remu_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_remu_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_remu_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_remu = insn_remu = rvfi_insn_remu() - m.d.comb += insn_remu.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_remu.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_remu.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_remu.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_remu.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_remu.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_remu_valid.eq(insn_remu.spec_valid) - m.d.comb += spec_insn_remu_trap.eq(insn_remu.spec_trap) - m.d.comb += spec_insn_remu_rs1_addr.eq(insn_remu.spec_rs1_addr) - m.d.comb += spec_insn_remu_rs2_addr.eq(insn_remu.spec_rs2_addr) - m.d.comb += spec_insn_remu_rd_addr.eq(insn_remu.spec_rd_addr) - m.d.comb += spec_insn_remu_rd_wdata.eq(insn_remu.spec_rd_wdata) - m.d.comb += spec_insn_remu_pc_wdata.eq(insn_remu.spec_pc_wdata) - m.d.comb += spec_insn_remu_mem_addr.eq(insn_remu.spec_mem_addr) - m.d.comb += spec_insn_remu_mem_rmask.eq(insn_remu.spec_mem_rmask) - m.d.comb += spec_insn_remu_mem_wmask.eq(insn_remu.spec_mem_wmask) - m.d.comb += spec_insn_remu_mem_wdata.eq(insn_remu.spec_mem_wdata) - - m.d.comb += self.spec_valid.eq(Mux(spec_insn_remu_valid, spec_insn_remu_valid, Mux(spec_insn_rem_valid, spec_insn_rem_valid, Mux(spec_insn_divu_valid, spec_insn_divu_valid, Mux(spec_insn_div_valid, spec_insn_div_valid, Mux(spec_insn_mulhu_valid, spec_insn_mulhu_valid, Mux(spec_insn_mulhsu_valid, spec_insn_mulhsu_valid, Mux(spec_insn_mulh_valid, spec_insn_mulh_valid, Mux(spec_insn_mul_valid, spec_insn_mul_valid, Mux(spec_insn_and_valid, spec_insn_and_valid, Mux(spec_insn_or_valid, spec_insn_or_valid, Mux(spec_insn_sra_valid, spec_insn_sra_valid, Mux(spec_insn_srl_valid, spec_insn_srl_valid, Mux(spec_insn_xor_valid, spec_insn_xor_valid, Mux(spec_insn_sltu_valid, spec_insn_sltu_valid, Mux(spec_insn_slt_valid, spec_insn_slt_valid, Mux(spec_insn_sll_valid, spec_insn_sll_valid, Mux(spec_insn_sub_valid, spec_insn_sub_valid, Mux(spec_insn_add_valid, spec_insn_add_valid, Mux(spec_insn_srai_valid, spec_insn_srai_valid, Mux(spec_insn_srli_valid, spec_insn_srli_valid, Mux(spec_insn_slli_valid, spec_insn_slli_valid, Mux(spec_insn_andi_valid, spec_insn_andi_valid, Mux(spec_insn_ori_valid, spec_insn_ori_valid, Mux(spec_insn_xori_valid, spec_insn_xori_valid, Mux(spec_insn_sltiu_valid, spec_insn_sltiu_valid, Mux(spec_insn_slti_valid, spec_insn_slti_valid, Mux(spec_insn_addi_valid, spec_insn_addi_valid, Mux(spec_insn_sw_valid, spec_insn_sw_valid, Mux(spec_insn_sh_valid, spec_insn_sh_valid, Mux(spec_insn_sb_valid, spec_insn_sb_valid, Mux(spec_insn_lhu_valid, spec_insn_lhu_valid, Mux(spec_insn_lbu_valid, spec_insn_lbu_valid, Mux(spec_insn_lw_valid, spec_insn_lw_valid, Mux(spec_insn_lh_valid, spec_insn_lh_valid, Mux(spec_insn_lb_valid, spec_insn_lb_valid, Mux(spec_insn_bgeu_valid, spec_insn_bgeu_valid, Mux(spec_insn_bltu_valid, spec_insn_bltu_valid, Mux(spec_insn_bge_valid, spec_insn_bge_valid, Mux(spec_insn_blt_valid, spec_insn_blt_valid, Mux(spec_insn_bne_valid, spec_insn_bne_valid, Mux(spec_insn_beq_valid, spec_insn_beq_valid, Mux(spec_insn_jalr_valid, spec_insn_jalr_valid, Mux(spec_insn_jal_valid, spec_insn_jal_valid, Mux(spec_insn_auipc_valid, spec_insn_auipc_valid, Mux(spec_insn_lui_valid, spec_insn_lui_valid, 0)))))))))))))))))))))))))))))))))))))))))))))) - m.d.comb += self.spec_trap.eq(Mux(spec_insn_remu_valid, spec_insn_remu_trap, Mux(spec_insn_rem_valid, spec_insn_rem_trap, Mux(spec_insn_divu_valid, spec_insn_divu_trap, Mux(spec_insn_div_valid, spec_insn_div_trap, Mux(spec_insn_mulhu_valid, spec_insn_mulhu_trap, Mux(spec_insn_mulhsu_valid, spec_insn_mulhsu_trap, Mux(spec_insn_mulh_valid, spec_insn_mulh_trap, Mux(spec_insn_mul_valid, spec_insn_mul_trap, Mux(spec_insn_and_valid, spec_insn_and_trap, Mux(spec_insn_or_valid, spec_insn_or_trap, Mux(spec_insn_sra_valid, spec_insn_sra_trap, Mux(spec_insn_srl_valid, spec_insn_srl_trap, Mux(spec_insn_xor_valid, spec_insn_xor_trap, Mux(spec_insn_sltu_valid, spec_insn_sltu_trap, Mux(spec_insn_slt_valid, spec_insn_slt_trap, Mux(spec_insn_sll_valid, spec_insn_sll_trap, Mux(spec_insn_sub_valid, spec_insn_sub_trap, Mux(spec_insn_add_valid, spec_insn_add_trap, Mux(spec_insn_srai_valid, spec_insn_srai_trap, Mux(spec_insn_srli_valid, spec_insn_srli_trap, Mux(spec_insn_slli_valid, spec_insn_slli_trap, Mux(spec_insn_andi_valid, spec_insn_andi_trap, Mux(spec_insn_ori_valid, spec_insn_ori_trap, Mux(spec_insn_xori_valid, spec_insn_xori_trap, Mux(spec_insn_sltiu_valid, spec_insn_sltiu_trap, Mux(spec_insn_slti_valid, spec_insn_slti_trap, Mux(spec_insn_addi_valid, spec_insn_addi_trap, Mux(spec_insn_sw_valid, spec_insn_sw_trap, Mux(spec_insn_sh_valid, spec_insn_sh_trap, Mux(spec_insn_sb_valid, spec_insn_sb_trap, Mux(spec_insn_lhu_valid, spec_insn_lhu_trap, Mux(spec_insn_lbu_valid, spec_insn_lbu_trap, Mux(spec_insn_lw_valid, spec_insn_lw_trap, Mux(spec_insn_lh_valid, spec_insn_lh_trap, Mux(spec_insn_lb_valid, spec_insn_lb_trap, Mux(spec_insn_bgeu_valid, spec_insn_bgeu_trap, Mux(spec_insn_bltu_valid, spec_insn_bltu_trap, Mux(spec_insn_bge_valid, spec_insn_bge_trap, Mux(spec_insn_blt_valid, spec_insn_blt_trap, Mux(spec_insn_bne_valid, spec_insn_bne_trap, Mux(spec_insn_beq_valid, spec_insn_beq_trap, Mux(spec_insn_jalr_valid, spec_insn_jalr_trap, Mux(spec_insn_jal_valid, spec_insn_jal_trap, Mux(spec_insn_auipc_valid, spec_insn_auipc_trap, Mux(spec_insn_lui_valid, spec_insn_lui_trap, 0)))))))))))))))))))))))))))))))))))))))))))))) - m.d.comb += self.spec_rs1_addr.eq(Mux(spec_insn_remu_valid, spec_insn_remu_rs1_addr, Mux(spec_insn_rem_valid, spec_insn_rem_rs1_addr, Mux(spec_insn_divu_valid, spec_insn_divu_rs1_addr, Mux(spec_insn_div_valid, spec_insn_div_rs1_addr, Mux(spec_insn_mulhu_valid, spec_insn_mulhu_rs1_addr, Mux(spec_insn_mulhsu_valid, spec_insn_mulhsu_rs1_addr, Mux(spec_insn_mulh_valid, spec_insn_mulh_rs1_addr, Mux(spec_insn_mul_valid, spec_insn_mul_rs1_addr, Mux(spec_insn_and_valid, spec_insn_and_rs1_addr, Mux(spec_insn_or_valid, spec_insn_or_rs1_addr, Mux(spec_insn_sra_valid, spec_insn_sra_rs1_addr, Mux(spec_insn_srl_valid, spec_insn_srl_rs1_addr, Mux(spec_insn_xor_valid, spec_insn_xor_rs1_addr, Mux(spec_insn_sltu_valid, spec_insn_sltu_rs1_addr, Mux(spec_insn_slt_valid, spec_insn_slt_rs1_addr, Mux(spec_insn_sll_valid, spec_insn_sll_rs1_addr, Mux(spec_insn_sub_valid, spec_insn_sub_rs1_addr, Mux(spec_insn_add_valid, spec_insn_add_rs1_addr, Mux(spec_insn_srai_valid, spec_insn_srai_rs1_addr, Mux(spec_insn_srli_valid, spec_insn_srli_rs1_addr, Mux(spec_insn_slli_valid, spec_insn_slli_rs1_addr, Mux(spec_insn_andi_valid, spec_insn_andi_rs1_addr, Mux(spec_insn_ori_valid, spec_insn_ori_rs1_addr, Mux(spec_insn_xori_valid, spec_insn_xori_rs1_addr, Mux(spec_insn_sltiu_valid, spec_insn_sltiu_rs1_addr, Mux(spec_insn_slti_valid, spec_insn_slti_rs1_addr, Mux(spec_insn_addi_valid, spec_insn_addi_rs1_addr, Mux(spec_insn_sw_valid, spec_insn_sw_rs1_addr, Mux(spec_insn_sh_valid, spec_insn_sh_rs1_addr, Mux(spec_insn_sb_valid, spec_insn_sb_rs1_addr, Mux(spec_insn_lhu_valid, spec_insn_lhu_rs1_addr, Mux(spec_insn_lbu_valid, spec_insn_lbu_rs1_addr, Mux(spec_insn_lw_valid, spec_insn_lw_rs1_addr, Mux(spec_insn_lh_valid, spec_insn_lh_rs1_addr, Mux(spec_insn_lb_valid, spec_insn_lb_rs1_addr, Mux(spec_insn_bgeu_valid, spec_insn_bgeu_rs1_addr, Mux(spec_insn_bltu_valid, spec_insn_bltu_rs1_addr, Mux(spec_insn_bge_valid, spec_insn_bge_rs1_addr, Mux(spec_insn_blt_valid, spec_insn_blt_rs1_addr, Mux(spec_insn_bne_valid, spec_insn_bne_rs1_addr, Mux(spec_insn_beq_valid, spec_insn_beq_rs1_addr, Mux(spec_insn_jalr_valid, spec_insn_jalr_rs1_addr, Mux(spec_insn_jal_valid, spec_insn_jal_rs1_addr, Mux(spec_insn_auipc_valid, spec_insn_auipc_rs1_addr, Mux(spec_insn_lui_valid, spec_insn_lui_rs1_addr, 0)))))))))))))))))))))))))))))))))))))))))))))) - m.d.comb += self.spec_rs2_addr.eq(Mux(spec_insn_remu_valid, spec_insn_remu_rs2_addr, Mux(spec_insn_rem_valid, spec_insn_rem_rs2_addr, Mux(spec_insn_divu_valid, spec_insn_divu_rs2_addr, Mux(spec_insn_div_valid, spec_insn_div_rs2_addr, Mux(spec_insn_mulhu_valid, spec_insn_mulhu_rs2_addr, Mux(spec_insn_mulhsu_valid, spec_insn_mulhsu_rs2_addr, Mux(spec_insn_mulh_valid, spec_insn_mulh_rs2_addr, Mux(spec_insn_mul_valid, spec_insn_mul_rs2_addr, Mux(spec_insn_and_valid, spec_insn_and_rs2_addr, Mux(spec_insn_or_valid, spec_insn_or_rs2_addr, Mux(spec_insn_sra_valid, spec_insn_sra_rs2_addr, Mux(spec_insn_srl_valid, spec_insn_srl_rs2_addr, Mux(spec_insn_xor_valid, spec_insn_xor_rs2_addr, Mux(spec_insn_sltu_valid, spec_insn_sltu_rs2_addr, Mux(spec_insn_slt_valid, spec_insn_slt_rs2_addr, Mux(spec_insn_sll_valid, spec_insn_sll_rs2_addr, Mux(spec_insn_sub_valid, spec_insn_sub_rs2_addr, Mux(spec_insn_add_valid, spec_insn_add_rs2_addr, Mux(spec_insn_srai_valid, spec_insn_srai_rs2_addr, Mux(spec_insn_srli_valid, spec_insn_srli_rs2_addr, Mux(spec_insn_slli_valid, spec_insn_slli_rs2_addr, Mux(spec_insn_andi_valid, spec_insn_andi_rs2_addr, Mux(spec_insn_ori_valid, spec_insn_ori_rs2_addr, Mux(spec_insn_xori_valid, spec_insn_xori_rs2_addr, Mux(spec_insn_sltiu_valid, spec_insn_sltiu_rs2_addr, Mux(spec_insn_slti_valid, spec_insn_slti_rs2_addr, Mux(spec_insn_addi_valid, spec_insn_addi_rs2_addr, Mux(spec_insn_sw_valid, spec_insn_sw_rs2_addr, Mux(spec_insn_sh_valid, spec_insn_sh_rs2_addr, Mux(spec_insn_sb_valid, spec_insn_sb_rs2_addr, Mux(spec_insn_lhu_valid, spec_insn_lhu_rs2_addr, Mux(spec_insn_lbu_valid, spec_insn_lbu_rs2_addr, Mux(spec_insn_lw_valid, spec_insn_lw_rs2_addr, Mux(spec_insn_lh_valid, spec_insn_lh_rs2_addr, Mux(spec_insn_lb_valid, spec_insn_lb_rs2_addr, Mux(spec_insn_bgeu_valid, spec_insn_bgeu_rs2_addr, Mux(spec_insn_bltu_valid, spec_insn_bltu_rs2_addr, Mux(spec_insn_bge_valid, spec_insn_bge_rs2_addr, Mux(spec_insn_blt_valid, spec_insn_blt_rs2_addr, Mux(spec_insn_bne_valid, spec_insn_bne_rs2_addr, Mux(spec_insn_beq_valid, spec_insn_beq_rs2_addr, Mux(spec_insn_jalr_valid, spec_insn_jalr_rs2_addr, Mux(spec_insn_jal_valid, spec_insn_jal_rs2_addr, Mux(spec_insn_auipc_valid, spec_insn_auipc_rs2_addr, Mux(spec_insn_lui_valid, spec_insn_lui_rs2_addr, 0)))))))))))))))))))))))))))))))))))))))))))))) - m.d.comb += self.spec_rd_addr.eq(Mux(spec_insn_remu_valid, spec_insn_remu_rd_addr, Mux(spec_insn_rem_valid, spec_insn_rem_rd_addr, Mux(spec_insn_divu_valid, spec_insn_divu_rd_addr, Mux(spec_insn_div_valid, spec_insn_div_rd_addr, Mux(spec_insn_mulhu_valid, spec_insn_mulhu_rd_addr, Mux(spec_insn_mulhsu_valid, spec_insn_mulhsu_rd_addr, Mux(spec_insn_mulh_valid, spec_insn_mulh_rd_addr, Mux(spec_insn_mul_valid, spec_insn_mul_rd_addr, Mux(spec_insn_and_valid, spec_insn_and_rd_addr, Mux(spec_insn_or_valid, spec_insn_or_rd_addr, Mux(spec_insn_sra_valid, spec_insn_sra_rd_addr, Mux(spec_insn_srl_valid, spec_insn_srl_rd_addr, Mux(spec_insn_xor_valid, spec_insn_xor_rd_addr, Mux(spec_insn_sltu_valid, spec_insn_sltu_rd_addr, Mux(spec_insn_slt_valid, spec_insn_slt_rd_addr, Mux(spec_insn_sll_valid, spec_insn_sll_rd_addr, Mux(spec_insn_sub_valid, spec_insn_sub_rd_addr, Mux(spec_insn_add_valid, spec_insn_add_rd_addr, Mux(spec_insn_srai_valid, spec_insn_srai_rd_addr, Mux(spec_insn_srli_valid, spec_insn_srli_rd_addr, Mux(spec_insn_slli_valid, spec_insn_slli_rd_addr, Mux(spec_insn_andi_valid, spec_insn_andi_rd_addr, Mux(spec_insn_ori_valid, spec_insn_ori_rd_addr, Mux(spec_insn_xori_valid, spec_insn_xori_rd_addr, Mux(spec_insn_sltiu_valid, spec_insn_sltiu_rd_addr, Mux(spec_insn_slti_valid, spec_insn_slti_rd_addr, Mux(spec_insn_addi_valid, spec_insn_addi_rd_addr, Mux(spec_insn_sw_valid, spec_insn_sw_rd_addr, Mux(spec_insn_sh_valid, spec_insn_sh_rd_addr, Mux(spec_insn_sb_valid, spec_insn_sb_rd_addr, Mux(spec_insn_lhu_valid, spec_insn_lhu_rd_addr, Mux(spec_insn_lbu_valid, spec_insn_lbu_rd_addr, Mux(spec_insn_lw_valid, spec_insn_lw_rd_addr, Mux(spec_insn_lh_valid, spec_insn_lh_rd_addr, Mux(spec_insn_lb_valid, spec_insn_lb_rd_addr, Mux(spec_insn_bgeu_valid, spec_insn_bgeu_rd_addr, Mux(spec_insn_bltu_valid, spec_insn_bltu_rd_addr, Mux(spec_insn_bge_valid, spec_insn_bge_rd_addr, Mux(spec_insn_blt_valid, spec_insn_blt_rd_addr, Mux(spec_insn_bne_valid, spec_insn_bne_rd_addr, Mux(spec_insn_beq_valid, spec_insn_beq_rd_addr, Mux(spec_insn_jalr_valid, spec_insn_jalr_rd_addr, Mux(spec_insn_jal_valid, spec_insn_jal_rd_addr, Mux(spec_insn_auipc_valid, spec_insn_auipc_rd_addr, Mux(spec_insn_lui_valid, spec_insn_lui_rd_addr, 0)))))))))))))))))))))))))))))))))))))))))))))) - m.d.comb += self.spec_rd_wdata.eq(Mux(spec_insn_remu_valid, spec_insn_remu_rd_wdata, Mux(spec_insn_rem_valid, spec_insn_rem_rd_wdata, Mux(spec_insn_divu_valid, spec_insn_divu_rd_wdata, Mux(spec_insn_div_valid, spec_insn_div_rd_wdata, Mux(spec_insn_mulhu_valid, spec_insn_mulhu_rd_wdata, Mux(spec_insn_mulhsu_valid, spec_insn_mulhsu_rd_wdata, Mux(spec_insn_mulh_valid, spec_insn_mulh_rd_wdata, Mux(spec_insn_mul_valid, spec_insn_mul_rd_wdata, Mux(spec_insn_and_valid, spec_insn_and_rd_wdata, Mux(spec_insn_or_valid, spec_insn_or_rd_wdata, Mux(spec_insn_sra_valid, spec_insn_sra_rd_wdata, Mux(spec_insn_srl_valid, spec_insn_srl_rd_wdata, Mux(spec_insn_xor_valid, spec_insn_xor_rd_wdata, Mux(spec_insn_sltu_valid, spec_insn_sltu_rd_wdata, Mux(spec_insn_slt_valid, spec_insn_slt_rd_wdata, Mux(spec_insn_sll_valid, spec_insn_sll_rd_wdata, Mux(spec_insn_sub_valid, spec_insn_sub_rd_wdata, Mux(spec_insn_add_valid, spec_insn_add_rd_wdata, Mux(spec_insn_srai_valid, spec_insn_srai_rd_wdata, Mux(spec_insn_srli_valid, spec_insn_srli_rd_wdata, Mux(spec_insn_slli_valid, spec_insn_slli_rd_wdata, Mux(spec_insn_andi_valid, spec_insn_andi_rd_wdata, Mux(spec_insn_ori_valid, spec_insn_ori_rd_wdata, Mux(spec_insn_xori_valid, spec_insn_xori_rd_wdata, Mux(spec_insn_sltiu_valid, spec_insn_sltiu_rd_wdata, Mux(spec_insn_slti_valid, spec_insn_slti_rd_wdata, Mux(spec_insn_addi_valid, spec_insn_addi_rd_wdata, Mux(spec_insn_sw_valid, spec_insn_sw_rd_wdata, Mux(spec_insn_sh_valid, spec_insn_sh_rd_wdata, Mux(spec_insn_sb_valid, spec_insn_sb_rd_wdata, Mux(spec_insn_lhu_valid, spec_insn_lhu_rd_wdata, Mux(spec_insn_lbu_valid, spec_insn_lbu_rd_wdata, Mux(spec_insn_lw_valid, spec_insn_lw_rd_wdata, Mux(spec_insn_lh_valid, spec_insn_lh_rd_wdata, Mux(spec_insn_lb_valid, spec_insn_lb_rd_wdata, Mux(spec_insn_bgeu_valid, spec_insn_bgeu_rd_wdata, Mux(spec_insn_bltu_valid, spec_insn_bltu_rd_wdata, Mux(spec_insn_bge_valid, spec_insn_bge_rd_wdata, Mux(spec_insn_blt_valid, spec_insn_blt_rd_wdata, Mux(spec_insn_bne_valid, spec_insn_bne_rd_wdata, Mux(spec_insn_beq_valid, spec_insn_beq_rd_wdata, Mux(spec_insn_jalr_valid, spec_insn_jalr_rd_wdata, Mux(spec_insn_jal_valid, spec_insn_jal_rd_wdata, Mux(spec_insn_auipc_valid, spec_insn_auipc_rd_wdata, Mux(spec_insn_lui_valid, spec_insn_lui_rd_wdata, 0)))))))))))))))))))))))))))))))))))))))))))))) - m.d.comb += self.spec_pc_wdata.eq(Mux(spec_insn_remu_valid, spec_insn_remu_pc_wdata, Mux(spec_insn_rem_valid, spec_insn_rem_pc_wdata, Mux(spec_insn_divu_valid, spec_insn_divu_pc_wdata, Mux(spec_insn_div_valid, spec_insn_div_pc_wdata, Mux(spec_insn_mulhu_valid, spec_insn_mulhu_pc_wdata, Mux(spec_insn_mulhsu_valid, spec_insn_mulhsu_pc_wdata, Mux(spec_insn_mulh_valid, spec_insn_mulh_pc_wdata, Mux(spec_insn_mul_valid, spec_insn_mul_pc_wdata, Mux(spec_insn_and_valid, spec_insn_and_pc_wdata, Mux(spec_insn_or_valid, spec_insn_or_pc_wdata, Mux(spec_insn_sra_valid, spec_insn_sra_pc_wdata, Mux(spec_insn_srl_valid, spec_insn_srl_pc_wdata, Mux(spec_insn_xor_valid, spec_insn_xor_pc_wdata, Mux(spec_insn_sltu_valid, spec_insn_sltu_pc_wdata, Mux(spec_insn_slt_valid, spec_insn_slt_pc_wdata, Mux(spec_insn_sll_valid, spec_insn_sll_pc_wdata, Mux(spec_insn_sub_valid, spec_insn_sub_pc_wdata, Mux(spec_insn_add_valid, spec_insn_add_pc_wdata, Mux(spec_insn_srai_valid, spec_insn_srai_pc_wdata, Mux(spec_insn_srli_valid, spec_insn_srli_pc_wdata, Mux(spec_insn_slli_valid, spec_insn_slli_pc_wdata, Mux(spec_insn_andi_valid, spec_insn_andi_pc_wdata, Mux(spec_insn_ori_valid, spec_insn_ori_pc_wdata, Mux(spec_insn_xori_valid, spec_insn_xori_pc_wdata, Mux(spec_insn_sltiu_valid, spec_insn_sltiu_pc_wdata, Mux(spec_insn_slti_valid, spec_insn_slti_pc_wdata, Mux(spec_insn_addi_valid, spec_insn_addi_pc_wdata, Mux(spec_insn_sw_valid, spec_insn_sw_pc_wdata, Mux(spec_insn_sh_valid, spec_insn_sh_pc_wdata, Mux(spec_insn_sb_valid, spec_insn_sb_pc_wdata, Mux(spec_insn_lhu_valid, spec_insn_lhu_pc_wdata, Mux(spec_insn_lbu_valid, spec_insn_lbu_pc_wdata, Mux(spec_insn_lw_valid, spec_insn_lw_pc_wdata, Mux(spec_insn_lh_valid, spec_insn_lh_pc_wdata, Mux(spec_insn_lb_valid, spec_insn_lb_pc_wdata, Mux(spec_insn_bgeu_valid, spec_insn_bgeu_pc_wdata, Mux(spec_insn_bltu_valid, spec_insn_bltu_pc_wdata, Mux(spec_insn_bge_valid, spec_insn_bge_pc_wdata, Mux(spec_insn_blt_valid, spec_insn_blt_pc_wdata, Mux(spec_insn_bne_valid, spec_insn_bne_pc_wdata, Mux(spec_insn_beq_valid, spec_insn_beq_pc_wdata, Mux(spec_insn_jalr_valid, spec_insn_jalr_pc_wdata, Mux(spec_insn_jal_valid, spec_insn_jal_pc_wdata, Mux(spec_insn_auipc_valid, spec_insn_auipc_pc_wdata, Mux(spec_insn_lui_valid, spec_insn_lui_pc_wdata, 0)))))))))))))))))))))))))))))))))))))))))))))) - m.d.comb += self.spec_mem_addr.eq(Mux(spec_insn_remu_valid, spec_insn_remu_mem_addr, Mux(spec_insn_rem_valid, spec_insn_rem_mem_addr, Mux(spec_insn_divu_valid, spec_insn_divu_mem_addr, Mux(spec_insn_div_valid, spec_insn_div_mem_addr, Mux(spec_insn_mulhu_valid, spec_insn_mulhu_mem_addr, Mux(spec_insn_mulhsu_valid, spec_insn_mulhsu_mem_addr, Mux(spec_insn_mulh_valid, spec_insn_mulh_mem_addr, Mux(spec_insn_mul_valid, spec_insn_mul_mem_addr, Mux(spec_insn_and_valid, spec_insn_and_mem_addr, Mux(spec_insn_or_valid, spec_insn_or_mem_addr, Mux(spec_insn_sra_valid, spec_insn_sra_mem_addr, Mux(spec_insn_srl_valid, spec_insn_srl_mem_addr, Mux(spec_insn_xor_valid, spec_insn_xor_mem_addr, Mux(spec_insn_sltu_valid, spec_insn_sltu_mem_addr, Mux(spec_insn_slt_valid, spec_insn_slt_mem_addr, Mux(spec_insn_sll_valid, spec_insn_sll_mem_addr, Mux(spec_insn_sub_valid, spec_insn_sub_mem_addr, Mux(spec_insn_add_valid, spec_insn_add_mem_addr, Mux(spec_insn_srai_valid, spec_insn_srai_mem_addr, Mux(spec_insn_srli_valid, spec_insn_srli_mem_addr, Mux(spec_insn_slli_valid, spec_insn_slli_mem_addr, Mux(spec_insn_andi_valid, spec_insn_andi_mem_addr, Mux(spec_insn_ori_valid, spec_insn_ori_mem_addr, Mux(spec_insn_xori_valid, spec_insn_xori_mem_addr, Mux(spec_insn_sltiu_valid, spec_insn_sltiu_mem_addr, Mux(spec_insn_slti_valid, spec_insn_slti_mem_addr, Mux(spec_insn_addi_valid, spec_insn_addi_mem_addr, Mux(spec_insn_sw_valid, spec_insn_sw_mem_addr, Mux(spec_insn_sh_valid, spec_insn_sh_mem_addr, Mux(spec_insn_sb_valid, spec_insn_sb_mem_addr, Mux(spec_insn_lhu_valid, spec_insn_lhu_mem_addr, Mux(spec_insn_lbu_valid, spec_insn_lbu_mem_addr, Mux(spec_insn_lw_valid, spec_insn_lw_mem_addr, Mux(spec_insn_lh_valid, spec_insn_lh_mem_addr, Mux(spec_insn_lb_valid, spec_insn_lb_mem_addr, Mux(spec_insn_bgeu_valid, spec_insn_bgeu_mem_addr, Mux(spec_insn_bltu_valid, spec_insn_bltu_mem_addr, Mux(spec_insn_bge_valid, spec_insn_bge_mem_addr, Mux(spec_insn_blt_valid, spec_insn_blt_mem_addr, Mux(spec_insn_bne_valid, spec_insn_bne_mem_addr, Mux(spec_insn_beq_valid, spec_insn_beq_mem_addr, Mux(spec_insn_jalr_valid, spec_insn_jalr_mem_addr, Mux(spec_insn_jal_valid, spec_insn_jal_mem_addr, Mux(spec_insn_auipc_valid, spec_insn_auipc_mem_addr, Mux(spec_insn_lui_valid, spec_insn_lui_mem_addr, 0)))))))))))))))))))))))))))))))))))))))))))))) - m.d.comb += self.spec_mem_rmask.eq(Mux(spec_insn_remu_valid, spec_insn_remu_mem_rmask, Mux(spec_insn_rem_valid, spec_insn_rem_mem_rmask, Mux(spec_insn_divu_valid, spec_insn_divu_mem_rmask, Mux(spec_insn_div_valid, spec_insn_div_mem_rmask, Mux(spec_insn_mulhu_valid, spec_insn_mulhu_mem_rmask, Mux(spec_insn_mulhsu_valid, spec_insn_mulhsu_mem_rmask, Mux(spec_insn_mulh_valid, spec_insn_mulh_mem_rmask, Mux(spec_insn_mul_valid, spec_insn_mul_mem_rmask, Mux(spec_insn_and_valid, spec_insn_and_mem_rmask, Mux(spec_insn_or_valid, spec_insn_or_mem_rmask, Mux(spec_insn_sra_valid, spec_insn_sra_mem_rmask, Mux(spec_insn_srl_valid, spec_insn_srl_mem_rmask, Mux(spec_insn_xor_valid, spec_insn_xor_mem_rmask, Mux(spec_insn_sltu_valid, spec_insn_sltu_mem_rmask, Mux(spec_insn_slt_valid, spec_insn_slt_mem_rmask, Mux(spec_insn_sll_valid, spec_insn_sll_mem_rmask, Mux(spec_insn_sub_valid, spec_insn_sub_mem_rmask, Mux(spec_insn_add_valid, spec_insn_add_mem_rmask, Mux(spec_insn_srai_valid, spec_insn_srai_mem_rmask, Mux(spec_insn_srli_valid, spec_insn_srli_mem_rmask, Mux(spec_insn_slli_valid, spec_insn_slli_mem_rmask, Mux(spec_insn_andi_valid, spec_insn_andi_mem_rmask, Mux(spec_insn_ori_valid, spec_insn_ori_mem_rmask, Mux(spec_insn_xori_valid, spec_insn_xori_mem_rmask, Mux(spec_insn_sltiu_valid, spec_insn_sltiu_mem_rmask, Mux(spec_insn_slti_valid, spec_insn_slti_mem_rmask, Mux(spec_insn_addi_valid, spec_insn_addi_mem_rmask, Mux(spec_insn_sw_valid, spec_insn_sw_mem_rmask, Mux(spec_insn_sh_valid, spec_insn_sh_mem_rmask, Mux(spec_insn_sb_valid, spec_insn_sb_mem_rmask, Mux(spec_insn_lhu_valid, spec_insn_lhu_mem_rmask, Mux(spec_insn_lbu_valid, spec_insn_lbu_mem_rmask, Mux(spec_insn_lw_valid, spec_insn_lw_mem_rmask, Mux(spec_insn_lh_valid, spec_insn_lh_mem_rmask, Mux(spec_insn_lb_valid, spec_insn_lb_mem_rmask, Mux(spec_insn_bgeu_valid, spec_insn_bgeu_mem_rmask, Mux(spec_insn_bltu_valid, spec_insn_bltu_mem_rmask, Mux(spec_insn_bge_valid, spec_insn_bge_mem_rmask, Mux(spec_insn_blt_valid, spec_insn_blt_mem_rmask, Mux(spec_insn_bne_valid, spec_insn_bne_mem_rmask, Mux(spec_insn_beq_valid, spec_insn_beq_mem_rmask, Mux(spec_insn_jalr_valid, spec_insn_jalr_mem_rmask, Mux(spec_insn_jal_valid, spec_insn_jal_mem_rmask, Mux(spec_insn_auipc_valid, spec_insn_auipc_mem_rmask, Mux(spec_insn_lui_valid, spec_insn_lui_mem_rmask, 0)))))))))))))))))))))))))))))))))))))))))))))) - m.d.comb += self.spec_mem_wmask.eq(Mux(spec_insn_remu_valid, spec_insn_remu_mem_wmask, Mux(spec_insn_rem_valid, spec_insn_rem_mem_wmask, Mux(spec_insn_divu_valid, spec_insn_divu_mem_wmask, Mux(spec_insn_div_valid, spec_insn_div_mem_wmask, Mux(spec_insn_mulhu_valid, spec_insn_mulhu_mem_wmask, Mux(spec_insn_mulhsu_valid, spec_insn_mulhsu_mem_wmask, Mux(spec_insn_mulh_valid, spec_insn_mulh_mem_wmask, Mux(spec_insn_mul_valid, spec_insn_mul_mem_wmask, Mux(spec_insn_and_valid, spec_insn_and_mem_wmask, Mux(spec_insn_or_valid, spec_insn_or_mem_wmask, Mux(spec_insn_sra_valid, spec_insn_sra_mem_wmask, Mux(spec_insn_srl_valid, spec_insn_srl_mem_wmask, Mux(spec_insn_xor_valid, spec_insn_xor_mem_wmask, Mux(spec_insn_sltu_valid, spec_insn_sltu_mem_wmask, Mux(spec_insn_slt_valid, spec_insn_slt_mem_wmask, Mux(spec_insn_sll_valid, spec_insn_sll_mem_wmask, Mux(spec_insn_sub_valid, spec_insn_sub_mem_wmask, Mux(spec_insn_add_valid, spec_insn_add_mem_wmask, Mux(spec_insn_srai_valid, spec_insn_srai_mem_wmask, Mux(spec_insn_srli_valid, spec_insn_srli_mem_wmask, Mux(spec_insn_slli_valid, spec_insn_slli_mem_wmask, Mux(spec_insn_andi_valid, spec_insn_andi_mem_wmask, Mux(spec_insn_ori_valid, spec_insn_ori_mem_wmask, Mux(spec_insn_xori_valid, spec_insn_xori_mem_wmask, Mux(spec_insn_sltiu_valid, spec_insn_sltiu_mem_wmask, Mux(spec_insn_slti_valid, spec_insn_slti_mem_wmask, Mux(spec_insn_addi_valid, spec_insn_addi_mem_wmask, Mux(spec_insn_sw_valid, spec_insn_sw_mem_wmask, Mux(spec_insn_sh_valid, spec_insn_sh_mem_wmask, Mux(spec_insn_sb_valid, spec_insn_sb_mem_wmask, Mux(spec_insn_lhu_valid, spec_insn_lhu_mem_wmask, Mux(spec_insn_lbu_valid, spec_insn_lbu_mem_wmask, Mux(spec_insn_lw_valid, spec_insn_lw_mem_wmask, Mux(spec_insn_lh_valid, spec_insn_lh_mem_wmask, Mux(spec_insn_lb_valid, spec_insn_lb_mem_wmask, Mux(spec_insn_bgeu_valid, spec_insn_bgeu_mem_wmask, Mux(spec_insn_bltu_valid, spec_insn_bltu_mem_wmask, Mux(spec_insn_bge_valid, spec_insn_bge_mem_wmask, Mux(spec_insn_blt_valid, spec_insn_blt_mem_wmask, Mux(spec_insn_bne_valid, spec_insn_bne_mem_wmask, Mux(spec_insn_beq_valid, spec_insn_beq_mem_wmask, Mux(spec_insn_jalr_valid, spec_insn_jalr_mem_wmask, Mux(spec_insn_jal_valid, spec_insn_jal_mem_wmask, Mux(spec_insn_auipc_valid, spec_insn_auipc_mem_wmask, Mux(spec_insn_lui_valid, spec_insn_lui_mem_wmask, 0)))))))))))))))))))))))))))))))))))))))))))))) - m.d.comb += self.spec_mem_wdata.eq(Mux(spec_insn_remu_valid, spec_insn_remu_mem_wdata, Mux(spec_insn_rem_valid, spec_insn_rem_mem_wdata, Mux(spec_insn_divu_valid, spec_insn_divu_mem_wdata, Mux(spec_insn_div_valid, spec_insn_div_mem_wdata, Mux(spec_insn_mulhu_valid, spec_insn_mulhu_mem_wdata, Mux(spec_insn_mulhsu_valid, spec_insn_mulhsu_mem_wdata, Mux(spec_insn_mulh_valid, spec_insn_mulh_mem_wdata, Mux(spec_insn_mul_valid, spec_insn_mul_mem_wdata, Mux(spec_insn_and_valid, spec_insn_and_mem_wdata, Mux(spec_insn_or_valid, spec_insn_or_mem_wdata, Mux(spec_insn_sra_valid, spec_insn_sra_mem_wdata, Mux(spec_insn_srl_valid, spec_insn_srl_mem_wdata, Mux(spec_insn_xor_valid, spec_insn_xor_mem_wdata, Mux(spec_insn_sltu_valid, spec_insn_sltu_mem_wdata, Mux(spec_insn_slt_valid, spec_insn_slt_mem_wdata, Mux(spec_insn_sll_valid, spec_insn_sll_mem_wdata, Mux(spec_insn_sub_valid, spec_insn_sub_mem_wdata, Mux(spec_insn_add_valid, spec_insn_add_mem_wdata, Mux(spec_insn_srai_valid, spec_insn_srai_mem_wdata, Mux(spec_insn_srli_valid, spec_insn_srli_mem_wdata, Mux(spec_insn_slli_valid, spec_insn_slli_mem_wdata, Mux(spec_insn_andi_valid, spec_insn_andi_mem_wdata, Mux(spec_insn_ori_valid, spec_insn_ori_mem_wdata, Mux(spec_insn_xori_valid, spec_insn_xori_mem_wdata, Mux(spec_insn_sltiu_valid, spec_insn_sltiu_mem_wdata, Mux(spec_insn_slti_valid, spec_insn_slti_mem_wdata, Mux(spec_insn_addi_valid, spec_insn_addi_mem_wdata, Mux(spec_insn_sw_valid, spec_insn_sw_mem_wdata, Mux(spec_insn_sh_valid, spec_insn_sh_mem_wdata, Mux(spec_insn_sb_valid, spec_insn_sb_mem_wdata, Mux(spec_insn_lhu_valid, spec_insn_lhu_mem_wdata, Mux(spec_insn_lbu_valid, spec_insn_lbu_mem_wdata, Mux(spec_insn_lw_valid, spec_insn_lw_mem_wdata, Mux(spec_insn_lh_valid, spec_insn_lh_mem_wdata, Mux(spec_insn_lb_valid, spec_insn_lb_mem_wdata, Mux(spec_insn_bgeu_valid, spec_insn_bgeu_mem_wdata, Mux(spec_insn_bltu_valid, spec_insn_bltu_mem_wdata, Mux(spec_insn_bge_valid, spec_insn_bge_mem_wdata, Mux(spec_insn_blt_valid, spec_insn_blt_mem_wdata, Mux(spec_insn_bne_valid, spec_insn_bne_mem_wdata, Mux(spec_insn_beq_valid, spec_insn_beq_mem_wdata, Mux(spec_insn_jalr_valid, spec_insn_jalr_mem_wdata, Mux(spec_insn_jal_valid, spec_insn_jal_mem_wdata, Mux(spec_insn_auipc_valid, spec_insn_auipc_mem_wdata, Mux(spec_insn_lui_valid, spec_insn_lui_mem_wdata, 0)))))))))))))))))))))))))))))))))))))))))))))) - - return m diff --git a/insns/isa_rv32im.txt b/insns/isa_rv32im.txt deleted file mode 100644 index f5412b3..0000000 --- a/insns/isa_rv32im.txt +++ /dev/null @@ -1,45 +0,0 @@ -lui -auipc -jal -jalr -beq -bne -blt -bge -bltu -bgeu -lb -lh -lw -lbu -lhu -sb -sh -sw -addi -slti -sltiu -xori -ori -andi -slli -srli -srai -add -sub -sll -slt -sltu -xor -srl -sra -or -and -mul -mulh -mulhsu -mulhu -div -divu -rem -remu diff --git a/insns/isa_rv32im_gen.py b/insns/isa_rv32im_gen.py deleted file mode 100644 index 3998357..0000000 --- a/insns/isa_rv32im_gen.py +++ /dev/null @@ -1,107 +0,0 @@ -with open('isa_rv32im.py', 'w') as isa_rv32im: - def fprint(strng): - print(strng, file=isa_rv32im) - fprint("# Generated by isa_rv32im_gen.py") - fprint("from nmigen import *") - with open('isa_rv32im.txt', 'r') as isa_rv32im_txt_file: - isa_rv32im_insns = isa_rv32im_txt_file.read().split('\n')[:-1] - for isa_rv32im_insn in isa_rv32im_insns: - fprint("from insn_%s import *" % isa_rv32im_insn) - fprint("") - fprint("class rvfi_isa_rv32im(Elaboratable):") - fprint(" def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):") - fprint(" self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN") - fprint(" self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN") - fprint(" self.rvfi_valid = Signal(1)") - fprint(" self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)") - fprint(" self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)") - fprint(" self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)") - fprint(" self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)") - fprint(" self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)") - fprint("") - fprint(" self.spec_valid = Signal(1)") - fprint(" self.spec_trap = Signal(1)") - fprint(" self.spec_rs1_addr = Signal(5)") - fprint(" self.spec_rs2_addr = Signal(5)") - fprint(" self.spec_rd_addr = Signal(5)") - fprint(" self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)") - fprint(" self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)") - fprint(" self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)") - fprint(" self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))") - fprint(" self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))") - fprint(" self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)") - fprint(" def ports(self):") - fprint(" input_ports = [") - fprint(" self.rvfi_valid,") - fprint(" self.rvfi_insn,") - fprint(" self.rvfi_pc_rdata,") - fprint(" self.rvfi_rs1_rdata,") - fprint(" self.rvfi_rs2_rdata,") - fprint(" self.rvfi_mem_rdata") - fprint(" ]") - fprint(" output_ports = [") - fprint(" self.spec_valid,") - fprint(" self.spec_trap,") - fprint(" self.spec_rs1_addr,") - fprint(" self.spec_rs2_addr,") - fprint(" self.spec_rd_addr,") - fprint(" self.spec_rd_wdata,") - fprint(" self.spec_pc_wdata,") - fprint(" self.spec_mem_addr,") - fprint(" self.spec_mem_rmask,") - fprint(" self.spec_mem_wmask,") - fprint(" self.spec_mem_wdata") - fprint(" ]") - fprint(" return input_ports + output_ports") - fprint(" def elaborate(self, platform):") - fprint(" m = Module()") - fprint("") - for isa_rv32im_insn in isa_rv32im_insns: - fprint(" spec_insn_%s_valid = Signal(1)" % isa_rv32im_insn) - fprint(" spec_insn_%s_trap = Signal(1)" % isa_rv32im_insn) - fprint(" spec_insn_%s_rs1_addr = Signal(5)" % isa_rv32im_insn) - fprint(" spec_insn_%s_rs2_addr = Signal(5)" % isa_rv32im_insn) - fprint(" spec_insn_%s_rd_addr = Signal(5)" % isa_rv32im_insn) - fprint(" spec_insn_%s_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)" % isa_rv32im_insn) - fprint(" spec_insn_%s_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)" % isa_rv32im_insn) - fprint(" spec_insn_%s_mem_addr = Signal(self.RISCV_FORMAL_XLEN)" % isa_rv32im_insn) - fprint(" spec_insn_%s_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))" % isa_rv32im_insn) - fprint(" spec_insn_%s_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))" % isa_rv32im_insn) - fprint(" spec_insn_%s_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)" % isa_rv32im_insn) - fprint(" m.submodules.insn_%s = insn_%s = rvfi_insn_%s()" % (isa_rv32im_insn, isa_rv32im_insn, isa_rv32im_insn)) - fprint(" m.d.comb += insn_%s.rvfi_valid.eq(self.rvfi_valid)" % isa_rv32im_insn) - fprint(" m.d.comb += insn_%s.rvfi_insn.eq(self.rvfi_insn)" % isa_rv32im_insn) - fprint(" m.d.comb += insn_%s.rvfi_pc_rdata.eq(self.rvfi_pc_rdata)" % isa_rv32im_insn) - fprint(" m.d.comb += insn_%s.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata)" % isa_rv32im_insn) - fprint(" m.d.comb += insn_%s.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata)" % isa_rv32im_insn) - fprint(" m.d.comb += insn_%s.rvfi_mem_rdata.eq(self.rvfi_mem_rdata)" % isa_rv32im_insn) - fprint(" m.d.comb += spec_insn_%s_valid.eq(insn_%s.spec_valid)" % (isa_rv32im_insn, isa_rv32im_insn)) - fprint(" m.d.comb += spec_insn_%s_trap.eq(insn_%s.spec_trap)" % (isa_rv32im_insn, isa_rv32im_insn)) - fprint(" m.d.comb += spec_insn_%s_rs1_addr.eq(insn_%s.spec_rs1_addr)" % (isa_rv32im_insn, isa_rv32im_insn)) - fprint(" m.d.comb += spec_insn_%s_rs2_addr.eq(insn_%s.spec_rs2_addr)" % (isa_rv32im_insn, isa_rv32im_insn)) - fprint(" m.d.comb += spec_insn_%s_rd_addr.eq(insn_%s.spec_rd_addr)" % (isa_rv32im_insn, isa_rv32im_insn)) - fprint(" m.d.comb += spec_insn_%s_rd_wdata.eq(insn_%s.spec_rd_wdata)" % (isa_rv32im_insn, isa_rv32im_insn)) - fprint(" m.d.comb += spec_insn_%s_pc_wdata.eq(insn_%s.spec_pc_wdata)" % (isa_rv32im_insn, isa_rv32im_insn)) - fprint(" m.d.comb += spec_insn_%s_mem_addr.eq(insn_%s.spec_mem_addr)" % (isa_rv32im_insn, isa_rv32im_insn)) - fprint(" m.d.comb += spec_insn_%s_mem_rmask.eq(insn_%s.spec_mem_rmask)" % (isa_rv32im_insn, isa_rv32im_insn)) - fprint(" m.d.comb += spec_insn_%s_mem_wmask.eq(insn_%s.spec_mem_wmask)" % (isa_rv32im_insn, isa_rv32im_insn)) - fprint(" m.d.comb += spec_insn_%s_mem_wdata.eq(insn_%s.spec_mem_wdata)" % (isa_rv32im_insn, isa_rv32im_insn)) - fprint("") - def gen_spec(strng): - result = "0" - for isa_rv32im_insn in isa_rv32im_insns: - result = "Mux(spec_insn_%s_valid, spec_insn_%s_%s, %s)" % (isa_rv32im_insn, isa_rv32im_insn, strng, result) - fprint(" m.d.comb += self.spec_%s.eq(%s)" % (strng, result)) - gen_spec("valid") - gen_spec("trap") - gen_spec("rs1_addr") - gen_spec("rs2_addr") - gen_spec("rd_addr") - gen_spec("rd_wdata") - gen_spec("pc_wdata") - gen_spec("mem_addr") - gen_spec("mem_rmask") - gen_spec("mem_wmask") - gen_spec("mem_wdata") - fprint("") - fprint(" return m") -- 2.44.1 From 7c420cce7abfa37715aa41715d57c55e7e5ad7ef Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Thu, 6 Aug 2020 14:13:00 +0800 Subject: [PATCH 002/109] Categorize all (to be) supported instructions --- insns/README.md | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 insns/README.md diff --git a/insns/README.md b/insns/README.md new file mode 100644 index 0000000..14d7434 --- /dev/null +++ b/insns/README.md @@ -0,0 +1,38 @@ +# RISC-V Supported Instructions + +## Instructions + +| Instruction type | Instructions | +| R-type | ADD, ADDW, AND, DIV, DIVU, DIVUW, DIVW, MUL, MULH, MULHSU, MULHU, MULW, OR, REM, REMU, REMUW, REMW, SLL, SLLW, SLT, SLTU, SRA, SRAW, SRL, SRLW, SUB, SUBW, XOR | +| I-type | ADDI, ADDIW, ANDI, JALR, LB, LBU, LD, LH, LHU, LW, LWU, ORI, SLTI, SLTIU, XORI | +| I-type (shift variation) | SLLI, SLLIW, SRAI, SRAIW, SRLI, SRLIW | +| S-type | SB, SD, SH, SW | +| SB-type | BEQ, BGE, BGEU, BLT, BLTU, BNE | +| U-type | AUIPC, LUI | +| J-type | JAL | +| CI-type | C\_ADD, C\_ADDI, C\_ADDIW, C\_JALR, C\_JR, C\_LI, C\_MV | +| CI-type (SP variation) | C\_ADDI16SP | +| CI-type (ANDI variation) | C\_ANDI | +| CI-type (LSP variation, 32 bit version) | C\_LWSP | +| CI-type (LSP variation, 64 bit version) | C\_LDSP | +| CI-type (LUI variation) | C\_LUI | +| CI-type (SLI variation) | C\_SLLI | +| CI-type (SRI variation) | C\_SRAI, C\_SRLI | +| CIW-type | C\_ADDI4SPN | +| CS-type (ALU version) | C\_ADDW, C\_AND, C\_OR, C\_SUB, C\_SUBW, C\_XOR | +| CS-type (32 bit version) | C\_SW | +| CS-type (64 bit version) | C\_SD | +| CSS-type (32 bit version) | C\_SWSP | +| CSS-type (64 bit version) | C\_SDSP | +| CB-type | C\_BEQZ, C\_BNEZ | +| CJ-type | C\_J, C\_JAL | +| CL-type (32 bit version) | C\_LW | +| CL-type (64 bit version) | C\_LD | + +## File Synopsis + +TODO + +## Parameters + +TODO -- 2.44.1 From 9a3cb8e88af90526111e657996c05bccc91dcc6e Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Thu, 6 Aug 2020 14:45:51 +0800 Subject: [PATCH 003/109] Fix table formatting in insns/README.md --- insns/README.md | 1 + 1 file changed, 1 insertion(+) diff --git a/insns/README.md b/insns/README.md index 14d7434..7d6ec87 100644 --- a/insns/README.md +++ b/insns/README.md @@ -3,6 +3,7 @@ ## Instructions | Instruction type | Instructions | +| --- | --- | | R-type | ADD, ADDW, AND, DIV, DIVU, DIVUW, DIVW, MUL, MULH, MULHSU, MULHU, MULW, OR, REM, REMU, REMUW, REMW, SLL, SLLW, SLT, SLTU, SRA, SRAW, SRL, SRLW, SUB, SUBW, XOR | | I-type | ADDI, ADDIW, ANDI, JALR, LB, LBU, LD, LH, LHU, LW, LWU, ORI, SLTI, SLTIU, XORI | | I-type (shift variation) | SLLI, SLLIW, SRAI, SRAIW, SRLI, SRLIW | -- 2.44.1 From 56048099b3e561109864b18c11a334d7a0cddd74 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Thu, 6 Aug 2020 16:44:54 +0800 Subject: [PATCH 004/109] Correct typo in insns/README.md --- insns/README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/insns/README.md b/insns/README.md index 7d6ec87..d9a0ebd 100644 --- a/insns/README.md +++ b/insns/README.md @@ -10,7 +10,7 @@ | S-type | SB, SD, SH, SW | | SB-type | BEQ, BGE, BGEU, BLT, BLTU, BNE | | U-type | AUIPC, LUI | -| J-type | JAL | +| UJ-type | JAL | | CI-type | C\_ADD, C\_ADDI, C\_ADDIW, C\_JALR, C\_JR, C\_LI, C\_MV | | CI-type (SP variation) | C\_ADDI16SP | | CI-type (ANDI variation) | C\_ANDI | -- 2.44.1 From a8cf15e123087b15f36a32ede45771d3e688385c Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Fri, 7 Aug 2020 12:28:52 +0800 Subject: [PATCH 005/109] Add generic instruction class --- insns/Insn.py | 107 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 107 insertions(+) create mode 100644 insns/Insn.py diff --git a/insns/Insn.py b/insns/Insn.py new file mode 100644 index 0000000..72dc7a0 --- /dev/null +++ b/insns/Insn.py @@ -0,0 +1,107 @@ +from nmigen import * + +""" +Insn.py +Class for generic RISC-V instructions +""" + +class Insn(Elaboratable): + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): + # Core-specific constants + self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN + self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN + self.RISCV_FORMAL_CSR_MISA = RISCV_FORMAL_CSR_MISA + self.RISCV_FORMAL_COMPRESSED = RISCV_FORMAL_COMPRESSED + + # RVFI input ports + self.rvfi_valid = Signal(1) + self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) + self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) + self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) + self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) + self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) + if self.RISCV_FORMAL_CSR_MISA: + self.rvfi_csr_misa_rdata = Signal(self.RISCV_FORMAL_XLEN) + + # RVFI output ports + if self.RISCV_FORMAL_CSR_MISA: + self.spec_csr_misa_rmask = Signal(self.RISCV_FORMAL_XLEN) + self.spec_valid = Signal(1) + self.spec_trap = Signal(1) + self.spec_rs1_addr = Signal(5) + self.spec_rs2_addr = Signal(5) + self.spec_rd_addr = Signal(5) + self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) + self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) + self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) + self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) + self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) + self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) + + # Additional wires and registers + self.insn_padding = Signal(self.RISCV_FORMAL_ILEN) + self.insn_imm = Signal(self.RISCV_FORMAL_XLEN) + self.insn_funct7 = Signal(7) + self.insn_funct6 = Signal(6) + self.insn_shamt = Signal(6) + self.insn_rs2 = Signal(5) + self.insn_rs1 = Signal(5) + self.insn_funct3 = Signal(3) + self.insn_rd = Signal(5) + self.insn_opcode = Signal(7) + self.misa_ok = Signal(1) + self.ialign16 = Signal(1) + def ports(self): + input_ports = [ + self.rvfi_valid, + self.rvfi_insn, + self.rvfi_pc_rdata, + self.rvfi_rs1_rdata, + self.rvfi_rs2_rdata, + self.rvfi_mem_rdata + ] + if self.RISCV_FORMAL_CSR_MISA: + input_ports.append(self.rvfi_csr_misa_rdata) + output_ports = [ + self.spec_valid, + self.spec_trap, + self.spec_rs1_addr, + self.spec_rs2_addr, + self.spec_rd_addr, + self.spec_rd_wdata, + self.spec_pc_wdata, + self.spec_mem_addr, + self.spec_mem_rmask, + self.spec_mem_wmask, + self.spec_mem_wdata + ] + if self.RISCV_FORMAL_CSR_MISA: + output_ports.append(self.spec_csr_misa_rmask) + return input_ports + output_ports + def elaborate(self, platform): + m = Module() + + m.d.comb += self.insn_padding.eq(self.rvfi_insn >> 32) + m.d.comb += self.insn_funct7.eq(self.rvfi_insn[25:32]) + m.d.comb += self.insn_funct6.eq(self.rvfi_insn[26:32]) + m.d.comb += self.insn_shamt.eq(self.rvfi_insn[20:26]) + m.d.comb += self.insn_rs2.eq(self.rvfi_insn[20:25]) + m.d.comb += self.insn_rs1.eq(self.rvfi_insn[15:20]) + m.d.comb += self.insn_funct3.eq(self.rvfi_insn[12:15]) + m.d.comb += self.insn_rd.eq(self.rvfi_insn[7:12]) + m.d.comb += self.insn_opcode.eq(self.rvfi_insn[:7]) + + # default assignments + m.d.comb += self.spec_valid.eq(0) + m.d.comb += self.spec_trap.eq(~self.misa_ok) + m.d.comb += self.spec_rs1_addr.eq(0) + m.d.comb += self.spec_rs2_addr.eq(0) + m.d.comb += self.spec_rd_addr.eq(0) + m.d.comb += self.spec_rd_wdata.eq(0) + m.d.comb += self.spec_pc_wdata.eq(0) + m.d.comb += self.spec_mem_addr.eq(0) + m.d.comb += self.spec_mem_rmask.eq(0) + m.d.comb += self.spec_mem_wmask.eq(0) + m.d.comb += self.spec_mem_wdata.eq(0) + + return m -- 2.44.1 From 2e2300e5c8b62d03f744c4839911f55b783e317d Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Fri, 7 Aug 2020 12:54:31 +0800 Subject: [PATCH 006/109] Update insns/README.md --- insns/README.md | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/insns/README.md b/insns/README.md index d9a0ebd..a8ca67e 100644 --- a/insns/README.md +++ b/insns/README.md @@ -30,9 +30,11 @@ | CL-type (32 bit version) | C\_LW | | CL-type (64 bit version) | C\_LD | -## File Synopsis +## Class Synopsis -TODO +_Note: This section is under development and will be updated as more classes are implemented._ + +- `Insn`: General RISC-V instruction ## Parameters -- 2.44.1 From 4f7b11d009cb6bb02bc7c23eb3b924587213550d Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Fri, 7 Aug 2020 13:45:35 +0800 Subject: [PATCH 007/109] Add RV32I R-Type Instruction --- insns/InsnRV32IRType.py | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 insns/InsnRV32IRType.py diff --git a/insns/InsnRV32IRType.py b/insns/InsnRV32IRType.py new file mode 100644 index 0000000..f990e53 --- /dev/null +++ b/insns/InsnRV32IRType.py @@ -0,0 +1,28 @@ +from Insn import * + +""" +RV32I R-Type Instruction +""" + +class InsnRV32IRType(Insn): + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, funct7, funct3, opcode): + super(InsnRV32IRType, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED) + self.funct7 = funct7 + self.funct3 = funct3 + self.opcode = opcode + def elaborate(self, platform): + m = super(InsnRV32IRType, self).elaborate(platform) + + if self.RISCV_FORMAL_CSR_MISA: + m.d.comb += self.misa_ok.eq((self.rvfi_csr_misa_rdata & 0) == 0) + m.d.comb += self.spec_csr_misa_rmask.eq(0) + else: + m.d.comb += self.misa_ok.eq(1) + + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == self.funct7) & (self.insn_funct3 == self.funct3) & (self.insn_opcode == self.opcode)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) + m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) + + return m -- 2.44.1 From ccc1bd098b32ea58ac4dbb72458536505cf71838 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Fri, 7 Aug 2020 13:54:00 +0800 Subject: [PATCH 008/109] Add ADD instruction --- insns/InsnAdd.py | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 insns/InsnAdd.py diff --git a/insns/InsnAdd.py b/insns/InsnAdd.py new file mode 100644 index 0000000..16d2de3 --- /dev/null +++ b/insns/InsnAdd.py @@ -0,0 +1,11 @@ +from InsnRV32IRType import * + +class InsnAdd(InsnRV32IRType): + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): + super(InsnAdd, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b000, 0b0110011) + def elaborate(self, platform): + m = super(InsnAdd, self).elaborate(platform) + + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_rs1_rdata + self.rvfi_rs2_rdata, 0)) + + return m -- 2.44.1 From 060dd9891979670857f180c7ff967adbaf416373 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Fri, 7 Aug 2020 14:00:12 +0800 Subject: [PATCH 009/109] Add SUB instruction --- insns/InsnSub.py | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 insns/InsnSub.py diff --git a/insns/InsnSub.py b/insns/InsnSub.py new file mode 100644 index 0000000..85bf28c --- /dev/null +++ b/insns/InsnSub.py @@ -0,0 +1,11 @@ +from InsnRV32IRType import * + +class InsnSub(InsnRV32IRType): + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): + super(InsnSub, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0100000, 0b000, 0b0110011) + def elaborate(self, platform): + m = super(InsnSub, self).elaborate(platform) + + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_rs1_rdata - self.rvfi_rs2_rdata, 0)) + + return m -- 2.44.1 From 44bdff60c878702032d22770c3d24c166017c4fc Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Fri, 7 Aug 2020 15:25:05 +0800 Subject: [PATCH 010/109] Add SLL instruction --- insns/InsnSll.py | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 insns/InsnSll.py diff --git a/insns/InsnSll.py b/insns/InsnSll.py new file mode 100644 index 0000000..f825bb9 --- /dev/null +++ b/insns/InsnSll.py @@ -0,0 +1,11 @@ +from InsnRV32IRType import * + +class InsnSll(InsnRV32IRType): + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): + super(InsnSll, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b001, 0b0110011) + def elaborate(self, platform): + m = super(InsnSll, self).elaborate(platform) + + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_rs1_rdata << Mux(self.RISCV_FORMAL_XLEN == 64, self.rvfi_rs2_rdata[:6], self.rvfi_rs2_rdata[:5]), 0)) + + return m -- 2.44.1 From d33dc1b137cd93d32e11147e2912043be220f3f1 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Fri, 7 Aug 2020 15:29:54 +0800 Subject: [PATCH 011/109] Add SLT instruction --- insns/InsnSlt.py | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 insns/InsnSlt.py diff --git a/insns/InsnSlt.py b/insns/InsnSlt.py new file mode 100644 index 0000000..7ba4b9e --- /dev/null +++ b/insns/InsnSlt.py @@ -0,0 +1,11 @@ +from InsnRV32IRType import * + +class InsnSlt(InsnRV32IRType): + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): + super(InsnSlt, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b010, 0b0110011) + def elaborate(self, platform): + m = super(InsnSlt, self).elaborate(platform) + + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, Value.as_signed(self.rvfi_rs1_rdata) < Value.as_signed(self.rvfi_rs2_rdata), 0)) + + return m -- 2.44.1 From cab30848e92283c9220f92747649008c18eab8c0 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Fri, 7 Aug 2020 15:33:18 +0800 Subject: [PATCH 012/109] Add SLTU instruction --- insns/InsnSltu.py | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 insns/InsnSltu.py diff --git a/insns/InsnSltu.py b/insns/InsnSltu.py new file mode 100644 index 0000000..aa2f207 --- /dev/null +++ b/insns/InsnSltu.py @@ -0,0 +1,11 @@ +from InsnRV32IRType import * + +class InsnSltu(InsnRV32IRType): + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): + super(InsnSltu, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b011, 0b0110011) + def elaborate(self, platform): + m = super(InsnSltu, self).elaborate(platform) + + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_rs1_rdata < self.rvfi_rs2_rdata, 0)) + + return m -- 2.44.1 From d106ceede79a8918714a9d5bf2647730007372f8 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Fri, 7 Aug 2020 15:35:40 +0800 Subject: [PATCH 013/109] Add XOR instruction --- insns/InsnXor.py | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 insns/InsnXor.py diff --git a/insns/InsnXor.py b/insns/InsnXor.py new file mode 100644 index 0000000..4e08162 --- /dev/null +++ b/insns/InsnXor.py @@ -0,0 +1,11 @@ +from InsnRV32IRType import * + +class InsnXor(InsnRV32IRType): + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): + super(InsnXor, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b100, 0b0110011) + def elaborate(self, platform): + m = super(InsnXor, self).elaborate(platform) + + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_rs1_rdata ^ self.rvfi_rs2_rdata, 0)) + + return m -- 2.44.1 From 4f7cf5a3706c8981d829af068d37ccbaa3167ec3 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Fri, 7 Aug 2020 15:39:46 +0800 Subject: [PATCH 014/109] Add SRL instruction --- insns/InsnSrl.py | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 insns/InsnSrl.py diff --git a/insns/InsnSrl.py b/insns/InsnSrl.py new file mode 100644 index 0000000..51c1b06 --- /dev/null +++ b/insns/InsnSrl.py @@ -0,0 +1,11 @@ +from InsnRV32IRType import * + +class InsnSrl(InsnRV32IRType): + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): + super(InsnSrl, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b100, 0b0110011) + def elaborate(self, platform): + m = super(InsnSrl, self).elaborate(platform) + + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_rs1_rdata >> Mux(self.RISCV_FORMAL_XLEN == 64, self.rvfi_rs2_rdata[:6], self.rvfi_rs2_rdata[:5]), 0)) + + return m -- 2.44.1 From d06daac123ece13904faa52b0fb82220b8c82489 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Fri, 7 Aug 2020 15:51:21 +0800 Subject: [PATCH 015/109] Add SRA instruction --- insns/InsnSra.py | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 insns/InsnSra.py diff --git a/insns/InsnSra.py b/insns/InsnSra.py new file mode 100644 index 0000000..bccf74b --- /dev/null +++ b/insns/InsnSra.py @@ -0,0 +1,11 @@ +from InsnRV32IRType import * + +class InsnSra(InsnRV32IRType): + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): + super(InsnSra, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0100000, 0b101, 0b0110011) + def elaborate(self, platform): + m = super(InsnSra, self).elaborate(platform) + + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, (Value.as_signed(self.rvfi_rs1_rdata) >> Mux(self.RISCV_FORMAL_XLEN == 64, self.rvfi_rs2_rdata[:6], self.rvfi_rs2_rdata[:5])) | (-(Value.as_signed(self.rvfi_rs1_rdata) < 0) << (self.RISCV_FORMAL_XLEN - Mux(self.RISCV_FORMAL_XLEN == 64, self.rvfi_rs2_rdata[:6], self.rvfi_rs2_rdata[:5]))), 0)) + + return m -- 2.44.1 From 07e4c04b2645ced458094c2da787686a418a0192 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Fri, 7 Aug 2020 15:54:18 +0800 Subject: [PATCH 016/109] Add OR instruction --- insns/InsnOr.py | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 insns/InsnOr.py diff --git a/insns/InsnOr.py b/insns/InsnOr.py new file mode 100644 index 0000000..241faa0 --- /dev/null +++ b/insns/InsnOr.py @@ -0,0 +1,11 @@ +from InsnRV32IRType import * + +class InsnOr(InsnRV32IRType): + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): + super(InsnOr, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b110, 0b0110011) + def elaborate(self, platform): + m = super(InsnOr, self).elaborate(platform) + + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_rs1_rdata | self.rvfi_rs2_rdata, 0)) + + return m -- 2.44.1 From 9bfd155b44aae4e0934ed1ae7ac82aa4cd88b5b0 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Fri, 7 Aug 2020 15:57:19 +0800 Subject: [PATCH 017/109] Add AND instruction --- insns/InsnAnd.py | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 insns/InsnAnd.py diff --git a/insns/InsnAnd.py b/insns/InsnAnd.py new file mode 100644 index 0000000..0194446 --- /dev/null +++ b/insns/InsnAnd.py @@ -0,0 +1,11 @@ +from InsnRV32IRType import * + +class InsnAnd(InsnRV32IRType): + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): + super(InsnAnd, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b111, 0b0110011) + def elaborate(self, platform): + m = super(InsnAnd, self).elaborate(platform) + + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_rs1_rdata & self.rvfi_rs2_rdata, 0)) + + return m -- 2.44.1 From 1c0541cd12c888c6a5e63bd416a1f76342489b55 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Fri, 7 Aug 2020 16:06:15 +0800 Subject: [PATCH 018/109] Document RV32I R-Type Instructions --- insns/InsnAdd.py | 4 ++++ insns/InsnAnd.py | 4 ++++ insns/InsnOr.py | 4 ++++ insns/InsnSll.py | 4 ++++ insns/InsnSlt.py | 4 ++++ insns/InsnSltu.py | 4 ++++ insns/InsnSra.py | 4 ++++ insns/InsnSrl.py | 4 ++++ insns/InsnSub.py | 4 ++++ insns/InsnXor.py | 4 ++++ insns/README.md | 11 +++++++++++ 11 files changed, 51 insertions(+) diff --git a/insns/InsnAdd.py b/insns/InsnAdd.py index 16d2de3..018afbc 100644 --- a/insns/InsnAdd.py +++ b/insns/InsnAdd.py @@ -1,5 +1,9 @@ from InsnRV32IRType import * +""" +ADD instruction +""" + class InsnAdd(InsnRV32IRType): def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): super(InsnAdd, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b000, 0b0110011) diff --git a/insns/InsnAnd.py b/insns/InsnAnd.py index 0194446..e0f4adb 100644 --- a/insns/InsnAnd.py +++ b/insns/InsnAnd.py @@ -1,5 +1,9 @@ from InsnRV32IRType import * +""" +AND instruction +""" + class InsnAnd(InsnRV32IRType): def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): super(InsnAnd, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b111, 0b0110011) diff --git a/insns/InsnOr.py b/insns/InsnOr.py index 241faa0..1470644 100644 --- a/insns/InsnOr.py +++ b/insns/InsnOr.py @@ -1,5 +1,9 @@ from InsnRV32IRType import * +""" +OR instruction +""" + class InsnOr(InsnRV32IRType): def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): super(InsnOr, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b110, 0b0110011) diff --git a/insns/InsnSll.py b/insns/InsnSll.py index f825bb9..bb99acb 100644 --- a/insns/InsnSll.py +++ b/insns/InsnSll.py @@ -1,5 +1,9 @@ from InsnRV32IRType import * +""" +SLL instruction +""" + class InsnSll(InsnRV32IRType): def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): super(InsnSll, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b001, 0b0110011) diff --git a/insns/InsnSlt.py b/insns/InsnSlt.py index 7ba4b9e..4f2be0f 100644 --- a/insns/InsnSlt.py +++ b/insns/InsnSlt.py @@ -1,5 +1,9 @@ from InsnRV32IRType import * +""" +SLT instruction +""" + class InsnSlt(InsnRV32IRType): def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): super(InsnSlt, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b010, 0b0110011) diff --git a/insns/InsnSltu.py b/insns/InsnSltu.py index aa2f207..318f717 100644 --- a/insns/InsnSltu.py +++ b/insns/InsnSltu.py @@ -1,5 +1,9 @@ from InsnRV32IRType import * +""" +SLTU instruction +""" + class InsnSltu(InsnRV32IRType): def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): super(InsnSltu, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b011, 0b0110011) diff --git a/insns/InsnSra.py b/insns/InsnSra.py index bccf74b..bbdc626 100644 --- a/insns/InsnSra.py +++ b/insns/InsnSra.py @@ -1,5 +1,9 @@ from InsnRV32IRType import * +""" +SRA instruction +""" + class InsnSra(InsnRV32IRType): def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): super(InsnSra, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0100000, 0b101, 0b0110011) diff --git a/insns/InsnSrl.py b/insns/InsnSrl.py index 51c1b06..ad93d47 100644 --- a/insns/InsnSrl.py +++ b/insns/InsnSrl.py @@ -1,5 +1,9 @@ from InsnRV32IRType import * +""" +SRL instruction +""" + class InsnSrl(InsnRV32IRType): def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): super(InsnSrl, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b100, 0b0110011) diff --git a/insns/InsnSub.py b/insns/InsnSub.py index 85bf28c..d8bf5fd 100644 --- a/insns/InsnSub.py +++ b/insns/InsnSub.py @@ -1,5 +1,9 @@ from InsnRV32IRType import * +""" +SUB instruction +""" + class InsnSub(InsnRV32IRType): def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): super(InsnSub, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0100000, 0b000, 0b0110011) diff --git a/insns/InsnXor.py b/insns/InsnXor.py index 4e08162..58c4978 100644 --- a/insns/InsnXor.py +++ b/insns/InsnXor.py @@ -1,5 +1,9 @@ from InsnRV32IRType import * +""" +XOR instruction +""" + class InsnXor(InsnRV32IRType): def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): super(InsnXor, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b100, 0b0110011) diff --git a/insns/README.md b/insns/README.md index a8ca67e..37bae7a 100644 --- a/insns/README.md +++ b/insns/README.md @@ -35,6 +35,17 @@ _Note: This section is under development and will be updated as more classes are implemented._ - `Insn`: General RISC-V instruction + - `InsnRV32IRType`: RV32I R-Type Instruction + - `InsnAdd`: ADD instruction + - `InsnSub`: SUB instruction + - `InsnSll`: SLL instruction + - `InsnSlt`: SLT instruction + - `InsnSltu`: SLTU instruction + - `InsnXor`: XOR instruction + - `InsnSrl`: SRL instruction + - `InsnSra`: SRA instruction + - `InsnOr`: OR instruction + - `InsnAnd`: AND instruction ## Parameters -- 2.44.1 From 9e64c7ee176d1681284b0c5b437d1e865c9e88cb Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Fri, 7 Aug 2020 16:39:14 +0800 Subject: [PATCH 019/109] Add RV32I I-Type Instruction (Shift Variation) --- insns/InsnRV32IITypeShift.py | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 insns/InsnRV32IITypeShift.py diff --git a/insns/InsnRV32IITypeShift.py b/insns/InsnRV32IITypeShift.py new file mode 100644 index 0000000..ab28f2c --- /dev/null +++ b/insns/InsnRV32IITypeShift.py @@ -0,0 +1,26 @@ +from Insn import * + +""" +RV32I I-Type Instruction (Shift Variation) +""" + +class InsnRV32IITypeShift(Insn): + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, funct6, funct3): + super(InsnRV32IITypeShift, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED) + self.funct6 = funct6 + self.funct3 = funct3 + def elaborate(self, platform): + m = super(InsnRV32IITypeShift, self).elaborate(platform) + + if self.RISCV_FORMAL_CSR_MISA: + m.d.comb += self.misa_ok.eq((self.rvfi_csr_misa_rdata & 0) == 0) + m.d.comb += self.spec_csr_misa_rmask.eq(0) + else: + m.d.comb += self.misa_ok.eq(1) + + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct6 == self.funct6) & (self.insn_funct3 == self.funct3) & (self.insn_opcode == 0b0010011) & ((~self.insn_shamt[5]) | (self.RISCV_FORMAL_XLEN == 64))) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) + m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) + + return m -- 2.44.1 From 94faa3ba680804d26dd75bba9aa51d630650b568 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Mon, 10 Aug 2020 11:15:05 +0800 Subject: [PATCH 020/109] Remove redundancy in super() calls --- insns/InsnAdd.py | 4 ++-- insns/InsnAnd.py | 4 ++-- insns/InsnOr.py | 4 ++-- insns/InsnRV32IITypeShift.py | 4 ++-- insns/InsnRV32IRType.py | 4 ++-- insns/InsnSll.py | 4 ++-- insns/InsnSlt.py | 4 ++-- insns/InsnSltu.py | 4 ++-- insns/InsnSra.py | 4 ++-- insns/InsnSrl.py | 4 ++-- insns/InsnSub.py | 4 ++-- insns/InsnXor.py | 4 ++-- 12 files changed, 24 insertions(+), 24 deletions(-) diff --git a/insns/InsnAdd.py b/insns/InsnAdd.py index 018afbc..d495fe0 100644 --- a/insns/InsnAdd.py +++ b/insns/InsnAdd.py @@ -6,9 +6,9 @@ ADD instruction class InsnAdd(InsnRV32IRType): def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): - super(InsnAdd, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b000, 0b0110011) + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b000, 0b0110011) def elaborate(self, platform): - m = super(InsnAdd, self).elaborate(platform) + m = super().elaborate(platform) m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_rs1_rdata + self.rvfi_rs2_rdata, 0)) diff --git a/insns/InsnAnd.py b/insns/InsnAnd.py index e0f4adb..b874914 100644 --- a/insns/InsnAnd.py +++ b/insns/InsnAnd.py @@ -6,9 +6,9 @@ AND instruction class InsnAnd(InsnRV32IRType): def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): - super(InsnAnd, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b111, 0b0110011) + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b111, 0b0110011) def elaborate(self, platform): - m = super(InsnAnd, self).elaborate(platform) + m = super().elaborate(platform) m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_rs1_rdata & self.rvfi_rs2_rdata, 0)) diff --git a/insns/InsnOr.py b/insns/InsnOr.py index 1470644..ed832a0 100644 --- a/insns/InsnOr.py +++ b/insns/InsnOr.py @@ -6,9 +6,9 @@ OR instruction class InsnOr(InsnRV32IRType): def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): - super(InsnOr, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b110, 0b0110011) + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b110, 0b0110011) def elaborate(self, platform): - m = super(InsnOr, self).elaborate(platform) + m = super().elaborate(platform) m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_rs1_rdata | self.rvfi_rs2_rdata, 0)) diff --git a/insns/InsnRV32IITypeShift.py b/insns/InsnRV32IITypeShift.py index ab28f2c..62f6403 100644 --- a/insns/InsnRV32IITypeShift.py +++ b/insns/InsnRV32IITypeShift.py @@ -6,11 +6,11 @@ RV32I I-Type Instruction (Shift Variation) class InsnRV32IITypeShift(Insn): def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, funct6, funct3): - super(InsnRV32IITypeShift, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED) + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED) self.funct6 = funct6 self.funct3 = funct3 def elaborate(self, platform): - m = super(InsnRV32IITypeShift, self).elaborate(platform) + m = super().elaborate(platform) if self.RISCV_FORMAL_CSR_MISA: m.d.comb += self.misa_ok.eq((self.rvfi_csr_misa_rdata & 0) == 0) diff --git a/insns/InsnRV32IRType.py b/insns/InsnRV32IRType.py index f990e53..c14dabd 100644 --- a/insns/InsnRV32IRType.py +++ b/insns/InsnRV32IRType.py @@ -6,12 +6,12 @@ RV32I R-Type Instruction class InsnRV32IRType(Insn): def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, funct7, funct3, opcode): - super(InsnRV32IRType, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED) + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED) self.funct7 = funct7 self.funct3 = funct3 self.opcode = opcode def elaborate(self, platform): - m = super(InsnRV32IRType, self).elaborate(platform) + m = super().elaborate(platform) if self.RISCV_FORMAL_CSR_MISA: m.d.comb += self.misa_ok.eq((self.rvfi_csr_misa_rdata & 0) == 0) diff --git a/insns/InsnSll.py b/insns/InsnSll.py index bb99acb..5b55dbf 100644 --- a/insns/InsnSll.py +++ b/insns/InsnSll.py @@ -6,9 +6,9 @@ SLL instruction class InsnSll(InsnRV32IRType): def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): - super(InsnSll, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b001, 0b0110011) + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b001, 0b0110011) def elaborate(self, platform): - m = super(InsnSll, self).elaborate(platform) + m = super().elaborate(platform) m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_rs1_rdata << Mux(self.RISCV_FORMAL_XLEN == 64, self.rvfi_rs2_rdata[:6], self.rvfi_rs2_rdata[:5]), 0)) diff --git a/insns/InsnSlt.py b/insns/InsnSlt.py index 4f2be0f..89807ea 100644 --- a/insns/InsnSlt.py +++ b/insns/InsnSlt.py @@ -6,9 +6,9 @@ SLT instruction class InsnSlt(InsnRV32IRType): def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): - super(InsnSlt, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b010, 0b0110011) + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b010, 0b0110011) def elaborate(self, platform): - m = super(InsnSlt, self).elaborate(platform) + m = super().elaborate(platform) m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, Value.as_signed(self.rvfi_rs1_rdata) < Value.as_signed(self.rvfi_rs2_rdata), 0)) diff --git a/insns/InsnSltu.py b/insns/InsnSltu.py index 318f717..ff9f3ec 100644 --- a/insns/InsnSltu.py +++ b/insns/InsnSltu.py @@ -6,9 +6,9 @@ SLTU instruction class InsnSltu(InsnRV32IRType): def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): - super(InsnSltu, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b011, 0b0110011) + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b011, 0b0110011) def elaborate(self, platform): - m = super(InsnSltu, self).elaborate(platform) + m = super().elaborate(platform) m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_rs1_rdata < self.rvfi_rs2_rdata, 0)) diff --git a/insns/InsnSra.py b/insns/InsnSra.py index bbdc626..0b1f133 100644 --- a/insns/InsnSra.py +++ b/insns/InsnSra.py @@ -6,9 +6,9 @@ SRA instruction class InsnSra(InsnRV32IRType): def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): - super(InsnSra, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0100000, 0b101, 0b0110011) + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0100000, 0b101, 0b0110011) def elaborate(self, platform): - m = super(InsnSra, self).elaborate(platform) + m = super().elaborate(platform) m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, (Value.as_signed(self.rvfi_rs1_rdata) >> Mux(self.RISCV_FORMAL_XLEN == 64, self.rvfi_rs2_rdata[:6], self.rvfi_rs2_rdata[:5])) | (-(Value.as_signed(self.rvfi_rs1_rdata) < 0) << (self.RISCV_FORMAL_XLEN - Mux(self.RISCV_FORMAL_XLEN == 64, self.rvfi_rs2_rdata[:6], self.rvfi_rs2_rdata[:5]))), 0)) diff --git a/insns/InsnSrl.py b/insns/InsnSrl.py index ad93d47..f68164c 100644 --- a/insns/InsnSrl.py +++ b/insns/InsnSrl.py @@ -6,9 +6,9 @@ SRL instruction class InsnSrl(InsnRV32IRType): def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): - super(InsnSrl, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b100, 0b0110011) + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b100, 0b0110011) def elaborate(self, platform): - m = super(InsnSrl, self).elaborate(platform) + m = super().elaborate(platform) m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_rs1_rdata >> Mux(self.RISCV_FORMAL_XLEN == 64, self.rvfi_rs2_rdata[:6], self.rvfi_rs2_rdata[:5]), 0)) diff --git a/insns/InsnSub.py b/insns/InsnSub.py index d8bf5fd..b5435d8 100644 --- a/insns/InsnSub.py +++ b/insns/InsnSub.py @@ -6,9 +6,9 @@ SUB instruction class InsnSub(InsnRV32IRType): def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): - super(InsnSub, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0100000, 0b000, 0b0110011) + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0100000, 0b000, 0b0110011) def elaborate(self, platform): - m = super(InsnSub, self).elaborate(platform) + m = super().elaborate(platform) m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_rs1_rdata - self.rvfi_rs2_rdata, 0)) diff --git a/insns/InsnXor.py b/insns/InsnXor.py index 58c4978..0569fa7 100644 --- a/insns/InsnXor.py +++ b/insns/InsnXor.py @@ -6,9 +6,9 @@ XOR instruction class InsnXor(InsnRV32IRType): def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): - super(InsnXor, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b100, 0b0110011) + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b100, 0b0110011) def elaborate(self, platform): - m = super(InsnXor, self).elaborate(platform) + m = super().elaborate(platform) m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_rs1_rdata ^ self.rvfi_rs2_rdata, 0)) -- 2.44.1 From 1fb51e614d31dff093f131bed848d0484753fd4d Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Mon, 10 Aug 2020 12:29:52 +0800 Subject: [PATCH 021/109] Add SLLI instruction --- insns/InsnSlli.py | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 insns/InsnSlli.py diff --git a/insns/InsnSlli.py b/insns/InsnSlli.py new file mode 100644 index 0000000..0292cfa --- /dev/null +++ b/insns/InsnSlli.py @@ -0,0 +1,11 @@ +from InsnRV32IITypeShift import * + +class InsnSlli(InsnRV32IITypeShift): + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b000000, 0b001) + def elaborate(self, platform): + m = super().elaborate(platform) + + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_rs1_rdata << self.insn_shamt, 0)) + + return m -- 2.44.1 From 031f3353253a8e4a15f2a53c138fe5ed7c87f404 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Mon, 10 Aug 2020 12:31:20 +0800 Subject: [PATCH 022/109] Fix SLLI instruction --- insns/InsnSlli.py | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/insns/InsnSlli.py b/insns/InsnSlli.py index 0292cfa..f292ce8 100644 --- a/insns/InsnSlli.py +++ b/insns/InsnSlli.py @@ -1,5 +1,9 @@ from InsnRV32IITypeShift import * +""" +SLLI instruction +""" + class InsnSlli(InsnRV32IITypeShift): def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b000000, 0b001) -- 2.44.1 From 9740470c47d05f786d230f91da8a9744e645df2e Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Mon, 10 Aug 2020 12:35:49 +0800 Subject: [PATCH 023/109] Add SRLI instruction --- insns/InsnSrli.py | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 insns/InsnSrli.py diff --git a/insns/InsnSrli.py b/insns/InsnSrli.py new file mode 100644 index 0000000..cb678ba --- /dev/null +++ b/insns/InsnSrli.py @@ -0,0 +1,15 @@ +from InsnRV32IITypeShift import * + +""" +SRLI instruction +""" + +class InsnSrli(InsnRV32IITypeShift): + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b000000, 0b101) + def elaborate(self, platform): + m = super().elaborate(platform) + + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_rs1_rdata >> self.insn_shamt, 0)) + + return m -- 2.44.1 From 20a500157b90cc8beb200d2997234ff8615b3b40 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Mon, 10 Aug 2020 12:46:09 +0800 Subject: [PATCH 024/109] Add attribution to SO in InsnSra.py --- insns/InsnSra.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/insns/InsnSra.py b/insns/InsnSra.py index 0b1f133..28dde78 100644 --- a/insns/InsnSra.py +++ b/insns/InsnSra.py @@ -10,6 +10,6 @@ class InsnSra(InsnRV32IRType): def elaborate(self, platform): m = super().elaborate(platform) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, (Value.as_signed(self.rvfi_rs1_rdata) >> Mux(self.RISCV_FORMAL_XLEN == 64, self.rvfi_rs2_rdata[:6], self.rvfi_rs2_rdata[:5])) | (-(Value.as_signed(self.rvfi_rs1_rdata) < 0) << (self.RISCV_FORMAL_XLEN - Mux(self.RISCV_FORMAL_XLEN == 64, self.rvfi_rs2_rdata[:6], self.rvfi_rs2_rdata[:5]))), 0)) + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, (Value.as_signed(self.rvfi_rs1_rdata) >> Mux(self.RISCV_FORMAL_XLEN == 64, self.rvfi_rs2_rdata[:6], self.rvfi_rs2_rdata[:5])) | (-(Value.as_signed(self.rvfi_rs1_rdata) < 0) << (self.RISCV_FORMAL_XLEN - Mux(self.RISCV_FORMAL_XLEN == 64, self.rvfi_rs2_rdata[:6], self.rvfi_rs2_rdata[:5]))), 0)) # https://stackoverflow.com/a/25207042 return m -- 2.44.1 From 475c1d9fc2b97b5a09040b713338070eeba02b6a Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Mon, 10 Aug 2020 12:56:19 +0800 Subject: [PATCH 025/109] Add SRAI instruction --- insns/InsnSrai.py | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 insns/InsnSrai.py diff --git a/insns/InsnSrai.py b/insns/InsnSrai.py new file mode 100644 index 0000000..d95dbc8 --- /dev/null +++ b/insns/InsnSrai.py @@ -0,0 +1,15 @@ +from InsnRV32IITypeShift import * + +""" +SRAI instruction +""" + +class InsnSrai(InsnRV32IITypeShift): + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b010000, 0b101) + def elaborate(self, platform): + m = super().elaborate(platform) + + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, (Value.as_signed(self.rvfi_rs1_rdata) >> self.insn_shamt) | (-(Value.as_signed(self.rvfi_rs1_rdata) < 0) << (self.RISCV_FORMAL_XLEN - self.insn_shamt)), 0)) + + return m -- 2.44.1 From ff977c0e50286cc6a65e27642428e3aa9d980044 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Mon, 10 Aug 2020 12:59:00 +0800 Subject: [PATCH 026/109] Update README.md --- insns/README.md | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/insns/README.md b/insns/README.md index 37bae7a..b8f5eae 100644 --- a/insns/README.md +++ b/insns/README.md @@ -46,6 +46,10 @@ _Note: This section is under development and will be updated as more classes are - `InsnSra`: SRA instruction - `InsnOr`: OR instruction - `InsnAnd`: AND instruction + - `InsnRV32IITypeShift`: RV32I I-Type Instruction (Shift Variation) + - `InsnSlli`: SLLI instruction + - `InsnSrli`: SRLI instruction + - `InsnSrai`: SRAI instruction ## Parameters -- 2.44.1 From e97a86bfbec8c5af864750a55ef03106a2875d08 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Mon, 10 Aug 2020 13:32:04 +0800 Subject: [PATCH 027/109] Add (generic) RV32I I-Type Instruction --- insns/InsnRV32IIType.py | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 insns/InsnRV32IIType.py diff --git a/insns/InsnRV32IIType.py b/insns/InsnRV32IIType.py new file mode 100644 index 0000000..89d3517 --- /dev/null +++ b/insns/InsnRV32IIType.py @@ -0,0 +1,13 @@ +from Insn import * + +""" +RV32I I-Type Instruction +""" + +class InsnRV32IIType(Insn): + def elaborate(self, platform): + m = super().elaborate(platform) + + m.d.comb += self.insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32])) + + return m -- 2.44.1 From 1cae183569aa18238800351a2de1b762bc2eca4f Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Mon, 10 Aug 2020 14:13:25 +0800 Subject: [PATCH 028/109] Add JALR instruction --- insns/InsnJalr.py | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 insns/InsnJalr.py diff --git a/insns/InsnJalr.py b/insns/InsnJalr.py new file mode 100644 index 0000000..71b1073 --- /dev/null +++ b/insns/InsnJalr.py @@ -0,0 +1,31 @@ +from InsnRV32IIType import * + +""" +JALR instruction +""" + +class InsnJalr(InsnRV32IIType): + def elaborate(self, platform): + m = super().elaborate(platform) + + if self.RISCV_FORMAL_CSR_MISA: + m.d.comb += self.misa_ok.eq((self.rvfi_csr_misa_rdata & 0) == 0) + m.d.comb += self.spec_csr_misa_rmask.eq(4) + m.d.comb += self.ialign16.eq((self.rvfi_csr_misa_rdata & 4) != 0) + else: + m.d.comb += self.misa_ok.eq(1) + if self.RISCV_FORMAL_COMPRESSED: + m.d.comb += self.ialign16.eq(1) + else: + m.d.comb += self.ialign16.eq(0) + + next_pc = Signal(self.RISCV_FORMAL_XLEN) + m.d.comb += next_pc.eq((self.rvfi_rs1_rdata + self.insn_imm) & ~1) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b000) & (self.insn_opcode == 0b1100111)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_pc_rdata + 4, 0)) + m.d.comb += self.spec_pc_wdata.eq(next_pc) + m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) + + return m -- 2.44.1 From 10296cbf3be87e6c3d9ea6ff83065d34e7a66f48 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Mon, 10 Aug 2020 14:14:40 +0800 Subject: [PATCH 029/109] Update README --- insns/README.md | 2 ++ 1 file changed, 2 insertions(+) diff --git a/insns/README.md b/insns/README.md index b8f5eae..d5a2cd4 100644 --- a/insns/README.md +++ b/insns/README.md @@ -50,6 +50,8 @@ _Note: This section is under development and will be updated as more classes are - `InsnSlli`: SLLI instruction - `InsnSrli`: SRLI instruction - `InsnSrai`: SRAI instruction + - `InsnRV32IIType`: RV32I I-Type Instruction + - `InsnJalr`: JALR instruction ## Parameters -- 2.44.1 From bfd8f670c257eae3237ce9bc725a3768130cbb92 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Mon, 10 Aug 2020 16:16:30 +0800 Subject: [PATCH 030/109] Add RV32I I-Type Instruction (Load Variation) --- insns/InsnRV32IITypeLoad.py | 48 +++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 insns/InsnRV32IITypeLoad.py diff --git a/insns/InsnRV32IITypeLoad.py b/insns/InsnRV32IITypeLoad.py new file mode 100644 index 0000000..9bc6e6b --- /dev/null +++ b/insns/InsnRV32IITypeLoad.py @@ -0,0 +1,48 @@ +from InsnRV32IIType import * + +""" +RV32I I-Type Instruction (Load Variation) +""" + +class InsnRV32IITypeLoad(InsnRV32IIType): + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, RISCV_FORMAL_ALIGNED_MEM, funct3, mask_shift, is_signed): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED) + self.RISCV_FORMAL_ALIGNED_MEM = RISCV_FORMAL_ALIGNED_MEM + self.funct3 = funct3 + self.mask_shift = mask_shift + self.is_signed = is_signed + self.addr = Signal(self.RISCV_FORMAL_XLEN) + self.result = Signal(8 * self.mask_shift) + def elaborate(self, platform): + m = super().elaborate(platform) + + if self.RISCV_FORMAL_CSR_MISA: + m.d.comb += self.misa_ok.eq((self.rvfi_csr_misa_rdata & 0) == 0) + m.d.comb += self.spec_csr_misa_rmask.eq(0) + else: + m.d.comb += self.misa_ok.eq(1) + + if self.RISCV_FORMAL_ALIGNED_MEM: + m.d.comb += self.addr.eq(self.rvfi_rs1_rdata + self.insn_imm) + m.d.comb += self.result.eq(self.rvfi_mem_rdata >> (8 * (self.addr - self.spec_mem_addr))) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == self.funct3) & (self.insn_opcode == 0b0000011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) + m.d.comb += self.spec_mem_addr.eq(self.addr & ~(int(self.RISCV_FORMAL_XLEN // 8) - 1)) + m.d.comb += self.spec_mem_rmask.eq(((1 << self.mask_shift) - 1) << (self.addr - self.spec_mem_addr)) + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, Value.as_signed(result) if self.is_signed else result, 0)) + m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) + m.d.comb += self.spec_trap.eq(((self.addr & (self.mask_shift - 1)) != 0) | ~self.misa_ok) + else: + m.d.comb += self.addr.eq(self.rvfi_rs1_rdata + self.insn_imm) + m.d.comb += self.result.eq(self.rvfi_mem_rdata) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (self.insn_funct3 == self.funct3) & (self.insn_opcode == 0b0000011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) + m.d.comb += self.spec_mem_addr.eq(self.addr) + m.d.comb += self.spec_mem_rmask.eq((1 << self.mask_shift) - 1) + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, Value.as_signed(self.result) if self.is_signed else self.result, 0)) + m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) + m.d.comb += self.spec_trap.eq(~self.misa_ok) + + return m -- 2.44.1 From 167d654be8043ba722391efc7977da7579ef4601 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Mon, 10 Aug 2020 16:26:29 +0800 Subject: [PATCH 031/109] Add LB instruction --- insns/InsnLb.py | 9 +++++++++ 1 file changed, 9 insertions(+) create mode 100644 insns/InsnLb.py diff --git a/insns/InsnLb.py b/insns/InsnLb.py new file mode 100644 index 0000000..5ee2353 --- /dev/null +++ b/insns/InsnLb.py @@ -0,0 +1,9 @@ +from InsnRV32IITypeLoad import * + +""" +LB instruction +""" + +class InsnLb(InsnRV32IITypeLoad): + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, RISCV_FORMAL_ALIGNED_MEM): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, RISCV_FORMAL_ALIGNED_MEM, 0b000, 1, True) -- 2.44.1 From c88cf830fc8b23c24d5589a21309bf3e62273f46 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Mon, 10 Aug 2020 16:29:42 +0800 Subject: [PATCH 032/109] Add LH instruction --- insns/InsnLh.py | 9 +++++++++ 1 file changed, 9 insertions(+) create mode 100644 insns/InsnLh.py diff --git a/insns/InsnLh.py b/insns/InsnLh.py new file mode 100644 index 0000000..b69fac2 --- /dev/null +++ b/insns/InsnLh.py @@ -0,0 +1,9 @@ +from InsnRV32IITypeLoad import * + +""" +LH instruction +""" + +class InsnLh(InsnRV32IITypeLoad): + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, RISCV_FORMAL_ALIGNED_MEM): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, RISCV_FORMAL_ALIGNED_MEM, 0b001, 2, True) -- 2.44.1 From 7b440f0fa931f2b284e81d60f8b5efe2d3c02790 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Mon, 10 Aug 2020 16:35:37 +0800 Subject: [PATCH 033/109] Add LW instruction --- insns/InsnLw.py | 9 +++++++++ insns/InsnRV32IITypeLoad.py | 2 +- 2 files changed, 10 insertions(+), 1 deletion(-) create mode 100644 insns/InsnLw.py diff --git a/insns/InsnLw.py b/insns/InsnLw.py new file mode 100644 index 0000000..c4e9e6d --- /dev/null +++ b/insns/InsnLw.py @@ -0,0 +1,9 @@ +from InsnRV32IITypeLoad import * + +""" +LW instruction +""" + +class InsnLw(InsnRV32IITypeLoad): + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, RISCV_FORMAL_ALIGNED_MEM): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, RISCV_FORMAL_ALIGNED_MEM, 0b010, 4, True) diff --git a/insns/InsnRV32IITypeLoad.py b/insns/InsnRV32IITypeLoad.py index 9bc6e6b..8dba77c 100644 --- a/insns/InsnRV32IITypeLoad.py +++ b/insns/InsnRV32IITypeLoad.py @@ -30,7 +30,7 @@ class InsnRV32IITypeLoad(InsnRV32IIType): m.d.comb += self.spec_rd_addr.eq(self.insn_rd) m.d.comb += self.spec_mem_addr.eq(self.addr & ~(int(self.RISCV_FORMAL_XLEN // 8) - 1)) m.d.comb += self.spec_mem_rmask.eq(((1 << self.mask_shift) - 1) << (self.addr - self.spec_mem_addr)) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, Value.as_signed(result) if self.is_signed else result, 0)) + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, Value.as_signed(self.result) if self.is_signed else self.result, 0)) m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) m.d.comb += self.spec_trap.eq(((self.addr & (self.mask_shift - 1)) != 0) | ~self.misa_ok) else: -- 2.44.1 From 462e526e71c01919a249b55458cb18ee56da34d9 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Mon, 10 Aug 2020 16:40:45 +0800 Subject: [PATCH 034/109] Add LBU instruction --- insns/InsnLbu.py | 9 +++++++++ 1 file changed, 9 insertions(+) create mode 100644 insns/InsnLbu.py diff --git a/insns/InsnLbu.py b/insns/InsnLbu.py new file mode 100644 index 0000000..7ff15c0 --- /dev/null +++ b/insns/InsnLbu.py @@ -0,0 +1,9 @@ +from InsnRV32IITypeLoad import * + +""" +LBU instruction +""" + +class InsnLbu(InsnRV32IITypeLoad): + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, RISCV_FORMAL_ALIGNED_MEM): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, RISCV_FORMAL_ALIGNED_MEM, 0b100, 1, False) -- 2.44.1 From 42b8e5c245120ff1cf6cc85b06eeac4575e6c4c6 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Mon, 10 Aug 2020 16:44:08 +0800 Subject: [PATCH 035/109] Add LHU instruction --- insns/InsnLhu.py | 9 +++++++++ 1 file changed, 9 insertions(+) create mode 100644 insns/InsnLhu.py diff --git a/insns/InsnLhu.py b/insns/InsnLhu.py new file mode 100644 index 0000000..6f85978 --- /dev/null +++ b/insns/InsnLhu.py @@ -0,0 +1,9 @@ +from InsnRV32IITypeLoad import * + +""" +LHU instruction +""" + +class InsnLhu(InsnRV32IITypeLoad): + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, RISCV_FORMAL_ALIGNED_MEM): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, RISCV_FORMAL_ALIGNED_MEM, 0b101, 2, False) -- 2.44.1 From d60c71270402c646a97d4a744c1bbc26dd2648bd Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Mon, 10 Aug 2020 16:47:09 +0800 Subject: [PATCH 036/109] Update README.md --- insns/README.md | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/insns/README.md b/insns/README.md index d5a2cd4..3e74d9d 100644 --- a/insns/README.md +++ b/insns/README.md @@ -52,6 +52,12 @@ _Note: This section is under development and will be updated as more classes are - `InsnSrai`: SRAI instruction - `InsnRV32IIType`: RV32I I-Type Instruction - `InsnJalr`: JALR instruction + - `InsnRV32IITypeLoad`: RV32I I-Type Instruction (Load Variation) + - `InsnLb`: LB instruction + - `InsnLh`: LH instruction + - `InsnLw`: LW instruction + - `InsnLbu`: LBU instruction + - `InsnLhu`: LHU instruction ## Parameters -- 2.44.1 From 036f842faaa484985f241b431632e113b3054759 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Mon, 10 Aug 2020 17:12:09 +0800 Subject: [PATCH 037/109] Add RV32I I-Type Instruction (Arithmetic Variation) --- insns/InsnRV32IITypeArith.py | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 insns/InsnRV32IITypeArith.py diff --git a/insns/InsnRV32IITypeArith.py b/insns/InsnRV32IITypeArith.py new file mode 100644 index 0000000..2c78a4b --- /dev/null +++ b/insns/InsnRV32IITypeArith.py @@ -0,0 +1,25 @@ +from InsnRV32IIType import * + +""" +RV32I I-Type Instruction (Arithmetic Variation) +""" + +class InsnRV32IITypeArith(InsnRV32IIType): + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, funct3): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED) + self.funct3 = funct3 + def elaborate(self, platform): + m = super().elaborate(platform) + + if self.RISCV_FORMAL_CSR_MISA: + m.d.comb += self.misa_ok.eq((self.rvfi_csr_misa_rdata & 0) == 0) + m.d.comb += self.spec_csr_misa_rmask.eq(0) + else: + m.d.comb += self.misa_ok.eq(1) + + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == self.funct3) & (self.insn_opcode == 0b0010011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) + m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) + + return m -- 2.44.1 From 0ae11e12b5843903c9c9088f12a733ffd42f7609 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Mon, 10 Aug 2020 17:19:57 +0800 Subject: [PATCH 038/109] Add ADDI instruction --- insns/InsnAddi.py | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 insns/InsnAddi.py diff --git a/insns/InsnAddi.py b/insns/InsnAddi.py new file mode 100644 index 0000000..8c4aa99 --- /dev/null +++ b/insns/InsnAddi.py @@ -0,0 +1,11 @@ +from InsnRV32IITypeArith import * + +class InsnAddi(InsnRV32IITypeArith): + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b000) + def elaborate(self, platform): + m = super().elaborate(platform) + + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_rs1_rdata + self.insn_imm, 0)) + + return m -- 2.44.1 From 84f4b75267eabd02337cfbd4dd52fdd3447208bd Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Mon, 10 Aug 2020 17:24:50 +0800 Subject: [PATCH 039/109] Add SLTI instruction --- insns/InsnAddi.py | 4 ++++ insns/InsnSlti.py | 15 +++++++++++++++ 2 files changed, 19 insertions(+) create mode 100644 insns/InsnSlti.py diff --git a/insns/InsnAddi.py b/insns/InsnAddi.py index 8c4aa99..85abc02 100644 --- a/insns/InsnAddi.py +++ b/insns/InsnAddi.py @@ -1,5 +1,9 @@ from InsnRV32IITypeArith import * +""" +ADDI instruction +""" + class InsnAddi(InsnRV32IITypeArith): def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b000) diff --git a/insns/InsnSlti.py b/insns/InsnSlti.py new file mode 100644 index 0000000..07b4b52 --- /dev/null +++ b/insns/InsnSlti.py @@ -0,0 +1,15 @@ +from InsnRV32IITypeArith import * + +""" +SLTI instruction +""" + +class InsnSlti(InsnRV32IITypeArith): + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b010) + def elaborate(self, platform): + m = super().elaborate(platform) + + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, Value.as_signed(self.rvfi_rs1_rdata) < Value.as_signed(self.insn_imm), 0)) + + return m -- 2.44.1 From 71f8a594a6cbd644706523b2220105ba37342c97 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Mon, 10 Aug 2020 17:29:55 +0800 Subject: [PATCH 040/109] Add SLTIU instruction --- insns/InsnSltiu.py | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 insns/InsnSltiu.py diff --git a/insns/InsnSltiu.py b/insns/InsnSltiu.py new file mode 100644 index 0000000..2bf4d3a --- /dev/null +++ b/insns/InsnSltiu.py @@ -0,0 +1,15 @@ +from InsnRV32IITypeArith import * + +""" +SLTIU instruction +""" + +class InsnSltiu(InsnRV32IITypeArith): + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b011) + def elaborate(self, platform): + m = super().elaborate(platform) + + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_rs1_rdata < self.insn_imm, 0)) + + return m -- 2.44.1 From 4b79b06dba493d712a758f9cc56494e997587f68 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Mon, 10 Aug 2020 17:32:55 +0800 Subject: [PATCH 041/109] Add XORI instruction --- insns/InsnXori.py | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 insns/InsnXori.py diff --git a/insns/InsnXori.py b/insns/InsnXori.py new file mode 100644 index 0000000..c27f195 --- /dev/null +++ b/insns/InsnXori.py @@ -0,0 +1,15 @@ +from InsnRV32IITypeArith import * + +""" +XORI instruction +""" + +class InsnXori(InsnRV32IITypeArith): + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b100) + def elaborate(self, platform): + m = super().elaborate(platform) + + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_rs1_rdata ^ self.insn_imm, 0)) + + return m -- 2.44.1 From c258d541af7fe0f097227e2519d02113399b2a32 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Mon, 10 Aug 2020 17:34:22 +0800 Subject: [PATCH 042/109] Add ORI instruction --- insns/InsnOri.py | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 insns/InsnOri.py diff --git a/insns/InsnOri.py b/insns/InsnOri.py new file mode 100644 index 0000000..67c1b01 --- /dev/null +++ b/insns/InsnOri.py @@ -0,0 +1,15 @@ +from InsnRV32IITypeArith import * + +""" +ORI instruction +""" + +class InsnOri(InsnRV32IITypeArith): + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b110) + def elaborate(self, platform): + m = super().elaborate(platform) + + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_rs1_rdata | self.insn_imm, 0)) + + return m -- 2.44.1 From 31753e36791b46f9db7b664fee06577dcdc7c7b5 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Mon, 10 Aug 2020 17:35:43 +0800 Subject: [PATCH 043/109] Add ANDI instruction --- insns/InsnAndi.py | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 insns/InsnAndi.py diff --git a/insns/InsnAndi.py b/insns/InsnAndi.py new file mode 100644 index 0000000..aa6c054 --- /dev/null +++ b/insns/InsnAndi.py @@ -0,0 +1,15 @@ +from InsnRV32IITypeArith import * + +""" +ANDI instruction +""" + +class InsnAndi(InsnRV32IITypeArith): + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b111) + def elaborate(self, platform): + m = super().elaborate(platform) + + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_rs1_rdata & self.insn_imm, 0)) + + return m -- 2.44.1 From c938eefe4107239c3fc47852071a02d914ca588c Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Mon, 10 Aug 2020 17:37:47 +0800 Subject: [PATCH 044/109] Update README.md --- insns/README.md | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/insns/README.md b/insns/README.md index 3e74d9d..6fbb057 100644 --- a/insns/README.md +++ b/insns/README.md @@ -58,6 +58,13 @@ _Note: This section is under development and will be updated as more classes are - `InsnLw`: LW instruction - `InsnLbu`: LBU instruction - `InsnLhu`: LHU instruction + - `InsnRV32IITypeArith`: RV32I I-Type Instruction (Arithmetic Variation) + - `InsnAddi`: ADDI instruction + - `InsnSlti`: SLTI instruction + - `InsnSltiu`: SLTIU instruction + - `InsnXori`: XORI instruction + - `InsnOri`: ORI instruction + - `InsnAndi`: ANDI instruction ## Parameters -- 2.44.1 From 70c417f92029a30b676a8c48d52efff5e89e1af6 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Tue, 11 Aug 2020 10:08:11 +0800 Subject: [PATCH 045/109] Update README.md --- insns/README.md | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/insns/README.md b/insns/README.md index 6fbb057..5fa0a4d 100644 --- a/insns/README.md +++ b/insns/README.md @@ -1,7 +1,9 @@ -# RISC-V Supported Instructions +# RISC-V Instructions ## Instructions +Below is a table of RISC-V instructions supported by the original riscv-formal framework at the time of writing, categorized by instruction type. + | Instruction type | Instructions | | --- | --- | | R-type | ADD, ADDW, AND, DIV, DIVU, DIVUW, DIVW, MUL, MULH, MULHSU, MULHU, MULW, OR, REM, REMU, REMUW, REMW, SLL, SLLW, SLT, SLTU, SRA, SRAW, SRL, SRLW, SUB, SUBW, XOR | @@ -32,7 +34,7 @@ ## Class Synopsis -_Note: This section is under development and will be updated as more classes are implemented._ +Below is a list of instructions currently supported by this port of the riscv-formal framework and is expected to grow over time. The instructions are roughly grouped by instruction type but sometimes with further specializations - the hierarchy of the lists reflects the hierarchy of inheritance in the classes used to represent various instructions. - `Insn`: General RISC-V instruction - `InsnRV32IRType`: RV32I R-Type Instruction -- 2.44.1 From 0f71c1dad106802865bea370b8a0ec801f4f0693 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Tue, 11 Aug 2020 14:00:04 +0800 Subject: [PATCH 046/109] Add RV32I S-Type Instruction Format --- insns/InsnRV32ISType.py | 46 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 insns/InsnRV32ISType.py diff --git a/insns/InsnRV32ISType.py b/insns/InsnRV32ISType.py new file mode 100644 index 0000000..089173f --- /dev/null +++ b/insns/InsnRV32ISType.py @@ -0,0 +1,46 @@ +from Insn import * + +""" +RV32I S-Type Instruction +""" + +class InsnRV32ISType(Insn): + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, RISCV_FORMAL_ALIGNED_MEM, funct3, mask_shift): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED) + self.RISCV_FORMAL_ALIGNED_MEM = RISCV_FORMAL_ALIGNED_MEM + self.funct3 = funct3 + self.mask_shift = mask_shift + self.addr = Signal(self.RISCV_FORMAL_XLEN) + def elaborate(self, platform): + m = super().elaborate(platform) + + m.d.comb += self.insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[7:12], self.rvfi_insn[25:32]))) + + if self.RISCV_FORMAL_CSR_MISA: + m.d.comb += self.misa_ok.eq((self.rvfi_csr_misa_rdata & 0) == 0) + m.d.comb += self.spec_csr_misa_rmask.eq(0) + else: + m.d.comb += self.misa_ok.eq(1) + + if self.RISCV_FORMAL_ALIGNED_MEM: + m.d.comb += self.addr.eq(self.rvfi_rs1_rdata + self.insn_imm) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == self.funct3) & (self.insn_opcode == 0b0100011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) + m.d.comb += self.spec_mem_addr.eq(self.addr & ~(int(self.RISCV_FORMAL_XLEN // 8) - 1)) + m.d.comb += self.spec_mem_wmask.eq(((1 << self.mask_shift) - 1) << (self.addr - self.spec_mem_addr)) + m.d.comb += self.spec_mem_wdata.eq(self.rvfi_rs2_rdata << (8 * (self.addr - self.spec_mem_addr))) + m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) + m.d.comb += self.spec_trap.eq(((self.addr & (self.mask_shift - 1)) != 0) | ~self.misa_ok) + else: + m.d.comb += self.addr.eq(self.rvfi_rs1_rdata + self.insn_imm) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == self.funct3) & (self.insn_opcode == 0b0100011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) + m.d.comb += self.spec_mem_addr.eq(self.addr) + m.d.comb += self.spec_mem_wmask.eq((1 << self.mask_shift) - 1) + m.d.comb += self.spec_mem_wdata.eq(self.rvfi_rs2_rdata) + m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) + m.d.comb += self.spec_trap.eq(~self.misa_ok) + + return m -- 2.44.1 From c36806031596b464e2eda2cd1b688d10f576ac3c Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Tue, 11 Aug 2020 14:50:04 +0800 Subject: [PATCH 047/109] Add SB instruction --- insns/InsnSb.py | 9 +++++++++ 1 file changed, 9 insertions(+) create mode 100644 insns/InsnSb.py diff --git a/insns/InsnSb.py b/insns/InsnSb.py new file mode 100644 index 0000000..a589d1e --- /dev/null +++ b/insns/InsnSb.py @@ -0,0 +1,9 @@ +from InsnRV32ISType import * + +""" +SB instruction +""" + +class InsnSb(InsnRV32ISType): + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, RISCV_FORMAL_ALIGNED_MEM): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, RISCV_FORMAL_ALIGNED_MEM, 0b000, 1) -- 2.44.1 From ec86b3a76a65c3f90d1ac6b737bdc74b8ffc28e0 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Tue, 11 Aug 2020 14:51:34 +0800 Subject: [PATCH 048/109] Add SH instruction --- insns/InsnSh.py | 9 +++++++++ 1 file changed, 9 insertions(+) create mode 100644 insns/InsnSh.py diff --git a/insns/InsnSh.py b/insns/InsnSh.py new file mode 100644 index 0000000..b02608d --- /dev/null +++ b/insns/InsnSh.py @@ -0,0 +1,9 @@ +from InsnRV32ISType import * + +""" +SH instruction +""" + +class InsnSh(InsnRV32ISType): + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, RISCV_FORMAL_ALIGNED_MEM): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, RISCV_FORMAL_ALIGNED_MEM, 0b001, 2) -- 2.44.1 From a78309d9970739e802c9ac24822694f576ab1ee9 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Tue, 11 Aug 2020 14:52:59 +0800 Subject: [PATCH 049/109] Add SW instruction --- insns/InsnSw.py | 9 +++++++++ 1 file changed, 9 insertions(+) create mode 100644 insns/InsnSw.py diff --git a/insns/InsnSw.py b/insns/InsnSw.py new file mode 100644 index 0000000..904a427 --- /dev/null +++ b/insns/InsnSw.py @@ -0,0 +1,9 @@ +from InsnRV32ISType import * + +""" +SW instruction +""" + +class InshSw(InsnRV32ISType): + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, RISCV_FORMAL_ALIGNED_MEM): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, RISCV_FORMAL_ALIGNED_MEM, 0b010, 4) -- 2.44.1 From 507675b59f2a8f825cb24e5209770f53cc114212 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Tue, 11 Aug 2020 14:54:27 +0800 Subject: [PATCH 050/109] Update README.md --- insns/README.md | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/insns/README.md b/insns/README.md index 5fa0a4d..9e00672 100644 --- a/insns/README.md +++ b/insns/README.md @@ -67,6 +67,10 @@ Below is a list of instructions currently supported by this port of the riscv-fo - `InsnXori`: XORI instruction - `InsnOri`: ORI instruction - `InsnAndi`: ANDI instruction + - `InsnRV32ISType`: RV32I S-Type Instruction + - `InsnSb`: SB instruction + - `InsnSh`: SH instruction + - `InsnSw`: SW instruction ## Parameters -- 2.44.1 From edadb8da476c06fe6057ff8d5b3605d542bedee8 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Tue, 11 Aug 2020 16:37:42 +0800 Subject: [PATCH 051/109] Add RV32I SB-Type Instruction Format --- insns/InsnRV32ISBType.py | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 insns/InsnRV32ISBType.py diff --git a/insns/InsnRV32ISBType.py b/insns/InsnRV32ISBType.py new file mode 100644 index 0000000..dd19387 --- /dev/null +++ b/insns/InsnRV32ISBType.py @@ -0,0 +1,31 @@ +from Insn import * + +""" +RV32I SB-Type Instruction +""" + +class InsnRV32ISBType(Insn): + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, funct3): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED) + self.funct3 = funct3 + def elaborate(self, platform): + m = super().elaborate(platform) + + m.d.comb += self.insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[8:12], self.rvfi_insn[25:31], self.rvfi_insn[7], self.rvfi_insn[31]) << 1)) + + if self.RISCV_FORMAL_CSR_MISA: + m.d.comb += self.misa_ok.eq((self.rvfi_csr_misa_rdata & 0) == 0) + m.d.comb += self.spec_csr_misa_rmask.eq(4) + m.d.comb += self.ialign16.eq((self.rvfi_csr_misa_rdata & 4) != 0) + else: + m.d.comb += self.misa_ok.eq(1) + if self.RISCV_FORMAL_COMPRESSED: + m.d.comb += self.ialign16.eq(1) + else: + m.d.comb += self.ialign16.eq(0) + + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == self.funct3) & (self.insn_opcode == 0b1100011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) + + return m -- 2.44.1 From 6461f455d636d44d2c26aa5debb69cf800bb5047 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Tue, 11 Aug 2020 16:46:07 +0800 Subject: [PATCH 052/109] Add BEQ instruction --- insns/InsnBeq.py | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 insns/InsnBeq.py diff --git a/insns/InsnBeq.py b/insns/InsnBeq.py new file mode 100644 index 0000000..cb1f2bd --- /dev/null +++ b/insns/InsnBeq.py @@ -0,0 +1,18 @@ +from InsnRV32ISBType import * + +""" +BEQ instruction +""" + +class InsnBeq(InsnRV32ISBType): + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b000) + def elaborate(self, platform): + m = super().elaborate(platform) + + next_pc = Signal(self.RISCV_FORMAL_XLEN) + m.d.comb += next_pc.eq(Mux(self.rvfi_rs1_rdata == self.rvfi_rs2_rdata, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4)) + m.d.comb += self.spec_pc_wdata.eq(next_pc) + m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) + + return m -- 2.44.1 From 1cff0134fe12a700083ab1bbd0b681124c212a9b Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Tue, 11 Aug 2020 16:49:25 +0800 Subject: [PATCH 053/109] Add BNE instruction --- insns/InsnBne.py | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 insns/InsnBne.py diff --git a/insns/InsnBne.py b/insns/InsnBne.py new file mode 100644 index 0000000..415adfd --- /dev/null +++ b/insns/InsnBne.py @@ -0,0 +1,18 @@ +from InsnRV32ISBType import * + +""" +BNE instruction +""" + +class InsnBne(InsnRV32ISBType): + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b001) + def elaborate(self, platform): + m = super().elaborate(platform) + + next_pc = Signal(self.RISCV_FORMAL_XLEN) + m.d.comb += next_pc.eq(Mux(self.rvfi_rs1_rdata != self.rvfi_rs2_rdata, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4)) + m.d.comb += self.spec_pc_wdata.eq(next_pc) + m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) + + return m -- 2.44.1 From 17816f946467aaae18c99c4f2c3739937b2d2786 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Tue, 11 Aug 2020 16:52:34 +0800 Subject: [PATCH 054/109] Add BLT instruction --- insns/InsnBlt.py | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 insns/InsnBlt.py diff --git a/insns/InsnBlt.py b/insns/InsnBlt.py new file mode 100644 index 0000000..ade2f47 --- /dev/null +++ b/insns/InsnBlt.py @@ -0,0 +1,18 @@ +from InsnRV32ISBType import * + +""" +BLT instruction +""" + +class InsnBlt(InsnRV32ISBType): + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b100) + def elaborate(self, platform): + m = super().elaborate(platform) + + next_pc = Signal(self.RISCV_FORMAL_XLEN) + m.d.comb += next_pc.eq(Mux(Value.as_signed(self.rvfi_rs1_rdata) < Value.as_signed(self.rvfi_rs2_rdata), self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4)) + m.d.comb += self.spec_pc_wdata.eq(next_pc) + m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) + + return m -- 2.44.1 From c82dcfb570ef734418160ea96892196a3f5033d8 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Tue, 11 Aug 2020 16:54:16 +0800 Subject: [PATCH 055/109] Add BGE instruction --- insns/InsnBge.py | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 insns/InsnBge.py diff --git a/insns/InsnBge.py b/insns/InsnBge.py new file mode 100644 index 0000000..2158e79 --- /dev/null +++ b/insns/InsnBge.py @@ -0,0 +1,18 @@ +from InsnRV32ISBType import * + +""" +BGE instruction +""" + +class InsnBge(InsnRV32ISBType): + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b101) + def elaborate(self, platform): + m = super().elaborate(platform) + + next_pc = Signal(self.RISCV_FORMAL_XLEN) + m.d.comb += next_pc.eq(Mux(Value.as_signed(self.rvfi_rs1_rdata) >= Value.as_signed(self.rvfi_rs2_rdata), self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4)) + m.d.comb += self.spec_pc_wdata.eq(next_pc) + m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) + + return m -- 2.44.1 From 504d6e1984cb1c08bccef5a471903899084ade35 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Tue, 11 Aug 2020 16:55:58 +0800 Subject: [PATCH 056/109] Add BLTU instruction --- insns/InsnBltu.py | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 insns/InsnBltu.py diff --git a/insns/InsnBltu.py b/insns/InsnBltu.py new file mode 100644 index 0000000..fb39c75 --- /dev/null +++ b/insns/InsnBltu.py @@ -0,0 +1,18 @@ +from InsnRV32ISBType import * + +""" +BLTU instruction +""" + +class InsnBltu(InsnRV32ISBType): + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b110) + def elaborate(self, platform): + m = super().elaborate(platform) + + next_pc = Signal(self.RISCV_FORMAL_XLEN) + m.d.comb += next_pc.eq(Mux(self.rvfi_rs1_rdata < self.rvfi_rs2_rdata, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4)) + m.d.comb += self.spec_pc_wdata.eq(next_pc) + m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) + + return m -- 2.44.1 From a515938780d43074f75d38e9590113a66d62f83b Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Tue, 11 Aug 2020 16:57:34 +0800 Subject: [PATCH 057/109] Add BGEU instruction --- insns/InsnBgeu.py | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 insns/InsnBgeu.py diff --git a/insns/InsnBgeu.py b/insns/InsnBgeu.py new file mode 100644 index 0000000..5f1341e --- /dev/null +++ b/insns/InsnBgeu.py @@ -0,0 +1,18 @@ +from InsnRV32ISBType import * + +""" +BGEU instruction +""" + +class InsnBgeu(InsnRV32ISBType): + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b111) + def elaborate(self, platform): + m = super().elaborate(platform) + + next_pc = Signal(self.RISCV_FORMAL_XLEN) + m.d.comb += next_pc.eq(Mux(self.rvfi_rs1_rdata >= self.rvfi_rs2_rdata, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4)) + m.d.comb += self.spec_pc_wdata.eq(next_pc) + m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) + + return m -- 2.44.1 From 2ab62a6f79a3f1d824c6956fba6736eaa240a02c Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Tue, 11 Aug 2020 16:59:02 +0800 Subject: [PATCH 058/109] Update README.md --- insns/README.md | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/insns/README.md b/insns/README.md index 9e00672..a61b02f 100644 --- a/insns/README.md +++ b/insns/README.md @@ -71,6 +71,13 @@ Below is a list of instructions currently supported by this port of the riscv-fo - `InsnSb`: SB instruction - `InsnSh`: SH instruction - `InsnSw`: SW instruction + - `InsnRV32ISBType`: RV32I SB-Type Instruction + - `InsnBeq`: BEQ instruction + - `InsnBne`: BNE instruction + - `InsnBlt`: BLT instruction + - `InsnBge`: BGE instruction + - `InsnBltu`: BLTU instruction + - `InsnBgeu`: BGEU instruction ## Parameters -- 2.44.1 From bae0f5e7bc49ddd16a36c197c826624666861bf8 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Tue, 11 Aug 2020 17:11:40 +0800 Subject: [PATCH 059/109] Add JAL instruction --- insns/InsnJal.py | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 insns/InsnJal.py diff --git a/insns/InsnJal.py b/insns/InsnJal.py new file mode 100644 index 0000000..68ed094 --- /dev/null +++ b/insns/InsnJal.py @@ -0,0 +1,32 @@ +from Insn import * + +""" +JAL instruction +""" + +class InsnJal(Insn): + def elaborate(self, platform): + m = super().elaborate(platform) + + m.d.comb += self.insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[21:31], self.rvfi_insn[20], self.rvfi_insn[12:20], self.rvfi_insn[31]) << 1)) + + if self.RISCV_FORMAL_CSR_MISA: + m.d.comb += self.misa_ok.eq((self.rvfi_csr_misa_rdata & 0) == 0) + m.d.comb += self.spec_csr_misa_rmask.eq(4) + m.d.comb += self.ialign16.eq((self.rvfi_csr_misa_rdata & 4) != 0) + else: + m.d.comb += self.misa_ok.eq(1) + if self.RISCV_FORMAL_COMPRESSED: + m.d.comb += self.ialign16.eq(1) + else: + m.d.comb += self.ialign16.eq(0) + + next_pc = Signal(self.RISCV_FORMAL_XLEN) + m.d.comb += next_pc.eq(self.rvfi_rs1_rdata + self.insn_imm) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_opcode == 0b1101111)) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_pc_rdata + 4, 0)) + m.d.comb += self.spec_pc_wdata.eq(next_pc) + m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) + + return m -- 2.44.1 From 32526017d050e5d9924da32b5244dbee4533fd53 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Tue, 11 Aug 2020 17:12:27 +0800 Subject: [PATCH 060/109] Update README.md --- insns/README.md | 1 + 1 file changed, 1 insertion(+) diff --git a/insns/README.md b/insns/README.md index a61b02f..8e1d631 100644 --- a/insns/README.md +++ b/insns/README.md @@ -78,6 +78,7 @@ Below is a list of instructions currently supported by this port of the riscv-fo - `InsnBge`: BGE instruction - `InsnBltu`: BLTU instruction - `InsnBgeu`: BGEU instruction + - `InsnJal`: JAL instruction ## Parameters -- 2.44.1 From 371fcc81c11993625bd75f4cf28583f765ef21e3 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Tue, 11 Aug 2020 17:25:57 +0800 Subject: [PATCH 061/109] Add RV32I U-Type Instruction Format --- insns/InsnRV32IUType.py | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 insns/InsnRV32IUType.py diff --git a/insns/InsnRV32IUType.py b/insns/InsnRV32IUType.py new file mode 100644 index 0000000..4016206 --- /dev/null +++ b/insns/InsnRV32IUType.py @@ -0,0 +1,26 @@ +from Insn import * + +""" +RV32I U-Type Instruction +""" + +class InsnRV32IUType(Insn): + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, opcode): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED) + self.opcode = opcode + def elaborate(self, platform): + m = super().elaborate(platform) + + m.d.comb += self.insn_imm.eq(Value.as_signed(self.rvfi_insn[12:32] << 12)) + + if self.RISCV_FORMAL_CSR_MISA: + m.d.comb += self.misa_ok.eq((self.rvfi_csr_misa_rdata & 0) == 0) + m.d.comb += self.spec_csr_misa_rmask.eq(0) + else: + m.d.comb += self.misa_ok.eq(1) + + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_opcode == self.opcode)) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) + m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) + + return m -- 2.44.1 From 35b515e53b3294d4bbbc6cf373a993a08d3a0cb6 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Tue, 11 Aug 2020 17:30:47 +0800 Subject: [PATCH 062/109] Add LUI instruction --- insns/InsnLui.py | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 insns/InsnLui.py diff --git a/insns/InsnLui.py b/insns/InsnLui.py new file mode 100644 index 0000000..fa8ec49 --- /dev/null +++ b/insns/InsnLui.py @@ -0,0 +1,15 @@ +from InsnRV32IUType import * + +""" +LUI instruction +""" + +class InsnLui(InsnRV32IUType): + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0110111) + def elaborate(self, platform): + m = super().elaborate(platform) + + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.insn_imm, 0)) + + return m -- 2.44.1 From 28ed0c8656cf2953050187557ccd8da3e8233cda Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Tue, 11 Aug 2020 17:32:56 +0800 Subject: [PATCH 063/109] Add AUIPC instruction --- insns/InsnAuipc.py | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 insns/InsnAuipc.py diff --git a/insns/InsnAuipc.py b/insns/InsnAuipc.py new file mode 100644 index 0000000..3760264 --- /dev/null +++ b/insns/InsnAuipc.py @@ -0,0 +1,15 @@ +from InsnRV32IUType import * + +""" +AUIPC instruction +""" + +class InsnAuipc(InsnRV32IUType): + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0010111) + def elaborate(self, platform): + m = super().elaborate(platform) + + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_pc_rdata + self.insn_imm, 0)) + + return m -- 2.44.1 From eb5650172779eb1e53f8fabc2f67aee693b6a4e3 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Tue, 11 Aug 2020 17:33:50 +0800 Subject: [PATCH 064/109] Update README.md --- insns/README.md | 3 +++ 1 file changed, 3 insertions(+) diff --git a/insns/README.md b/insns/README.md index 8e1d631..7f2d35f 100644 --- a/insns/README.md +++ b/insns/README.md @@ -79,6 +79,9 @@ Below is a list of instructions currently supported by this port of the riscv-fo - `InsnBltu`: BLTU instruction - `InsnBgeu`: BGEU instruction - `InsnJal`: JAL instruction + - `InsnRV32IUType`: RV32I U-Type Instruction + - `InsnLui`: LUI instruction + - `InsnAuipc`: AUIPC instruction ## Parameters -- 2.44.1 From 186c8659dbd68d50c2e4e382bece73ae55d85789 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Wed, 12 Aug 2020 13:16:37 +0800 Subject: [PATCH 065/109] Remove redundant parameter in Insn constructor --- insns/Insn.py | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/insns/Insn.py b/insns/Insn.py index 72dc7a0..b3fbc3e 100644 --- a/insns/Insn.py +++ b/insns/Insn.py @@ -6,12 +6,11 @@ Class for generic RISC-V instructions """ class Insn(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA): # Core-specific constants self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN self.RISCV_FORMAL_CSR_MISA = RISCV_FORMAL_CSR_MISA - self.RISCV_FORMAL_COMPRESSED = RISCV_FORMAL_COMPRESSED # RVFI input ports self.rvfi_valid = Signal(1) -- 2.44.1 From 3f6021bbb63e571ddc251035385a7c718b2ad764 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Wed, 12 Aug 2020 13:19:13 +0800 Subject: [PATCH 066/109] Remove redundant parameter in InsRV32IRType constructor --- insns/InsnRV32IRType.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/insns/InsnRV32IRType.py b/insns/InsnRV32IRType.py index c14dabd..dcd510b 100644 --- a/insns/InsnRV32IRType.py +++ b/insns/InsnRV32IRType.py @@ -5,8 +5,8 @@ RV32I R-Type Instruction """ class InsnRV32IRType(Insn): - def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, funct7, funct3, opcode): - super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED) + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, funct7, funct3, opcode): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA) self.funct7 = funct7 self.funct3 = funct3 self.opcode = opcode -- 2.44.1 From 8483e2b318bba14acbb4858d6150cfbbcad4321e Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Wed, 12 Aug 2020 13:20:46 +0800 Subject: [PATCH 067/109] Remove redundant parameter in InnAdd constructor --- insns/InsnAdd.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/insns/InsnAdd.py b/insns/InsnAdd.py index d495fe0..c3efd9e 100644 --- a/insns/InsnAdd.py +++ b/insns/InsnAdd.py @@ -5,8 +5,8 @@ ADD instruction """ class InsnAdd(InsnRV32IRType): - def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): - super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b000, 0b0110011) + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b0000000, 0b000, 0b0110011) def elaborate(self, platform): m = super().elaborate(platform) -- 2.44.1 From 4a8197e1f9c38e777b05537f840397befb9db578 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Wed, 12 Aug 2020 13:22:33 +0800 Subject: [PATCH 068/109] Remove redundant parameter in IsnnSub constructor --- insns/InsnSub.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/insns/InsnSub.py b/insns/InsnSub.py index b5435d8..dc1212e 100644 --- a/insns/InsnSub.py +++ b/insns/InsnSub.py @@ -5,8 +5,8 @@ SUB instruction """ class InsnSub(InsnRV32IRType): - def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): - super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0100000, 0b000, 0b0110011) + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b0100000, 0b000, 0b0110011) def elaborate(self, platform): m = super().elaborate(platform) -- 2.44.1 From 83b36c23b32d70cdd15f8cf9df3832fbed7ea745 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Wed, 12 Aug 2020 13:24:24 +0800 Subject: [PATCH 069/109] Remove redundant parameter from InsnSll constructor --- insns/InsnSll.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/insns/InsnSll.py b/insns/InsnSll.py index 5b55dbf..e559e6a 100644 --- a/insns/InsnSll.py +++ b/insns/InsnSll.py @@ -5,8 +5,8 @@ SLL instruction """ class InsnSll(InsnRV32IRType): - def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): - super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b001, 0b0110011) + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b0000000, 0b001, 0b0110011) def elaborate(self, platform): m = super().elaborate(platform) -- 2.44.1 From 6bbf227aaf7babfca494f2b81cafb701d4dcdedf Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Wed, 12 Aug 2020 13:25:40 +0800 Subject: [PATCH 070/109] Remove redundant parameter in InsnSlt construcotr --- insns/InsnSlt.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/insns/InsnSlt.py b/insns/InsnSlt.py index 89807ea..7aa260d 100644 --- a/insns/InsnSlt.py +++ b/insns/InsnSlt.py @@ -5,8 +5,8 @@ SLT instruction """ class InsnSlt(InsnRV32IRType): - def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): - super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b010, 0b0110011) + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b0000000, 0b010, 0b0110011) def elaborate(self, platform): m = super().elaborate(platform) -- 2.44.1 From eddc863a29b7e389ddddde82b55f01ad0993fc84 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Wed, 12 Aug 2020 13:26:32 +0800 Subject: [PATCH 071/109] Remove redundant parameter in InsnSltu constructor --- insns/InsnSltu.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/insns/InsnSltu.py b/insns/InsnSltu.py index ff9f3ec..0361ac6 100644 --- a/insns/InsnSltu.py +++ b/insns/InsnSltu.py @@ -5,8 +5,8 @@ SLTU instruction """ class InsnSltu(InsnRV32IRType): - def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): - super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b011, 0b0110011) + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b0000000, 0b011, 0b0110011) def elaborate(self, platform): m = super().elaborate(platform) -- 2.44.1 From 96acab72d78dd77bed34b8c7fd981fba7e5151da Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Wed, 12 Aug 2020 13:27:29 +0800 Subject: [PATCH 072/109] Remove redundant parameter in InsnXor constructor --- insns/InsnXor.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/insns/InsnXor.py b/insns/InsnXor.py index 0569fa7..c7a23d8 100644 --- a/insns/InsnXor.py +++ b/insns/InsnXor.py @@ -5,8 +5,8 @@ XOR instruction """ class InsnXor(InsnRV32IRType): - def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): - super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b100, 0b0110011) + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b0000000, 0b100, 0b0110011) def elaborate(self, platform): m = super().elaborate(platform) -- 2.44.1 From 92fdabad321ba72f8d55b5f648f57ee4e233ce54 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Wed, 12 Aug 2020 13:28:30 +0800 Subject: [PATCH 073/109] Remove redundant parameter in InsnSrl constructor --- insns/InsnSrl.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/insns/InsnSrl.py b/insns/InsnSrl.py index f68164c..dbe462b 100644 --- a/insns/InsnSrl.py +++ b/insns/InsnSrl.py @@ -5,8 +5,8 @@ SRL instruction """ class InsnSrl(InsnRV32IRType): - def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): - super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b100, 0b0110011) + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b0000000, 0b100, 0b0110011) def elaborate(self, platform): m = super().elaborate(platform) -- 2.44.1 From 72aeb3cf360f3d802926ea49d3fddb59345865d5 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Wed, 12 Aug 2020 13:29:21 +0800 Subject: [PATCH 074/109] Remove redundant parameter in InsnSra constructor --- insns/InsnSra.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/insns/InsnSra.py b/insns/InsnSra.py index 28dde78..afa8c3c 100644 --- a/insns/InsnSra.py +++ b/insns/InsnSra.py @@ -5,8 +5,8 @@ SRA instruction """ class InsnSra(InsnRV32IRType): - def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): - super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0100000, 0b101, 0b0110011) + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b0100000, 0b101, 0b0110011) def elaborate(self, platform): m = super().elaborate(platform) -- 2.44.1 From 96fdc5a455967a9370ed124dfe8389b1bae9af5f Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Wed, 12 Aug 2020 13:30:12 +0800 Subject: [PATCH 075/109] Remove redundant parameter in InsnOr constructor --- insns/InsnOr.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/insns/InsnOr.py b/insns/InsnOr.py index ed832a0..e1bf586 100644 --- a/insns/InsnOr.py +++ b/insns/InsnOr.py @@ -5,8 +5,8 @@ OR instruction """ class InsnOr(InsnRV32IRType): - def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): - super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b110, 0b0110011) + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b0000000, 0b110, 0b0110011) def elaborate(self, platform): m = super().elaborate(platform) -- 2.44.1 From f40f5e35e0ecb87544c10a4c9938a81c9d015c72 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Wed, 12 Aug 2020 13:31:12 +0800 Subject: [PATCH 076/109] Remove redundant parameter in InsnAdd constructor --- insns/InsnAnd.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/insns/InsnAnd.py b/insns/InsnAnd.py index b874914..a71390a 100644 --- a/insns/InsnAnd.py +++ b/insns/InsnAnd.py @@ -5,8 +5,8 @@ AND instruction """ class InsnAnd(InsnRV32IRType): - def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): - super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b111, 0b0110011) + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b0000000, 0b111, 0b0110011) def elaborate(self, platform): m = super().elaborate(platform) -- 2.44.1 From 05aafd7f22b2b5b9de34636f85f29e25bfc5ebf8 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Wed, 12 Aug 2020 13:35:26 +0800 Subject: [PATCH 077/109] Remove redundant parameter in InsnRV32IITypeShift constructor --- insns/InsnRV32IITypeShift.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/insns/InsnRV32IITypeShift.py b/insns/InsnRV32IITypeShift.py index 62f6403..1b7f872 100644 --- a/insns/InsnRV32IITypeShift.py +++ b/insns/InsnRV32IITypeShift.py @@ -5,8 +5,8 @@ RV32I I-Type Instruction (Shift Variation) """ class InsnRV32IITypeShift(Insn): - def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, funct6, funct3): - super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED) + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, funct6, funct3): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA) self.funct6 = funct6 self.funct3 = funct3 def elaborate(self, platform): -- 2.44.1 From 2da87d4686919efd9fc728e7759387b3cd2c3b29 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Wed, 12 Aug 2020 13:36:50 +0800 Subject: [PATCH 078/109] Remove redundant parameter in InsnSlli constructor --- insns/InsnSlli.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/insns/InsnSlli.py b/insns/InsnSlli.py index f292ce8..72b22f5 100644 --- a/insns/InsnSlli.py +++ b/insns/InsnSlli.py @@ -5,8 +5,8 @@ SLLI instruction """ class InsnSlli(InsnRV32IITypeShift): - def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): - super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b000000, 0b001) + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b000000, 0b001) def elaborate(self, platform): m = super().elaborate(platform) -- 2.44.1 From 25dbc0e427926ef810ebf1ad1f7905c3371b62a7 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Wed, 12 Aug 2020 13:37:54 +0800 Subject: [PATCH 079/109] Remove redundant parameter in InsnSrli constructor --- insns/InsnSrli.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/insns/InsnSrli.py b/insns/InsnSrli.py index cb678ba..1216c99 100644 --- a/insns/InsnSrli.py +++ b/insns/InsnSrli.py @@ -5,8 +5,8 @@ SRLI instruction """ class InsnSrli(InsnRV32IITypeShift): - def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): - super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b000000, 0b101) + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b000000, 0b101) def elaborate(self, platform): m = super().elaborate(platform) -- 2.44.1 From 70c5a442d8598d3dfcff9e5e29305ebabce7e47c Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Wed, 12 Aug 2020 13:38:40 +0800 Subject: [PATCH 080/109] Remove redundant parameter in InsnSrai constructor --- insns/InsnSrai.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/insns/InsnSrai.py b/insns/InsnSrai.py index d95dbc8..f709aee 100644 --- a/insns/InsnSrai.py +++ b/insns/InsnSrai.py @@ -5,8 +5,8 @@ SRAI instruction """ class InsnSrai(InsnRV32IITypeShift): - def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): - super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b010000, 0b101) + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b010000, 0b101) def elaborate(self, platform): m = super().elaborate(platform) -- 2.44.1 From 4d55cce1b123b3f2572596a38ccb19343e307aad Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Wed, 12 Aug 2020 13:45:04 +0800 Subject: [PATCH 081/109] Fix JALR instruction --- insns/InsnJalr.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/insns/InsnJalr.py b/insns/InsnJalr.py index 71b1073..e2d76a6 100644 --- a/insns/InsnJalr.py +++ b/insns/InsnJalr.py @@ -5,6 +5,9 @@ JALR instruction """ class InsnJalr(InsnRV32IIType): + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA) + self.RISCV_FORMAL_COMPRESSED = RISCV_FORMAL_COMPRESSED def elaborate(self, platform): m = super().elaborate(platform) -- 2.44.1 From b12efc507acdc660bcd0cccaae98c13cc754c42e Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Wed, 12 Aug 2020 13:48:50 +0800 Subject: [PATCH 082/109] Remove redundant parameter in InsnRV32IITypeLoad constructor --- insns/InsnRV32IITypeLoad.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/insns/InsnRV32IITypeLoad.py b/insns/InsnRV32IITypeLoad.py index 8dba77c..d1d790b 100644 --- a/insns/InsnRV32IITypeLoad.py +++ b/insns/InsnRV32IITypeLoad.py @@ -5,8 +5,8 @@ RV32I I-Type Instruction (Load Variation) """ class InsnRV32IITypeLoad(InsnRV32IIType): - def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, RISCV_FORMAL_ALIGNED_MEM, funct3, mask_shift, is_signed): - super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED) + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM, funct3, mask_shift, is_signed): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA) self.RISCV_FORMAL_ALIGNED_MEM = RISCV_FORMAL_ALIGNED_MEM self.funct3 = funct3 self.mask_shift = mask_shift -- 2.44.1 From f7cada3535278748149f272c308c1f222d5799c0 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Wed, 12 Aug 2020 13:50:37 +0800 Subject: [PATCH 083/109] Remove redundant parameter in InsnLb constructor --- insns/InsnLb.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/insns/InsnLb.py b/insns/InsnLb.py index 5ee2353..663065f 100644 --- a/insns/InsnLb.py +++ b/insns/InsnLb.py @@ -5,5 +5,5 @@ LB instruction """ class InsnLb(InsnRV32IITypeLoad): - def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, RISCV_FORMAL_ALIGNED_MEM): - super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, RISCV_FORMAL_ALIGNED_MEM, 0b000, 1, True) + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM, 0b000, 1, True) -- 2.44.1 From 95c0c07c8308bbad14fe3fa2734a14e8ec77a9b1 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Wed, 12 Aug 2020 13:52:02 +0800 Subject: [PATCH 084/109] Remove redundant parameter in InsnLh constructor --- insns/InsnLh.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/insns/InsnLh.py b/insns/InsnLh.py index b69fac2..8698fa5 100644 --- a/insns/InsnLh.py +++ b/insns/InsnLh.py @@ -5,5 +5,5 @@ LH instruction """ class InsnLh(InsnRV32IITypeLoad): - def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, RISCV_FORMAL_ALIGNED_MEM): - super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, RISCV_FORMAL_ALIGNED_MEM, 0b001, 2, True) + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM, 0b001, 2, True) -- 2.44.1 From 1ab0c0c11dbecec6b420875a769bf589bb75f800 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Wed, 12 Aug 2020 13:52:47 +0800 Subject: [PATCH 085/109] Remove redundant parameter in InsnLw instruction --- insns/InsnLw.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/insns/InsnLw.py b/insns/InsnLw.py index c4e9e6d..2ab8565 100644 --- a/insns/InsnLw.py +++ b/insns/InsnLw.py @@ -5,5 +5,5 @@ LW instruction """ class InsnLw(InsnRV32IITypeLoad): - def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, RISCV_FORMAL_ALIGNED_MEM): - super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, RISCV_FORMAL_ALIGNED_MEM, 0b010, 4, True) + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM, 0b010, 4, True) -- 2.44.1 From 7c68ef175bfdfc0f09c9d6e0a6149f3e485bf017 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Wed, 12 Aug 2020 13:53:28 +0800 Subject: [PATCH 086/109] Remove redundant parameter in InsnLbu instruction --- insns/InsnLbu.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/insns/InsnLbu.py b/insns/InsnLbu.py index 7ff15c0..9db69e8 100644 --- a/insns/InsnLbu.py +++ b/insns/InsnLbu.py @@ -5,5 +5,5 @@ LBU instruction """ class InsnLbu(InsnRV32IITypeLoad): - def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, RISCV_FORMAL_ALIGNED_MEM): - super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, RISCV_FORMAL_ALIGNED_MEM, 0b100, 1, False) + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM, 0b100, 1, False) -- 2.44.1 From 5d083339ab0e025927b11daeca6f8245d58eec97 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Wed, 12 Aug 2020 13:54:13 +0800 Subject: [PATCH 087/109] Remove redundant parameter in InsnLhu constructor --- insns/InsnLhu.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/insns/InsnLhu.py b/insns/InsnLhu.py index 6f85978..2b40198 100644 --- a/insns/InsnLhu.py +++ b/insns/InsnLhu.py @@ -5,5 +5,5 @@ LHU instruction """ class InsnLhu(InsnRV32IITypeLoad): - def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, RISCV_FORMAL_ALIGNED_MEM): - super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, RISCV_FORMAL_ALIGNED_MEM, 0b101, 2, False) + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM, 0b101, 2, False) -- 2.44.1 From 8ef50fa0cf5c0381725cd49515ac82043241f347 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Wed, 12 Aug 2020 13:56:44 +0800 Subject: [PATCH 088/109] Remove redundant parameter in InsnRV32IITypeArith constructor --- insns/InsnRV32IITypeArith.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/insns/InsnRV32IITypeArith.py b/insns/InsnRV32IITypeArith.py index 2c78a4b..5cf1116 100644 --- a/insns/InsnRV32IITypeArith.py +++ b/insns/InsnRV32IITypeArith.py @@ -5,8 +5,8 @@ RV32I I-Type Instruction (Arithmetic Variation) """ class InsnRV32IITypeArith(InsnRV32IIType): - def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, funct3): - super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED) + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, funct3): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA) self.funct3 = funct3 def elaborate(self, platform): m = super().elaborate(platform) -- 2.44.1 From 0720d1fa0793db46901ef57a47e6c77173c86e22 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Wed, 12 Aug 2020 13:59:14 +0800 Subject: [PATCH 089/109] Remove redundant parameter in InsnAddi constructor --- insns/InsnAddi.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/insns/InsnAddi.py b/insns/InsnAddi.py index 85abc02..9bd72cb 100644 --- a/insns/InsnAddi.py +++ b/insns/InsnAddi.py @@ -5,8 +5,8 @@ ADDI instruction """ class InsnAddi(InsnRV32IITypeArith): - def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): - super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b000) + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b000) def elaborate(self, platform): m = super().elaborate(platform) -- 2.44.1 From c60203ce81f2d71b444398313580347906eb1550 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Wed, 12 Aug 2020 14:00:10 +0800 Subject: [PATCH 090/109] Remove redundant prameter in InsnSlti instruction --- insns/InsnSlti.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/insns/InsnSlti.py b/insns/InsnSlti.py index 07b4b52..2f70f8b 100644 --- a/insns/InsnSlti.py +++ b/insns/InsnSlti.py @@ -5,8 +5,8 @@ SLTI instruction """ class InsnSlti(InsnRV32IITypeArith): - def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): - super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b010) + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b010) def elaborate(self, platform): m = super().elaborate(platform) -- 2.44.1 From fda097c52e45bb37a88994e99be770185429009d Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Wed, 12 Aug 2020 14:01:00 +0800 Subject: [PATCH 091/109] Remove redundant prameter in InsnSltui instruction --- insns/InsnSltiu.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/insns/InsnSltiu.py b/insns/InsnSltiu.py index 2bf4d3a..946c11a 100644 --- a/insns/InsnSltiu.py +++ b/insns/InsnSltiu.py @@ -5,8 +5,8 @@ SLTIU instruction """ class InsnSltiu(InsnRV32IITypeArith): - def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): - super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b011) + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b011) def elaborate(self, platform): m = super().elaborate(platform) -- 2.44.1 From 3e08d4f26ee34426b4bc9aa0498dbd5012aa4534 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Wed, 12 Aug 2020 14:01:58 +0800 Subject: [PATCH 092/109] Remove redundant parameter in InsnXori constructor --- insns/InsnXori.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/insns/InsnXori.py b/insns/InsnXori.py index c27f195..77d74a1 100644 --- a/insns/InsnXori.py +++ b/insns/InsnXori.py @@ -5,8 +5,8 @@ XORI instruction """ class InsnXori(InsnRV32IITypeArith): - def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): - super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b100) + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b100) def elaborate(self, platform): m = super().elaborate(platform) -- 2.44.1 From 801bf08549aa59c9153115397f24f8bdb88f5f50 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Wed, 12 Aug 2020 14:02:43 +0800 Subject: [PATCH 093/109] Remove redundant parameter in InsnOri constructor --- insns/InsnOri.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/insns/InsnOri.py b/insns/InsnOri.py index 67c1b01..71fd535 100644 --- a/insns/InsnOri.py +++ b/insns/InsnOri.py @@ -5,8 +5,8 @@ ORI instruction """ class InsnOri(InsnRV32IITypeArith): - def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): - super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b110) + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b110) def elaborate(self, platform): m = super().elaborate(platform) -- 2.44.1 From 35ba759c30558536012e5b0b1941b17d4bd2ae99 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Wed, 12 Aug 2020 14:03:27 +0800 Subject: [PATCH 094/109] Remove redundant parameter in InsnAndi constructor --- insns/InsnAndi.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/insns/InsnAndi.py b/insns/InsnAndi.py index aa6c054..111f05f 100644 --- a/insns/InsnAndi.py +++ b/insns/InsnAndi.py @@ -5,8 +5,8 @@ ANDI instruction """ class InsnAndi(InsnRV32IITypeArith): - def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): - super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b111) + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b111) def elaborate(self, platform): m = super().elaborate(platform) -- 2.44.1 From 2943a307efeffec77878423dc1ce1655048031bb Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Wed, 12 Aug 2020 14:06:01 +0800 Subject: [PATCH 095/109] Remove redundant parameter in InsnRV32ISType constructor --- insns/InsnRV32ISType.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/insns/InsnRV32ISType.py b/insns/InsnRV32ISType.py index 089173f..8b8a44b 100644 --- a/insns/InsnRV32ISType.py +++ b/insns/InsnRV32ISType.py @@ -5,8 +5,8 @@ RV32I S-Type Instruction """ class InsnRV32ISType(Insn): - def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, RISCV_FORMAL_ALIGNED_MEM, funct3, mask_shift): - super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED) + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM, funct3, mask_shift): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA) self.RISCV_FORMAL_ALIGNED_MEM = RISCV_FORMAL_ALIGNED_MEM self.funct3 = funct3 self.mask_shift = mask_shift -- 2.44.1 From 8dbc8ebd8cf794e315a450dcc48e877ad5a8493d Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Wed, 12 Aug 2020 14:06:55 +0800 Subject: [PATCH 096/109] Remove redundant parameter in InsnSb constructor --- insns/InsnSb.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/insns/InsnSb.py b/insns/InsnSb.py index a589d1e..86f3748 100644 --- a/insns/InsnSb.py +++ b/insns/InsnSb.py @@ -5,5 +5,5 @@ SB instruction """ class InsnSb(InsnRV32ISType): - def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, RISCV_FORMAL_ALIGNED_MEM): - super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, RISCV_FORMAL_ALIGNED_MEM, 0b000, 1) + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM, 0b000, 1) -- 2.44.1 From 47fa70b3890a8f0fec8bd04460162e16dce1ce48 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Wed, 12 Aug 2020 14:07:47 +0800 Subject: [PATCH 097/109] Remove redundant parameter in InsnSh constructor --- insns/InsnSh.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/insns/InsnSh.py b/insns/InsnSh.py index b02608d..97d5b0e 100644 --- a/insns/InsnSh.py +++ b/insns/InsnSh.py @@ -5,5 +5,5 @@ SH instruction """ class InsnSh(InsnRV32ISType): - def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, RISCV_FORMAL_ALIGNED_MEM): - super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, RISCV_FORMAL_ALIGNED_MEM, 0b001, 2) + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM, 0b001, 2) -- 2.44.1 From 3c82069a4d1321d4782f1b1b2ac406af8d6c32f9 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Wed, 12 Aug 2020 14:09:41 +0800 Subject: [PATCH 098/109] Remove redundant parameter in InsnSw constructor --- insns/InsnSw.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/insns/InsnSw.py b/insns/InsnSw.py index 904a427..9db387f 100644 --- a/insns/InsnSw.py +++ b/insns/InsnSw.py @@ -5,5 +5,5 @@ SW instruction """ class InshSw(InsnRV32ISType): - def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, RISCV_FORMAL_ALIGNED_MEM): - super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, RISCV_FORMAL_ALIGNED_MEM, 0b010, 4) + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM, 0b010, 4) -- 2.44.1 From a09df9c7c4e2c946b7f1f6ca274019eddd50e121 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Wed, 12 Aug 2020 14:12:57 +0800 Subject: [PATCH 099/109] Remove redundant parameter in InsnRV32ISBType constructor --- insns/InsnRV32ISBType.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/insns/InsnRV32ISBType.py b/insns/InsnRV32ISBType.py index dd19387..f100e71 100644 --- a/insns/InsnRV32ISBType.py +++ b/insns/InsnRV32ISBType.py @@ -6,7 +6,8 @@ RV32I SB-Type Instruction class InsnRV32ISBType(Insn): def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, funct3): - super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED) + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA) + self.RISCV_FORMAL_COMPRESSED = RISCV_FORMAL_COMPRESSED self.funct3 = funct3 def elaborate(self, platform): m = super().elaborate(platform) -- 2.44.1 From 7e8ca12e5f819cb912223ba74bcae29d24e6e3df Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Wed, 12 Aug 2020 14:17:45 +0800 Subject: [PATCH 100/109] Fix JAL instruction --- insns/InsnJal.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/insns/InsnJal.py b/insns/InsnJal.py index 68ed094..6dcde6e 100644 --- a/insns/InsnJal.py +++ b/insns/InsnJal.py @@ -5,6 +5,9 @@ JAL instruction """ class InsnJal(Insn): + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA) + self.RISCV_FORMAL_COMPRESSED = RISCV_FORMAL_COMPRESSED def elaborate(self, platform): m = super().elaborate(platform) -- 2.44.1 From 23daacc619f45dd0ae15d72ca87311ac3cf1ac25 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Wed, 12 Aug 2020 14:20:17 +0800 Subject: [PATCH 101/109] Remove redundant parameter in InsnRV32IUType constructor --- insns/InsnRV32IUType.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/insns/InsnRV32IUType.py b/insns/InsnRV32IUType.py index 4016206..abea3a1 100644 --- a/insns/InsnRV32IUType.py +++ b/insns/InsnRV32IUType.py @@ -5,8 +5,8 @@ RV32I U-Type Instruction """ class InsnRV32IUType(Insn): - def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, opcode): - super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED) + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, opcode): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA) self.opcode = opcode def elaborate(self, platform): m = super().elaborate(platform) -- 2.44.1 From 8b92b1cbedd6edfd03aabec38ae6b862afdca7fb Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Wed, 12 Aug 2020 14:22:10 +0800 Subject: [PATCH 102/109] Remove redundant parameter in InsnLui constructor --- insns/InsnLui.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/insns/InsnLui.py b/insns/InsnLui.py index fa8ec49..c8db2d5 100644 --- a/insns/InsnLui.py +++ b/insns/InsnLui.py @@ -5,8 +5,8 @@ LUI instruction """ class InsnLui(InsnRV32IUType): - def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): - super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0110111) + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b0110111) def elaborate(self, platform): m = super().elaborate(platform) -- 2.44.1 From 75d113312532cc72fbb05ec4507a6e07dd33f96e Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Wed, 12 Aug 2020 14:23:09 +0800 Subject: [PATCH 103/109] Remove redundant parameter in InsnAuipc constructor --- insns/InsnAuipc.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/insns/InsnAuipc.py b/insns/InsnAuipc.py index 3760264..69d7c0b 100644 --- a/insns/InsnAuipc.py +++ b/insns/InsnAuipc.py @@ -5,8 +5,8 @@ AUIPC instruction """ class InsnAuipc(InsnRV32IUType): - def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): - super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0010111) + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b0010111) def elaborate(self, platform): m = super().elaborate(platform) -- 2.44.1 From 6868e0d7427b21a3e2f9c4f9354a5773728a6964 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Wed, 12 Aug 2020 17:26:39 +0800 Subject: [PATCH 104/109] Prepare RV32I Base ISA --- insns/IsaRV32I.py | 103 ++++++++++++++++++++++++++++++++++++++++ insns/IsaRV32IGen.py | 110 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 213 insertions(+) create mode 100644 insns/IsaRV32I.py create mode 100644 insns/IsaRV32IGen.py diff --git a/insns/IsaRV32I.py b/insns/IsaRV32I.py new file mode 100644 index 0000000..c66a33d --- /dev/null +++ b/insns/IsaRV32I.py @@ -0,0 +1,103 @@ +# Generated by IsaRV32IGen.py +from InsnLui import * +from InsnAuipc import * +from InsnJal import * +from InsnJalr import * +from InsnBeq import * +from InsnBne import * +from InsnBlt import * +from InsnBge import * +from InsnBltu import * +from InsnBgeu import * +from InsnLb import * +from InsnLh import * +from InsnLw import * +from InsnLbu import * +from InsnLhu import * +from InsnSb import * +from InsnSh import * +from InsnSw import * +from InsnAddi import * +from InsnSlti import * +from InsnSltiu import * +from InsnXori import * +from InsnOri import * +from InsnAndi import * +from InsnSlli import * +from InsnSrli import * +from InsnSrai import * +from InsnAdd import * +from InsnSub import * +from InsnSll import * +from InsnSlt import * +from InsnSltu import * +from InsnXor import * +from InsnSrl import * +from InsnSra import * +from InsnOr import * +from InsnAnd import * + +""" +RV32I Base ISA +""" + +class IsaRV32I(Elaboratable): + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA): + # Core-specific constants + self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN + self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN + self.RISCV_FORMAL_CSR_MISA = RISCV_FORMAL_CSR_MISA + + # Input ports + self.rvfi_valid = Signal(1) + self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) + self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) + self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) + self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) + self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) + if self.RISCV_FORMAL_CSR_MISA: + self.rvfi_csr_misa_rdata = Signal(self.RISCV_FORMAL_XLEN) + + # Output ports + if self.RISCV_FORMAL_CSR_MISA: + self.spec_csr_misa_rmask = Signal(self.RISCV_FORMAL_XLEN) + self.spec_valid = Signal(1) + self.spec_trap = Signal(1) + self.spec_rs1_addr = Signal(5) + self.spec_rs2_addr = Signal(5) + self.spec_rd_addr = Signal(5) + self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) + self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) + self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) + self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) + self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) + self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) + def ports(self): + input_ports = [ + self.rvfi_valid, + self.rvfi_insn, + self.rvfi_pc_rdata, + self.rvfi_rs1_rdata, + self.rvfi_rs2_rdata, + self.rvfi_mem_rdata + ] + if self.RISCV_FORMAL_CSR_MISA: + input_ports.append(self.rvfi_csr_misa_rdata) + output_ports = [ + self.spec_valid, + self.spec_trap, + self.spec_rs1_addr, + self.spec_rs2_addr, + self.spec_rd_addr, + self.spec_rd_wdata, + self.spec_pc_wdata, + self.spec_mem_addr, + self.spec_mem_rmask, + self.spec_mem_wmask, + self.spec_mem_wdata + ] + if self.RISCV_FORMAL_CSR_MISA: + output_ports.append(self.spec_csr_misa_rmask) + return input_ports + output_ports + def elaborate(self, platform): + pass diff --git a/insns/IsaRV32IGen.py b/insns/IsaRV32IGen.py new file mode 100644 index 0000000..4383bae --- /dev/null +++ b/insns/IsaRV32IGen.py @@ -0,0 +1,110 @@ +RV32I_INSNS = [ + 'lui', + 'auipc', + 'jal', + 'jalr', + 'beq', + 'bne', + 'blt', + 'bge', + 'bltu', + 'bgeu', + 'lb', + 'lh', + 'lw', + 'lbu', + 'lhu', + 'sb', + 'sh', + 'sw', + 'addi', + 'slti', + 'sltiu', + 'xori', + 'ori', + 'andi', + 'slli', + 'srli', + 'srai', + 'add', + 'sub', + 'sll', + 'slt', + 'sltu', + 'xor', + 'srl', + 'sra', + 'or', + 'and' +] + +if __name__ == '__main__': + print('# Generated by IsaRV32IGen.py') + for insn in RV32I_INSNS: + print('from Insn%s import *' % insn.capitalize()) + print() + print('"""') + print('RV32I Base ISA') + print('"""') + print() + print('class IsaRV32I(Elaboratable):') + print(' def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA):') + print(' # Core-specific constants') + print(' self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN') + print(' self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN') + print(' self.RISCV_FORMAL_CSR_MISA = RISCV_FORMAL_CSR_MISA') + print() + print(' # Input ports') + print(' self.rvfi_valid = Signal(1)') + print(' self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)') + print(' self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)') + print(' self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)') + print(' self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)') + print(' self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)') + print(' if self.RISCV_FORMAL_CSR_MISA:') + print(' self.rvfi_csr_misa_rdata = Signal(self.RISCV_FORMAL_XLEN)') + print() + print(' # Output ports') + print(' if self.RISCV_FORMAL_CSR_MISA:') + print(' self.spec_csr_misa_rmask = Signal(self.RISCV_FORMAL_XLEN)') + print(' self.spec_valid = Signal(1)') + print(' self.spec_trap = Signal(1)') + print(' self.spec_rs1_addr = Signal(5)') + print(' self.spec_rs2_addr = Signal(5)') + print(' self.spec_rd_addr = Signal(5)') + print(' self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)') + print(' self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)') + print(' self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)') + print(' self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))') + print(' self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))') + print(' self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)') + print(' def ports(self):') + print(' input_ports = [') + print(' self.rvfi_valid,') + print(' self.rvfi_insn,') + print(' self.rvfi_pc_rdata,') + print(' self.rvfi_rs1_rdata,') + print(' self.rvfi_rs2_rdata,') + print(' self.rvfi_mem_rdata') + print(' ]') + print(' if self.RISCV_FORMAL_CSR_MISA:') + print(' input_ports.append(self.rvfi_csr_misa_rdata)') + print(' output_ports = [') + print(' self.spec_valid,') + print(' self.spec_trap,') + print(' self.spec_rs1_addr,') + print(' self.spec_rs2_addr,') + print(' self.spec_rd_addr,') + print(' self.spec_rd_wdata,') + print(' self.spec_pc_wdata,') + print(' self.spec_mem_addr,') + print(' self.spec_mem_rmask,') + print(' self.spec_mem_wmask,') + print(' self.spec_mem_wdata') + print(' ]') + print(' if self.RISCV_FORMAL_CSR_MISA:') + print(' output_ports.append(self.spec_csr_misa_rmask)') + print(' return input_ports + output_ports') + print(' def elaborate(self, platform):') + print(' pass') + # TODO -- 2.44.1 From 9f6c634f4ac7a30fbf250910c9e4b0722f9d07cf Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Thu, 13 Aug 2020 12:19:40 +0800 Subject: [PATCH 105/109] Update README.md --- insns/IsaRV32I.py | 103 ---------------------------------------- insns/IsaRV32IGen.py | 110 ------------------------------------------- insns/README.md | 16 ++++++- 3 files changed, 15 insertions(+), 214 deletions(-) delete mode 100644 insns/IsaRV32I.py delete mode 100644 insns/IsaRV32IGen.py diff --git a/insns/IsaRV32I.py b/insns/IsaRV32I.py deleted file mode 100644 index c66a33d..0000000 --- a/insns/IsaRV32I.py +++ /dev/null @@ -1,103 +0,0 @@ -# Generated by IsaRV32IGen.py -from InsnLui import * -from InsnAuipc import * -from InsnJal import * -from InsnJalr import * -from InsnBeq import * -from InsnBne import * -from InsnBlt import * -from InsnBge import * -from InsnBltu import * -from InsnBgeu import * -from InsnLb import * -from InsnLh import * -from InsnLw import * -from InsnLbu import * -from InsnLhu import * -from InsnSb import * -from InsnSh import * -from InsnSw import * -from InsnAddi import * -from InsnSlti import * -from InsnSltiu import * -from InsnXori import * -from InsnOri import * -from InsnAndi import * -from InsnSlli import * -from InsnSrli import * -from InsnSrai import * -from InsnAdd import * -from InsnSub import * -from InsnSll import * -from InsnSlt import * -from InsnSltu import * -from InsnXor import * -from InsnSrl import * -from InsnSra import * -from InsnOr import * -from InsnAnd import * - -""" -RV32I Base ISA -""" - -class IsaRV32I(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA): - # Core-specific constants - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.RISCV_FORMAL_CSR_MISA = RISCV_FORMAL_CSR_MISA - - # Input ports - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - if self.RISCV_FORMAL_CSR_MISA: - self.rvfi_csr_misa_rdata = Signal(self.RISCV_FORMAL_XLEN) - - # Output ports - if self.RISCV_FORMAL_CSR_MISA: - self.spec_csr_misa_rmask = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - if self.RISCV_FORMAL_CSR_MISA: - input_ports.append(self.rvfi_csr_misa_rdata) - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - if self.RISCV_FORMAL_CSR_MISA: - output_ports.append(self.spec_csr_misa_rmask) - return input_ports + output_ports - def elaborate(self, platform): - pass diff --git a/insns/IsaRV32IGen.py b/insns/IsaRV32IGen.py deleted file mode 100644 index 4383bae..0000000 --- a/insns/IsaRV32IGen.py +++ /dev/null @@ -1,110 +0,0 @@ -RV32I_INSNS = [ - 'lui', - 'auipc', - 'jal', - 'jalr', - 'beq', - 'bne', - 'blt', - 'bge', - 'bltu', - 'bgeu', - 'lb', - 'lh', - 'lw', - 'lbu', - 'lhu', - 'sb', - 'sh', - 'sw', - 'addi', - 'slti', - 'sltiu', - 'xori', - 'ori', - 'andi', - 'slli', - 'srli', - 'srai', - 'add', - 'sub', - 'sll', - 'slt', - 'sltu', - 'xor', - 'srl', - 'sra', - 'or', - 'and' -] - -if __name__ == '__main__': - print('# Generated by IsaRV32IGen.py') - for insn in RV32I_INSNS: - print('from Insn%s import *' % insn.capitalize()) - print() - print('"""') - print('RV32I Base ISA') - print('"""') - print() - print('class IsaRV32I(Elaboratable):') - print(' def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA):') - print(' # Core-specific constants') - print(' self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN') - print(' self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN') - print(' self.RISCV_FORMAL_CSR_MISA = RISCV_FORMAL_CSR_MISA') - print() - print(' # Input ports') - print(' self.rvfi_valid = Signal(1)') - print(' self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)') - print(' self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)') - print(' self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)') - print(' self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)') - print(' self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)') - print(' if self.RISCV_FORMAL_CSR_MISA:') - print(' self.rvfi_csr_misa_rdata = Signal(self.RISCV_FORMAL_XLEN)') - print() - print(' # Output ports') - print(' if self.RISCV_FORMAL_CSR_MISA:') - print(' self.spec_csr_misa_rmask = Signal(self.RISCV_FORMAL_XLEN)') - print(' self.spec_valid = Signal(1)') - print(' self.spec_trap = Signal(1)') - print(' self.spec_rs1_addr = Signal(5)') - print(' self.spec_rs2_addr = Signal(5)') - print(' self.spec_rd_addr = Signal(5)') - print(' self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)') - print(' self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)') - print(' self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)') - print(' self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))') - print(' self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))') - print(' self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)') - print(' def ports(self):') - print(' input_ports = [') - print(' self.rvfi_valid,') - print(' self.rvfi_insn,') - print(' self.rvfi_pc_rdata,') - print(' self.rvfi_rs1_rdata,') - print(' self.rvfi_rs2_rdata,') - print(' self.rvfi_mem_rdata') - print(' ]') - print(' if self.RISCV_FORMAL_CSR_MISA:') - print(' input_ports.append(self.rvfi_csr_misa_rdata)') - print(' output_ports = [') - print(' self.spec_valid,') - print(' self.spec_trap,') - print(' self.spec_rs1_addr,') - print(' self.spec_rs2_addr,') - print(' self.spec_rd_addr,') - print(' self.spec_rd_wdata,') - print(' self.spec_pc_wdata,') - print(' self.spec_mem_addr,') - print(' self.spec_mem_rmask,') - print(' self.spec_mem_wmask,') - print(' self.spec_mem_wdata') - print(' ]') - print(' if self.RISCV_FORMAL_CSR_MISA:') - print(' output_ports.append(self.spec_csr_misa_rmask)') - print(' return input_ports + output_ports') - print(' def elaborate(self, platform):') - print(' pass') - # TODO diff --git a/insns/README.md b/insns/README.md index 7f2d35f..ca395c1 100644 --- a/insns/README.md +++ b/insns/README.md @@ -34,6 +34,8 @@ Below is a table of RISC-V instructions supported by the original riscv-formal f ## Class Synopsis +### Instructions + Below is a list of instructions currently supported by this port of the riscv-formal framework and is expected to grow over time. The instructions are roughly grouped by instruction type but sometimes with further specializations - the hierarchy of the lists reflects the hierarchy of inheritance in the classes used to represent various instructions. - `Insn`: General RISC-V instruction @@ -83,6 +85,18 @@ Below is a list of instructions currently supported by this port of the riscv-fo - `InsnLui`: LUI instruction - `InsnAuipc`: AUIPC instruction -## Parameters +### ISAs TODO + +## Core-specific constants + +The following core-specific constants are currently supported: + +| Constant | Description | Valid value(s) | Supported by instruction(s) | +| --- | --- | --- | --- | +| `RISCV_FORMAL_ILEN` | Max length of instruction retired by core | `32` | LUI, AUIPC, JAL, JALR, BEQ, BNE, BLT, BGE, BLTU, BGEU, LB, LH, LW, LBU, LHU, SB, SH, SW, ADDI, SLTI, SLTIU, XORI, ORI, ANDI, SLLI, SRLI, SRAI, ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND | +| `RISCV_FORMAL_XLEN` | Width of integer registers | `32` | LUI, AUIPC, JAL, JALR, BEQ, BNE, BLT, BGE, BLTU, BGEU, LB, LH, LW, LBU, LHU, SB, SH, SW, ADDI, SLTI, SLTIU, XORI, ORI, ANDI, SLLI, SRLI, SRAI, ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND | +| `RISCV_FORMAL_CSR_MISA` | Support for MISA CSRs enabled | `True`, `False` | LUI, AUIPC, JAL, JALR, BEQ, BNE, BLT, BGE, BLTU, BGEU, LB, LH, LW, LBU, LHU, SB, SH, SW, ADDI, SLTI, SLTIU, XORI, ORI, ANDI, SLLI, SRLI, SRAI, ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND | +| `RISCV_FORMAL_COMPRESSED` | Support for compressed instructions | `True`, `False` | JAL, JALR, BEQ, BNE, BLT, BGE, BLTU, BGEU | +| `RISCV_FORMAL_ALIGNED_MEM` | Require aligned memory accesses | `True`, `False` | LB, LH, LW, LBU, LHU, SB, SH, SW | -- 2.44.1 From 28949f36f42421cd1bc27b5330b9f56fddf54fb8 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Thu, 13 Aug 2020 13:46:16 +0800 Subject: [PATCH 106/109] Fix typo in InsnSw.py --- insns/InsnSw.py | 2 +- insns/IsaRV32I.py | 148 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 149 insertions(+), 1 deletion(-) create mode 100644 insns/IsaRV32I.py diff --git a/insns/InsnSw.py b/insns/InsnSw.py index 9db387f..cd17787 100644 --- a/insns/InsnSw.py +++ b/insns/InsnSw.py @@ -4,6 +4,6 @@ from InsnRV32ISType import * SW instruction """ -class InshSw(InsnRV32ISType): +class InsnSw(InsnRV32ISType): def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM): super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM, 0b010, 4) diff --git a/insns/IsaRV32I.py b/insns/IsaRV32I.py new file mode 100644 index 0000000..e895d8d --- /dev/null +++ b/insns/IsaRV32I.py @@ -0,0 +1,148 @@ +from InsnLui import * +from InsnAuipc import * +from InsnJal import * +from InsnJalr import * +from InsnBeq import * +from InsnBne import * +from InsnBlt import * +from InsnBge import * +from InsnBltu import * +from InsnBgeu import * +from InsnLb import * +from InsnLh import * +from InsnLw import * +from InsnLbu import * +from InsnLhu import * +from InsnSb import * +from InsnSh import * +from InsnSw import * +from InsnAddi import * +from InsnSlti import * +from InsnSltiu import * +from InsnXori import * +from InsnOri import * +from InsnAndi import * +from InsnSlli import * +from InsnSrli import * +from InsnSrai import * +from InsnAdd import * +from InsnSub import * +from InsnSll import * +from InsnSlt import * +from InsnSltu import * +from InsnXor import * +from InsnSrl import * +from InsnSra import * +from InsnOr import * +from InsnAnd import * + +""" +RV32I Base ISA +""" + +class IsaRV32I(Elaboratable): + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, RISCV_FORMAL_ALIGNED_MEM): + # Core-specific constants + self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN + self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN + self.RISCV_FORMAL_CSR_MISA = RISCV_FORMAL_CSR_MISA + self.RISCV_FORMAL_COMPRESSED = RISCV_FORMAL_COMPRESSED + self.RISCV_FORMAL_ALIGNED_MEM = RISCV_FORMAL_ALIGNED_MEM + + # Input ports + self.rvfi_valid = Signal(1) + self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) + self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) + self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) + self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) + self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) + if self.RISCV_FORMAL_CSR_MISA: + self.rvfi_csr_misa_rdata = Signal(self.RISCV_FORMAL_XLEN) + + # Output ports + if self.RISCV_FORMAL_CSR_MISA: + self.spec_csr_misa_rmask = Signal(self.RISCV_FORMAL_XLEN) + self.spec_valid = Signal(1) + self.spec_trap = Signal(1) + self.spec_rs1_addr = Signal(5) + self.spec_rs2_addr = Signal(5) + self.spec_rd_addr = Signal(5) + self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) + self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) + self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) + self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) + self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) + self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) + def ports(self): + input_ports = [ + self.rvfi_valid, + self.rvfi_insn, + self.rvfi_pc_rdata, + self.rvfi_rs1_rdata, + self.rvfi_rs2_rdata, + self.rvfi_mem_rdata + ] + if self.RISCV_FORMAL_CSR_MISA: + input_ports.append(self.rvfi_csr_misa_rdata) + output_ports = [ + self.spec_valid, + self.spec_trap, + self.spec_rs1_addr, + self.spec_rs2_addr, + self.spec_rd_addr, + self.spec_rd_wdata, + self.spec_pc_wdata, + self.spec_mem_addr, + self.spec_mem_rmask, + self.spec_mem_wmask, + self.spec_mem_wdata + ] + if self.RISCV_FORMAL_CSR_MISA: + output_ports.append(self.spec_csr_misa_rmask) + return input_ports + output_ports + def elaborate(self, platform): + m = Module() + + insn_submodules = {} + + m.submodules._lui = insn_submodules['lui'] = InsnLui(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA) + m.submodules._auipc = insn_submodules['auipc'] = InsnAuipc(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA) + m.submodules._jal = insn_submodules['jal'] = InsnJal(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED) + m.submodules._jalr = insn_submodules['jalr'] = InsnJalr(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED) + m.submodules._beq = insn_submodules['beq'] = InsnBeq(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED) + m.submodules._bne = insn_submodules['bne'] = InsnBne(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED) + m.submodules._blt = insn_submodules['blt'] = InsnBlt(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED) + m.submodules._bge = insn_submodules['bge'] = InsnBge(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED) + m.submodules._bltu = insn_submodules['bltu'] = InsnBltu(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED) + m.submodules._bgeu = insn_submodules['bgeu'] = InsnBgeu(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED) + m.submodules._lb = insn_submodules['lb'] = InsnLb(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED) + m.submodules._lh = insn_submodules['lh'] = InsnLh(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED) + m.submodules._lw = insn_submodules['lw'] = InsnLw(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED) + m.submodules._lbu = insn_submodules['lbu'] = InsnLbu(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED) + m.submodules._lhu = insn_submodules['lhu'] = InsnLhu(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED) + m.submodules._sb = insn_submodules['sb'] = InsnSb(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED) + m.submodules._sh = insn_submodules['Sh'] = InsnSh(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED) + m.submodules._sw = insn_submodules['sw'] = InsnSw(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED) + m.submodules._addi = insn_submodules['addi'] = InsnAddi(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA) + m.submodules._slti = insn_submodules['slti'] = InsnSlti(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA) + m.submodules._sltiu = insn_submodules['sltiu'] = InsnSltiu(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA) + m.submodules._xori = insn_submodules['xori'] = InsnXori(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA) + m.submodules._ori = insn_submodules['ori'] = InsnOri(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA) + m.submodules._andi = insn_submodules['andi'] = InsnAndi(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA) + m.submodules._slli = insn_submodules['slli'] = InsnSlli(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA) + m.submodules._srli = insn_submodules['srli'] = InsnSrli(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA) + m.submodules._srai = insn_submodules['srai'] = InsnSrai(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA) + m.submodules._add = insn_submodules['add'] = InsnAdd(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA) + m.submodules._sub = insn_submodules['sub'] = InsnSub(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA) + m.submodules._sll = insn_submodules['sll'] = InsnSll(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA) + m.submodules._slt = insn_submodules['slt'] = InsnSlt(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA) + m.submodules._sltu = insn_submodules['sltu'] = InsnSltu(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA) + m.submodules._xor = insn_submodules['xor'] = InsnXor(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA) + m.submodules._srl = insn_submodules['srl'] = InsnSrl(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA) + m.submodules._sra = insn_submodules['sra'] = InsnSra(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA) + m.submodules._or = insn_submodules['or'] = InsnOr(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA) + m.submodules._and = insn_submodules['and'] = InsnAnd(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA) + + # TODO + + return m -- 2.44.1 From 40344f78413da2357529951179b132bb435c8e66 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Thu, 13 Aug 2020 14:23:55 +0800 Subject: [PATCH 107/109] Add RV32I base ISA --- insns/IsaRV32I.py | 71 ++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 70 insertions(+), 1 deletion(-) diff --git a/insns/IsaRV32I.py b/insns/IsaRV32I.py index e895d8d..c1a7985 100644 --- a/insns/IsaRV32I.py +++ b/insns/IsaRV32I.py @@ -143,6 +143,75 @@ class IsaRV32I(Elaboratable): m.submodules._or = insn_submodules['or'] = InsnOr(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA) m.submodules._and = insn_submodules['and'] = InsnAnd(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA) - # TODO + for _, insn in insn_submodules.items(): + m.d.comb += insn.rvfi_valid.eq(self.rvfi_valid) + m.d.comb += insn.rvfi_insn.eq(self.rvfi_insn) + m.d.comb += insn.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) + m.d.comb += insn.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) + m.d.comb += insn.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) + m.d.comb += insn.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) + if self.RISCV_FORMAL_CSR_MISA: + m.d.comb += insn.rvfi_csr_misa_rdata.eq(self.rvfi_csr_misa_rdata) + + spec_valid = 0 + for _, insn in insn_submodules.items(): + spec_valid = Mux(insn.spec_valid, insn.spec_valid, spec_valid) + m.d.comb += self.spec_valid.eq(spec_valid) + + spec_trap = 0 + for _, insn in insn_submodules.items(): + spec_trap = Mux(insn.spec_valid, insn.spec_trap, spec_trap) + m.d.comb += self.spec_trap.eq(spec_trap) + + spec_rs1_addr = 0 + for _, insn in insn_submodules.items(): + spec_rs1_addr = Mux(insn.spec_valid, insn.spec_rs1_addr, spec_rs1_addr) + m.d.comb += self.spec_rs1_addr.eq(spec_rs1_addr) + + spec_rs2_addr = 0 + for _, insn in insn_submodules.items(): + spec_rs2_addr = Mux(insn.spec_valid, insn.spec_rs2_addr, spec_rs2_addr) + m.d.comb += self.spec_rs2_addr.eq(spec_rs2_addr) + + spec_rd_addr = 0 + for _, insn in insn_submodules.items(): + spec_rd_addr = Mux(insn.spec_valid, insn.spec_rd_addr, spec_rd_addr) + m.d.comb += self.spec_rd_addr.eq(spec_rd_addr) + + spec_rd_wdata = 0 + for _, insn in insn_submodules.items(): + spec_rd_wdata = Mux(insn.spec_valid, insn.spec_rd_wdata, spec_rd_wdata) + m.d.comb += self.spec_rd_wdata.eq(spec_rd_wdata) + + spec_pc_wdata = 0 + for _, insn in insn_submodules.items(): + spec_pc_wdata = Mux(insn.spec_valid, insn.spec_pc_wdata, spec_pc_wdata) + m.d.comb += self.spec_pc_wdata.eq(spec_pc_wdata) + + spec_mem_addr = 0 + for _, insn in insn_submodules.items(): + spec_mem_addr = Mux(insn.spec_valid, insn.spec_mem_addr, spec_mem_addr) + m.d.comb += self.spec_mem_addr.eq(spec_mem_addr) + + spec_mem_rmask = 0 + for _, insn in insn_submodules.items(): + spec_mem_rmask = Mux(insn.spec_valid, insn.spec_mem_rmask, spec_mem_rmask) + m.d.comb += self.spec_mem_rmask.eq(spec_mem_rmask) + + spec_mem_wmask = 0 + for _, insn in insn_submodules.items(): + spec_mem_wmask = Mux(insn.spec_valid, insn.spec_mem_wmask, spec_mem_wmask) + m.d.comb += self.spec_mem_wmask.eq(spec_mem_wmask) + + spec_mem_wdata = 0 + for _, insn in insn_submodules.items(): + spec_mem_wdata = Mux(insn.spec_valid, insn.spec_mem_wdata, spec_mem_wdata) + m.d.comb += self.spec_mem_wdata.eq(spec_mem_wdata) + + if self.RISCV_FORMAL_CSR_MISA: + spec_csr_misa_rmask = 0 + for _, insn in insn_submodules.items(): + spec_csr_misa_rmask = Mux(insn.spec_valid, insn.spec_csr_misa_rmask, spec_csr_misa_rmask) + m.d.comb += self.spec_csr_misa_rmask.eq(spec_csr_misa_rmask) return m -- 2.44.1 From 4d211bb24ab2ab2acd3a236d470a6c2877b2b322 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Thu, 13 Aug 2020 14:28:42 +0800 Subject: [PATCH 108/109] Update README.md --- insns/README.md | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/insns/README.md b/insns/README.md index ca395c1..48dd648 100644 --- a/insns/README.md +++ b/insns/README.md @@ -87,16 +87,16 @@ Below is a list of instructions currently supported by this port of the riscv-fo ### ISAs -TODO +- `IsaRV32I`: RV32I Base ISA ## Core-specific constants The following core-specific constants are currently supported: -| Constant | Description | Valid value(s) | Supported by instruction(s) | -| --- | --- | --- | --- | -| `RISCV_FORMAL_ILEN` | Max length of instruction retired by core | `32` | LUI, AUIPC, JAL, JALR, BEQ, BNE, BLT, BGE, BLTU, BGEU, LB, LH, LW, LBU, LHU, SB, SH, SW, ADDI, SLTI, SLTIU, XORI, ORI, ANDI, SLLI, SRLI, SRAI, ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND | -| `RISCV_FORMAL_XLEN` | Width of integer registers | `32` | LUI, AUIPC, JAL, JALR, BEQ, BNE, BLT, BGE, BLTU, BGEU, LB, LH, LW, LBU, LHU, SB, SH, SW, ADDI, SLTI, SLTIU, XORI, ORI, ANDI, SLLI, SRLI, SRAI, ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND | -| `RISCV_FORMAL_CSR_MISA` | Support for MISA CSRs enabled | `True`, `False` | LUI, AUIPC, JAL, JALR, BEQ, BNE, BLT, BGE, BLTU, BGEU, LB, LH, LW, LBU, LHU, SB, SH, SW, ADDI, SLTI, SLTIU, XORI, ORI, ANDI, SLLI, SRLI, SRAI, ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND | -| `RISCV_FORMAL_COMPRESSED` | Support for compressed instructions | `True`, `False` | JAL, JALR, BEQ, BNE, BLT, BGE, BLTU, BGEU | -| `RISCV_FORMAL_ALIGNED_MEM` | Require aligned memory accesses | `True`, `False` | LB, LH, LW, LBU, LHU, SB, SH, SW | +| Constant | Description | Valid value(s) | Supported by instruction(s) | Supported by ISA(s) | +| --- | --- | --- | --- | --- | +| `RISCV_FORMAL_ILEN` | Max length of instruction retired by core | `32` | LUI, AUIPC, JAL, JALR, BEQ, BNE, BLT, BGE, BLTU, BGEU, LB, LH, LW, LBU, LHU, SB, SH, SW, ADDI, SLTI, SLTIU, XORI, ORI, ANDI, SLLI, SRLI, SRAI, ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND | RV32I | +| `RISCV_FORMAL_XLEN` | Width of integer registers | `32` | LUI, AUIPC, JAL, JALR, BEQ, BNE, BLT, BGE, BLTU, BGEU, LB, LH, LW, LBU, LHU, SB, SH, SW, ADDI, SLTI, SLTIU, XORI, ORI, ANDI, SLLI, SRLI, SRAI, ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND | RV32I | +| `RISCV_FORMAL_CSR_MISA` | Support for MISA CSRs enabled | `True`, `False` | LUI, AUIPC, JAL, JALR, BEQ, BNE, BLT, BGE, BLTU, BGEU, LB, LH, LW, LBU, LHU, SB, SH, SW, ADDI, SLTI, SLTIU, XORI, ORI, ANDI, SLLI, SRLI, SRAI, ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND | RV32I | +| `RISCV_FORMAL_COMPRESSED` | Support for compressed instructions | `True`, `False` | JAL, JALR, BEQ, BNE, BLT, BGE, BLTU, BGEU | RV32I | +| `RISCV_FORMAL_ALIGNED_MEM` | Require aligned memory accesses | `True`, `False` | LB, LH, LW, LBU, LHU, SB, SH, SW | RV32I | -- 2.44.1 From f358e0679a86e399cb92edf260ce5738e8b2eb94 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Thu, 13 Aug 2020 15:14:46 +0800 Subject: [PATCH 109/109] Rename module names to follow PEP8 --- insns/{Insn.py => insn.py} | 0 insns/{InsnAdd.py => insn_add.py} | 2 +- insns/{InsnAddi.py => insn_addi.py} | 2 +- insns/{InsnAnd.py => insn_and.py} | 2 +- insns/{InsnAndi.py => insn_andi.py} | 2 +- insns/{InsnAuipc.py => insn_auipc.py} | 2 +- insns/{InsnBeq.py => insn_beq.py} | 2 +- insns/{InsnBge.py => insn_bge.py} | 2 +- insns/{InsnBgeu.py => insn_bgeu.py} | 2 +- insns/{InsnBlt.py => insn_blt.py} | 2 +- insns/{InsnBltu.py => insn_bltu.py} | 2 +- insns/{InsnBne.py => insn_bne.py} | 2 +- insns/{InsnJal.py => insn_jal.py} | 2 +- insns/{InsnJalr.py => insn_jalr.py} | 2 +- insns/{InsnLb.py => insn_lb.py} | 2 +- insns/{InsnLbu.py => insn_lbu.py} | 2 +- insns/{InsnLh.py => insn_lh.py} | 2 +- insns/{InsnLhu.py => insn_lhu.py} | 2 +- insns/{InsnLui.py => insn_lui.py} | 2 +- insns/{InsnLw.py => insn_lw.py} | 2 +- insns/{InsnOr.py => insn_or.py} | 2 +- insns/{InsnOri.py => insn_ori.py} | 2 +- ...InsnRV32IIType.py => insn_rv32i_i_type.py} | 2 +- ...ypeArith.py => insn_rv32i_i_type_arith.py} | 2 +- ...ITypeLoad.py => insn_rv32i_i_type_load.py} | 2 +- ...ypeShift.py => insn_rv32i_i_type_shift.py} | 2 +- ...InsnRV32IRType.py => insn_rv32i_r_type.py} | 2 +- ...InsnRV32ISType.py => insn_rv32i_s_type.py} | 2 +- ...snRV32ISBType.py => insn_rv32i_sb_type.py} | 2 +- ...InsnRV32IUType.py => insn_rv32i_u_type.py} | 2 +- insns/{InsnSb.py => insn_sb.py} | 2 +- insns/{InsnSh.py => insn_sh.py} | 2 +- insns/{InsnSll.py => insn_sll.py} | 2 +- insns/{InsnSlli.py => insn_slli.py} | 2 +- insns/{InsnSlt.py => insn_slt.py} | 2 +- insns/{InsnSlti.py => insn_slti.py} | 2 +- insns/{InsnSltiu.py => insn_sltiu.py} | 2 +- insns/{InsnSltu.py => insn_sltu.py} | 2 +- insns/{InsnSra.py => insn_sra.py} | 2 +- insns/{InsnSrai.py => insn_srai.py} | 2 +- insns/{InsnSrl.py => insn_srl.py} | 2 +- insns/{InsnSrli.py => insn_srli.py} | 2 +- insns/{InsnSub.py => insn_sub.py} | 2 +- insns/{InsnSw.py => insn_sw.py} | 2 +- insns/{InsnXor.py => insn_xor.py} | 2 +- insns/{InsnXori.py => insn_xori.py} | 2 +- insns/{IsaRV32I.py => isa_rv32i.py} | 74 +++++++++---------- 47 files changed, 82 insertions(+), 82 deletions(-) rename insns/{Insn.py => insn.py} (100%) rename insns/{InsnAdd.py => insn_add.py} (93%) rename insns/{InsnAddi.py => insn_addi.py} (92%) rename insns/{InsnAnd.py => insn_and.py} (93%) rename insns/{InsnAndi.py => insn_andi.py} (92%) rename insns/{InsnAuipc.py => insn_auipc.py} (93%) rename insns/{InsnBeq.py => insn_beq.py} (95%) rename insns/{InsnBge.py => insn_bge.py} (95%) rename insns/{InsnBgeu.py => insn_bgeu.py} (95%) rename insns/{InsnBlt.py => insn_blt.py} (95%) rename insns/{InsnBltu.py => insn_bltu.py} (95%) rename insns/{InsnBne.py => insn_bne.py} (95%) rename insns/{InsnJal.py => insn_jal.py} (98%) rename insns/{InsnJalr.py => insn_jalr.py} (97%) rename insns/{InsnLb.py => insn_lb.py} (88%) rename insns/{InsnLbu.py => insn_lbu.py} (89%) rename insns/{InsnLh.py => insn_lh.py} (88%) rename insns/{InsnLhu.py => insn_lhu.py} (89%) rename insns/{InsnLui.py => insn_lui.py} (92%) rename insns/{InsnLw.py => insn_lw.py} (88%) rename insns/{InsnOr.py => insn_or.py} (93%) rename insns/{InsnOri.py => insn_ori.py} (92%) rename insns/{InsnRV32IIType.py => insn_rv32i_i_type.py} (92%) rename insns/{InsnRV32IITypeArith.py => insn_rv32i_i_type_arith.py} (96%) rename insns/{InsnRV32IITypeLoad.py => insn_rv32i_i_type_load.py} (98%) rename insns/{InsnRV32IITypeShift.py => insn_rv32i_i_type_shift.py} (98%) rename insns/{InsnRV32IRType.py => insn_rv32i_r_type.py} (98%) rename insns/{InsnRV32ISType.py => insn_rv32i_s_type.py} (99%) rename insns/{InsnRV32ISBType.py => insn_rv32i_sb_type.py} (98%) rename insns/{InsnRV32IUType.py => insn_rv32i_u_type.py} (97%) rename insns/{InsnSb.py => insn_sb.py} (90%) rename insns/{InsnSh.py => insn_sh.py} (90%) rename insns/{InsnSll.py => insn_sll.py} (94%) rename insns/{InsnSlli.py => insn_slli.py} (92%) rename insns/{InsnSlt.py => insn_slt.py} (93%) rename insns/{InsnSlti.py => insn_slti.py} (92%) rename insns/{InsnSltiu.py => insn_sltiu.py} (92%) rename insns/{InsnSltu.py => insn_sltu.py} (93%) rename insns/{InsnSra.py => insn_sra.py} (95%) rename insns/{InsnSrai.py => insn_srai.py} (93%) rename insns/{InsnSrl.py => insn_srl.py} (94%) rename insns/{InsnSrli.py => insn_srli.py} (92%) rename insns/{InsnSub.py => insn_sub.py} (93%) rename insns/{InsnSw.py => insn_sw.py} (90%) rename insns/{InsnXor.py => insn_xor.py} (93%) rename insns/{InsnXori.py => insn_xori.py} (92%) rename insns/{IsaRV32I.py => isa_rv32i.py} (93%) diff --git a/insns/Insn.py b/insns/insn.py similarity index 100% rename from insns/Insn.py rename to insns/insn.py diff --git a/insns/InsnAdd.py b/insns/insn_add.py similarity index 93% rename from insns/InsnAdd.py rename to insns/insn_add.py index c3efd9e..54128cb 100644 --- a/insns/InsnAdd.py +++ b/insns/insn_add.py @@ -1,4 +1,4 @@ -from InsnRV32IRType import * +from insn_rv32i_r_type import * """ ADD instruction diff --git a/insns/InsnAddi.py b/insns/insn_addi.py similarity index 92% rename from insns/InsnAddi.py rename to insns/insn_addi.py index 9bd72cb..9aa5c64 100644 --- a/insns/InsnAddi.py +++ b/insns/insn_addi.py @@ -1,4 +1,4 @@ -from InsnRV32IITypeArith import * +from insn_rv32i_i_type_arith import * """ ADDI instruction diff --git a/insns/InsnAnd.py b/insns/insn_and.py similarity index 93% rename from insns/InsnAnd.py rename to insns/insn_and.py index a71390a..bb1f822 100644 --- a/insns/InsnAnd.py +++ b/insns/insn_and.py @@ -1,4 +1,4 @@ -from InsnRV32IRType import * +from insn_rv32i_r_type import * """ AND instruction diff --git a/insns/InsnAndi.py b/insns/insn_andi.py similarity index 92% rename from insns/InsnAndi.py rename to insns/insn_andi.py index 111f05f..94d74b2 100644 --- a/insns/InsnAndi.py +++ b/insns/insn_andi.py @@ -1,4 +1,4 @@ -from InsnRV32IITypeArith import * +from insn_rv32i_i_type_arith import * """ ANDI instruction diff --git a/insns/InsnAuipc.py b/insns/insn_auipc.py similarity index 93% rename from insns/InsnAuipc.py rename to insns/insn_auipc.py index 69d7c0b..d049422 100644 --- a/insns/InsnAuipc.py +++ b/insns/insn_auipc.py @@ -1,4 +1,4 @@ -from InsnRV32IUType import * +from insn_rv32i_u_type import * """ AUIPC instruction diff --git a/insns/InsnBeq.py b/insns/insn_beq.py similarity index 95% rename from insns/InsnBeq.py rename to insns/insn_beq.py index cb1f2bd..918454f 100644 --- a/insns/InsnBeq.py +++ b/insns/insn_beq.py @@ -1,4 +1,4 @@ -from InsnRV32ISBType import * +from insn_rv32i_sb_type import * """ BEQ instruction diff --git a/insns/InsnBge.py b/insns/insn_bge.py similarity index 95% rename from insns/InsnBge.py rename to insns/insn_bge.py index 2158e79..d91e300 100644 --- a/insns/InsnBge.py +++ b/insns/insn_bge.py @@ -1,4 +1,4 @@ -from InsnRV32ISBType import * +from insn_rv32i_sb_type import * """ BGE instruction diff --git a/insns/InsnBgeu.py b/insns/insn_bgeu.py similarity index 95% rename from insns/InsnBgeu.py rename to insns/insn_bgeu.py index 5f1341e..27c3e7f 100644 --- a/insns/InsnBgeu.py +++ b/insns/insn_bgeu.py @@ -1,4 +1,4 @@ -from InsnRV32ISBType import * +from insn_rv32i_sb_type import * """ BGEU instruction diff --git a/insns/InsnBlt.py b/insns/insn_blt.py similarity index 95% rename from insns/InsnBlt.py rename to insns/insn_blt.py index ade2f47..ba3ad17 100644 --- a/insns/InsnBlt.py +++ b/insns/insn_blt.py @@ -1,4 +1,4 @@ -from InsnRV32ISBType import * +from insn_rv32i_sb_type import * """ BLT instruction diff --git a/insns/InsnBltu.py b/insns/insn_bltu.py similarity index 95% rename from insns/InsnBltu.py rename to insns/insn_bltu.py index fb39c75..5817b60 100644 --- a/insns/InsnBltu.py +++ b/insns/insn_bltu.py @@ -1,4 +1,4 @@ -from InsnRV32ISBType import * +from insn_rv32i_sb_type import * """ BLTU instruction diff --git a/insns/InsnBne.py b/insns/insn_bne.py similarity index 95% rename from insns/InsnBne.py rename to insns/insn_bne.py index 415adfd..926acbc 100644 --- a/insns/InsnBne.py +++ b/insns/insn_bne.py @@ -1,4 +1,4 @@ -from InsnRV32ISBType import * +from insn_rv32i_sb_type import * """ BNE instruction diff --git a/insns/InsnJal.py b/insns/insn_jal.py similarity index 98% rename from insns/InsnJal.py rename to insns/insn_jal.py index 6dcde6e..82b1892 100644 --- a/insns/InsnJal.py +++ b/insns/insn_jal.py @@ -1,4 +1,4 @@ -from Insn import * +from insn import * """ JAL instruction diff --git a/insns/InsnJalr.py b/insns/insn_jalr.py similarity index 97% rename from insns/InsnJalr.py rename to insns/insn_jalr.py index e2d76a6..34aeeda 100644 --- a/insns/InsnJalr.py +++ b/insns/insn_jalr.py @@ -1,4 +1,4 @@ -from InsnRV32IIType import * +from insn_rv32i_i_type import * """ JALR instruction diff --git a/insns/InsnLb.py b/insns/insn_lb.py similarity index 88% rename from insns/InsnLb.py rename to insns/insn_lb.py index 663065f..d0ae726 100644 --- a/insns/InsnLb.py +++ b/insns/insn_lb.py @@ -1,4 +1,4 @@ -from InsnRV32IITypeLoad import * +from insn_rv32i_i_type_load import * """ LB instruction diff --git a/insns/InsnLbu.py b/insns/insn_lbu.py similarity index 89% rename from insns/InsnLbu.py rename to insns/insn_lbu.py index 9db69e8..c0f4520 100644 --- a/insns/InsnLbu.py +++ b/insns/insn_lbu.py @@ -1,4 +1,4 @@ -from InsnRV32IITypeLoad import * +from insn_rv32i_i_type_load import * """ LBU instruction diff --git a/insns/InsnLh.py b/insns/insn_lh.py similarity index 88% rename from insns/InsnLh.py rename to insns/insn_lh.py index 8698fa5..b9dc25c 100644 --- a/insns/InsnLh.py +++ b/insns/insn_lh.py @@ -1,4 +1,4 @@ -from InsnRV32IITypeLoad import * +from insn_rv32i_i_type_load import * """ LH instruction diff --git a/insns/InsnLhu.py b/insns/insn_lhu.py similarity index 89% rename from insns/InsnLhu.py rename to insns/insn_lhu.py index 2b40198..d6d4738 100644 --- a/insns/InsnLhu.py +++ b/insns/insn_lhu.py @@ -1,4 +1,4 @@ -from InsnRV32IITypeLoad import * +from insn_rv32i_i_type_load import * """ LHU instruction diff --git a/insns/InsnLui.py b/insns/insn_lui.py similarity index 92% rename from insns/InsnLui.py rename to insns/insn_lui.py index c8db2d5..9ba4833 100644 --- a/insns/InsnLui.py +++ b/insns/insn_lui.py @@ -1,4 +1,4 @@ -from InsnRV32IUType import * +from insn_rv32i_u_type import * """ LUI instruction diff --git a/insns/InsnLw.py b/insns/insn_lw.py similarity index 88% rename from insns/InsnLw.py rename to insns/insn_lw.py index 2ab8565..7609a87 100644 --- a/insns/InsnLw.py +++ b/insns/insn_lw.py @@ -1,4 +1,4 @@ -from InsnRV32IITypeLoad import * +from insn_rv32i_i_type_load import * """ LW instruction diff --git a/insns/InsnOr.py b/insns/insn_or.py similarity index 93% rename from insns/InsnOr.py rename to insns/insn_or.py index e1bf586..ae5e7a4 100644 --- a/insns/InsnOr.py +++ b/insns/insn_or.py @@ -1,4 +1,4 @@ -from InsnRV32IRType import * +from insn_rv32i_r_type import * """ OR instruction diff --git a/insns/InsnOri.py b/insns/insn_ori.py similarity index 92% rename from insns/InsnOri.py rename to insns/insn_ori.py index 71fd535..edbc7fe 100644 --- a/insns/InsnOri.py +++ b/insns/insn_ori.py @@ -1,4 +1,4 @@ -from InsnRV32IITypeArith import * +from insn_rv32i_i_type_arith import * """ ORI instruction diff --git a/insns/InsnRV32IIType.py b/insns/insn_rv32i_i_type.py similarity index 92% rename from insns/InsnRV32IIType.py rename to insns/insn_rv32i_i_type.py index 89d3517..05e7142 100644 --- a/insns/InsnRV32IIType.py +++ b/insns/insn_rv32i_i_type.py @@ -1,4 +1,4 @@ -from Insn import * +from insn import * """ RV32I I-Type Instruction diff --git a/insns/InsnRV32IITypeArith.py b/insns/insn_rv32i_i_type_arith.py similarity index 96% rename from insns/InsnRV32IITypeArith.py rename to insns/insn_rv32i_i_type_arith.py index 5cf1116..9862e9d 100644 --- a/insns/InsnRV32IITypeArith.py +++ b/insns/insn_rv32i_i_type_arith.py @@ -1,4 +1,4 @@ -from InsnRV32IIType import * +from insn_rv32i_i_type import * """ RV32I I-Type Instruction (Arithmetic Variation) diff --git a/insns/InsnRV32IITypeLoad.py b/insns/insn_rv32i_i_type_load.py similarity index 98% rename from insns/InsnRV32IITypeLoad.py rename to insns/insn_rv32i_i_type_load.py index d1d790b..bdef487 100644 --- a/insns/InsnRV32IITypeLoad.py +++ b/insns/insn_rv32i_i_type_load.py @@ -1,4 +1,4 @@ -from InsnRV32IIType import * +from insn_rv32i_i_type import * """ RV32I I-Type Instruction (Load Variation) diff --git a/insns/InsnRV32IITypeShift.py b/insns/insn_rv32i_i_type_shift.py similarity index 98% rename from insns/InsnRV32IITypeShift.py rename to insns/insn_rv32i_i_type_shift.py index 1b7f872..5292d9f 100644 --- a/insns/InsnRV32IITypeShift.py +++ b/insns/insn_rv32i_i_type_shift.py @@ -1,4 +1,4 @@ -from Insn import * +from insn import * """ RV32I I-Type Instruction (Shift Variation) diff --git a/insns/InsnRV32IRType.py b/insns/insn_rv32i_r_type.py similarity index 98% rename from insns/InsnRV32IRType.py rename to insns/insn_rv32i_r_type.py index dcd510b..d61ccf9 100644 --- a/insns/InsnRV32IRType.py +++ b/insns/insn_rv32i_r_type.py @@ -1,4 +1,4 @@ -from Insn import * +from insn import * """ RV32I R-Type Instruction diff --git a/insns/InsnRV32ISType.py b/insns/insn_rv32i_s_type.py similarity index 99% rename from insns/InsnRV32ISType.py rename to insns/insn_rv32i_s_type.py index 8b8a44b..1945d1d 100644 --- a/insns/InsnRV32ISType.py +++ b/insns/insn_rv32i_s_type.py @@ -1,4 +1,4 @@ -from Insn import * +from insn import * """ RV32I S-Type Instruction diff --git a/insns/InsnRV32ISBType.py b/insns/insn_rv32i_sb_type.py similarity index 98% rename from insns/InsnRV32ISBType.py rename to insns/insn_rv32i_sb_type.py index f100e71..a557c6e 100644 --- a/insns/InsnRV32ISBType.py +++ b/insns/insn_rv32i_sb_type.py @@ -1,4 +1,4 @@ -from Insn import * +from insn import * """ RV32I SB-Type Instruction diff --git a/insns/InsnRV32IUType.py b/insns/insn_rv32i_u_type.py similarity index 97% rename from insns/InsnRV32IUType.py rename to insns/insn_rv32i_u_type.py index abea3a1..d9bb1a0 100644 --- a/insns/InsnRV32IUType.py +++ b/insns/insn_rv32i_u_type.py @@ -1,4 +1,4 @@ -from Insn import * +from insn import * """ RV32I U-Type Instruction diff --git a/insns/InsnSb.py b/insns/insn_sb.py similarity index 90% rename from insns/InsnSb.py rename to insns/insn_sb.py index 86f3748..8ff936a 100644 --- a/insns/InsnSb.py +++ b/insns/insn_sb.py @@ -1,4 +1,4 @@ -from InsnRV32ISType import * +from insn_rv32i_s_type import * """ SB instruction diff --git a/insns/InsnSh.py b/insns/insn_sh.py similarity index 90% rename from insns/InsnSh.py rename to insns/insn_sh.py index 97d5b0e..626a3eb 100644 --- a/insns/InsnSh.py +++ b/insns/insn_sh.py @@ -1,4 +1,4 @@ -from InsnRV32ISType import * +from insn_rv32i_s_type import * """ SH instruction diff --git a/insns/InsnSll.py b/insns/insn_sll.py similarity index 94% rename from insns/InsnSll.py rename to insns/insn_sll.py index e559e6a..fe2c297 100644 --- a/insns/InsnSll.py +++ b/insns/insn_sll.py @@ -1,4 +1,4 @@ -from InsnRV32IRType import * +from insn_rv32i_r_type import * """ SLL instruction diff --git a/insns/InsnSlli.py b/insns/insn_slli.py similarity index 92% rename from insns/InsnSlli.py rename to insns/insn_slli.py index 72b22f5..f8a3da7 100644 --- a/insns/InsnSlli.py +++ b/insns/insn_slli.py @@ -1,4 +1,4 @@ -from InsnRV32IITypeShift import * +from insn_rv32i_i_type_shift import * """ SLLI instruction diff --git a/insns/InsnSlt.py b/insns/insn_slt.py similarity index 93% rename from insns/InsnSlt.py rename to insns/insn_slt.py index 7aa260d..a07f0ae 100644 --- a/insns/InsnSlt.py +++ b/insns/insn_slt.py @@ -1,4 +1,4 @@ -from InsnRV32IRType import * +from insn_rv32i_r_type import * """ SLT instruction diff --git a/insns/InsnSlti.py b/insns/insn_slti.py similarity index 92% rename from insns/InsnSlti.py rename to insns/insn_slti.py index 2f70f8b..23dc19d 100644 --- a/insns/InsnSlti.py +++ b/insns/insn_slti.py @@ -1,4 +1,4 @@ -from InsnRV32IITypeArith import * +from insn_rv32i_i_type_arith import * """ SLTI instruction diff --git a/insns/InsnSltiu.py b/insns/insn_sltiu.py similarity index 92% rename from insns/InsnSltiu.py rename to insns/insn_sltiu.py index 946c11a..9cb2136 100644 --- a/insns/InsnSltiu.py +++ b/insns/insn_sltiu.py @@ -1,4 +1,4 @@ -from InsnRV32IITypeArith import * +from insn_rv32i_i_type_arith import * """ SLTIU instruction diff --git a/insns/InsnSltu.py b/insns/insn_sltu.py similarity index 93% rename from insns/InsnSltu.py rename to insns/insn_sltu.py index 0361ac6..2669fea 100644 --- a/insns/InsnSltu.py +++ b/insns/insn_sltu.py @@ -1,4 +1,4 @@ -from InsnRV32IRType import * +from insn_rv32i_r_type import * """ SLTU instruction diff --git a/insns/InsnSra.py b/insns/insn_sra.py similarity index 95% rename from insns/InsnSra.py rename to insns/insn_sra.py index afa8c3c..804089a 100644 --- a/insns/InsnSra.py +++ b/insns/insn_sra.py @@ -1,4 +1,4 @@ -from InsnRV32IRType import * +from insn_rv32i_r_type import * """ SRA instruction diff --git a/insns/InsnSrai.py b/insns/insn_srai.py similarity index 93% rename from insns/InsnSrai.py rename to insns/insn_srai.py index f709aee..1c99816 100644 --- a/insns/InsnSrai.py +++ b/insns/insn_srai.py @@ -1,4 +1,4 @@ -from InsnRV32IITypeShift import * +from insn_rv32i_i_type_shift import * """ SRAI instruction diff --git a/insns/InsnSrl.py b/insns/insn_srl.py similarity index 94% rename from insns/InsnSrl.py rename to insns/insn_srl.py index dbe462b..1403af9 100644 --- a/insns/InsnSrl.py +++ b/insns/insn_srl.py @@ -1,4 +1,4 @@ -from InsnRV32IRType import * +from insn_rv32i_r_type import * """ SRL instruction diff --git a/insns/InsnSrli.py b/insns/insn_srli.py similarity index 92% rename from insns/InsnSrli.py rename to insns/insn_srli.py index 1216c99..6eeb7ae 100644 --- a/insns/InsnSrli.py +++ b/insns/insn_srli.py @@ -1,4 +1,4 @@ -from InsnRV32IITypeShift import * +from insn_rv32i_i_type_shift import * """ SRLI instruction diff --git a/insns/InsnSub.py b/insns/insn_sub.py similarity index 93% rename from insns/InsnSub.py rename to insns/insn_sub.py index dc1212e..9a45e1d 100644 --- a/insns/InsnSub.py +++ b/insns/insn_sub.py @@ -1,4 +1,4 @@ -from InsnRV32IRType import * +from insn_rv32i_r_type import * """ SUB instruction diff --git a/insns/InsnSw.py b/insns/insn_sw.py similarity index 90% rename from insns/InsnSw.py rename to insns/insn_sw.py index cd17787..aa566ce 100644 --- a/insns/InsnSw.py +++ b/insns/insn_sw.py @@ -1,4 +1,4 @@ -from InsnRV32ISType import * +from insn_rv32i_s_type import * """ SW instruction diff --git a/insns/InsnXor.py b/insns/insn_xor.py similarity index 93% rename from insns/InsnXor.py rename to insns/insn_xor.py index c7a23d8..7624731 100644 --- a/insns/InsnXor.py +++ b/insns/insn_xor.py @@ -1,4 +1,4 @@ -from InsnRV32IRType import * +from insn_rv32i_r_type import * """ XOR instruction diff --git a/insns/InsnXori.py b/insns/insn_xori.py similarity index 92% rename from insns/InsnXori.py rename to insns/insn_xori.py index 77d74a1..92ed9bf 100644 --- a/insns/InsnXori.py +++ b/insns/insn_xori.py @@ -1,4 +1,4 @@ -from InsnRV32IITypeArith import * +from insn_rv32i_i_type_arith import * """ XORI instruction diff --git a/insns/IsaRV32I.py b/insns/isa_rv32i.py similarity index 93% rename from insns/IsaRV32I.py rename to insns/isa_rv32i.py index c1a7985..5a4dca1 100644 --- a/insns/IsaRV32I.py +++ b/insns/isa_rv32i.py @@ -1,40 +1,40 @@ -from InsnLui import * -from InsnAuipc import * -from InsnJal import * -from InsnJalr import * -from InsnBeq import * -from InsnBne import * -from InsnBlt import * -from InsnBge import * -from InsnBltu import * -from InsnBgeu import * -from InsnLb import * -from InsnLh import * -from InsnLw import * -from InsnLbu import * -from InsnLhu import * -from InsnSb import * -from InsnSh import * -from InsnSw import * -from InsnAddi import * -from InsnSlti import * -from InsnSltiu import * -from InsnXori import * -from InsnOri import * -from InsnAndi import * -from InsnSlli import * -from InsnSrli import * -from InsnSrai import * -from InsnAdd import * -from InsnSub import * -from InsnSll import * -from InsnSlt import * -from InsnSltu import * -from InsnXor import * -from InsnSrl import * -from InsnSra import * -from InsnOr import * -from InsnAnd import * +from insn_lui import * +from insn_auipc import * +from insn_jal import * +from insn_jalr import * +from insn_beq import * +from insn_bne import * +from insn_blt import * +from insn_bge import * +from insn_bltu import * +from insn_bgeu import * +from insn_lb import * +from insn_lh import * +from insn_lw import * +from insn_lbu import * +from insn_lhu import * +from insn_sb import * +from insn_sh import * +from insn_sw import * +from insn_addi import * +from insn_slti import * +from insn_sltiu import * +from insn_xori import * +from insn_ori import * +from insn_andi import * +from insn_slli import * +from insn_srli import * +from insn_srai import * +from insn_add import * +from insn_sub import * +from insn_sll import * +from insn_slt import * +from insn_sltu import * +from insn_xor import * +from insn_srl import * +from insn_sra import * +from insn_or import * +from insn_and import * """ RV32I Base ISA -- 2.44.1