M-Labs
/
riscv-formal-nmigen
6
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Restructure insns directory contents #2

Merged
dsleung merged 109 commits from restructuring into master 2020-08-13 15:20:35 +08:00
Conversation 0 Commits 109 Files Changed 82 +4 -2
1 changed files with 4 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files
Showing only changes of commit 70c417f920 - Show all commits

6
insns/README.md
View File

@ -1,7 +1,9 @@
# RISC-V Supported Instructions
# RISC-V Instructions
## Instructions
Below is a table of RISC-V instructions supported by the original riscv-formal framework at the time of writing, categorized by instruction type.
| Instruction type | Instructions |
| --- | --- |
| R-type | ADD, ADDW, AND, DIV, DIVU, DIVUW, DIVW, MUL, MULH, MULHSU, MULHU, MULW, OR, REM, REMU, REMUW, REMW, SLL, SLLW, SLT, SLTU, SRA, SRAW, SRL, SRLW, SUB, SUBW, XOR |
@ -32,7 +34,7 @@
## Class Synopsis
_Note: This section is under development and will be updated as more classes are implemented._
Below is a list of instructions currently supported by this port of the riscv-formal framework and is expected to grow over time. The instructions are roughly grouped by instruction type but sometimes with further specializations - the hierarchy of the lists reflects the hierarchy of inheritance in the classes used to represent various instructions.
- `Insn`: General RISC-V instruction
- `InsnRV32IRType`: RV32I R-Type Instruction