Commit Graph

193 Commits

Author SHA1 Message Date
Donald Sebastian Leung 583d165ec1 Refactor BLT instruction 2020-07-30 15:42:10 +08:00
Donald Sebastian Leung 31f6847640 Refactor BNE instruction 2020-07-30 14:14:24 +08:00
Donald Sebastian Leung 3d1bb14bae Refactor BEQ instruction 2020-07-30 14:10:48 +08:00
Donald Sebastian Leung 4a695c950d Add SB-type instruction format 2020-07-30 14:03:59 +08:00
Donald Sebastian Leung f4f5e94843 Refactor JALR instruction 2020-07-30 13:56:30 +08:00
Donald Sebastian Leung e6c6f0462e Add I-type instruction format 2020-07-30 13:48:01 +08:00
Donald Sebastian Leung 7846ba95ac Refactor JAL instruction 2020-07-30 13:34:52 +08:00
Donald Sebastian Leung a84b6d50b8 Add UJ-type instruction format 2020-07-30 13:15:17 +08:00
Donald Sebastian Leung 3dc2a174fd Refactor AUIPC instruction 2020-07-30 13:01:13 +08:00
Donald Sebastian Leung 927c12e97c Refactor LUI instruction 2020-07-30 12:55:57 +08:00
Donald Sebastian Leung 34c8b6cf3d Create U-type instruction format 2020-07-30 12:45:32 +08:00
Donald Sebastian Leung c9c47ddc35 Create general instruction class 2020-07-30 12:06:51 +08:00
Donald Sebastian Leung 65576d0e70 Add rvfi_unique_check 2020-07-29 17:05:34 +08:00
Donald Sebastian Leung b6f72ce7c9 Add rvfi_reg_check 2020-07-29 16:47:36 +08:00
Donald Sebastian Leung d24d466e72 Add rvfi_pc_fwd_check 2020-07-29 13:43:50 +08:00
Donald Sebastian Leung e0bc557d49 Add rvfi_pc_bwd_check 2020-07-29 13:35:21 +08:00
Donald Sebastian Leung 226b225324 Add rvfi_liveness_check 2020-07-29 13:18:23 +08:00
Donald Sebastian Leung 0aaf7e8d03 Resolve import issue in rvfi_insn_check.py for now 2020-07-29 12:55:36 +08:00
Donald Sebastian Leung 0c971e96ce Update rvfi_insn_check.py 2020-07-28 17:55:30 +08:00
Donald Sebastian Leung 032e4c254d Create template for RVFI instruction check 2020-07-28 14:25:14 +08:00
Donald Sebastian Leung bae6fb38bd Add rvfi_imem_check 2020-07-28 14:21:51 +08:00
Donald Sebastian Leung 9908c603fe Add rvfi_ill_check 2020-07-28 14:04:13 +08:00
Donald Sebastian Leung 26a0af8517 Add rvfi_hang_check 2020-07-28 13:42:38 +08:00
Donald Sebastian Leung 0ae0e9c356 Add rvfi_dmem_check 2020-07-27 15:31:46 +08:00
Donald Sebastian Leung 4ba5262165 Add rvfi_channel check 2020-07-27 14:37:10 +08:00
Donald Sebastian Leung 8cb5110199 Add check for causality 2020-07-27 14:16:42 +08:00
Donald Sebastian Leung 2421f1f6b6 Add RV32IM ISA 2020-07-24 13:51:04 +08:00
Donald Sebastian Leung 5bce84836c Add REMU instruction for RV32M 2020-07-24 13:32:43 +08:00
Donald Sebastian Leung 4600eaeb74 Add REM instruction for RV32M 2020-07-24 13:30:06 +08:00
Donald Sebastian Leung 7f3f88cb69 Add DIVU instruction for RV32M 2020-07-24 13:27:48 +08:00
Donald Sebastian Leung 2b198303c6 Add DIV instruction for RV32M 2020-07-24 13:25:17 +08:00
Donald Sebastian Leung f13208455d Add MULHU instruction for RV32M 2020-07-24 13:22:41 +08:00
Donald Sebastian Leung 7a61919a88 Add MULHSU instruction for RV32M 2020-07-24 13:20:05 +08:00
Donald Sebastian Leung 9b4f6ac359 Add MULH instruction for RV32M 2020-07-24 13:16:47 +08:00
Donald Sebastian Leung c72205d433 Modify MUL instruction to use alternative operations 2020-07-24 13:13:03 +08:00
Donald Sebastian Leung dec39cb11d Re-add MUL instruction 2020-07-24 12:55:11 +08:00
Donald Sebastian Leung f33d229b2c Fix XOR instruction 2020-07-24 12:49:33 +08:00
Donald Sebastian Leung d54269d3f0 Fix SUB instruction 2020-07-24 12:48:08 +08:00
Donald Sebastian Leung fe2ff5150a Fix SRL instruction 2020-07-24 12:46:24 +08:00
Donald Sebastian Leung 6d35ecdc80 Fix SRA instruction 2020-07-24 12:44:44 +08:00
Donald Sebastian Leung 3c1510ebbc Fix SLT instruction 2020-07-24 12:42:27 +08:00
Donald Sebastian Leung 18e43d9689 Fix SLL instruction 2020-07-24 12:40:28 +08:00
Donald Sebastian Leung d59ebda628 Fix OR instruction 2020-07-24 12:32:59 +08:00
Donald Sebastian Leung 3028246b73 Fix AND instruction 2020-07-24 12:24:43 +08:00
Donald Sebastian Leung eedfc843f7 Fix ADD instruction 2020-07-24 12:21:07 +08:00
Donald Sebastian Leung 73005eb3c3 Revert MUL instruction 2020-07-24 12:17:02 +08:00
Donald Sebastian Leung 14c87fdde2 Add MUL instruction for RV32M 2020-07-24 12:13:40 +08:00
Donald Sebastian Leung 35a53071aa Complete generator for RV32I ISA 2020-07-23 14:33:25 +08:00
Donald Sebastian Leung 2e7cc106aa Add missing return in ports in RV32I ISA 2020-07-23 12:57:32 +08:00
Donald Sebastian Leung badd480a45 Prepare generator script for RV32I ISA 2020-07-23 12:42:59 +08:00