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riscv-formal-nmigen
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Fix BLT instruction

This commit is contained in:
Donald Sebastian Leung 2020-07-30 16:28:52 +08:00
parent 65e4b68517
commit d0de67d09c
1 changed files with 8 additions and 0 deletions
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8
insns/insn_blt.py
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@ -19,4 +19,12 @@ class rvfi_insn_blt(rvfi_insn_SB_type):
m.d.comb += self.spec_pc_wdata.eq(next_pc) m.d.comb += self.spec_pc_wdata.eq(next_pc)
m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok)
# default assignments
m.d.comb += self.spec_rd_addr.eq(0)
m.d.comb += self.spec_rd_wdata.eq(0)
m.d.comb += self.spec_mem_addr.eq(0)
m.d.comb += self.spec_mem_rmask.eq(0)
m.d.comb += self.spec_mem_wmask.eq(0)
m.d.comb += self.spec_mem_wdata.eq(0)
return m return m