From d0de67d09cf1c10f783cda2173f8dba46f4d8c26 Mon Sep 17 00:00:00 2001
From: Donald Sebastian Leung <dl@m-labs.hk>
Date: Thu, 30 Jul 2020 16:28:52 +0800
Subject: [PATCH] Fix BLT instruction

---
 insns/insn_blt.py | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/insns/insn_blt.py b/insns/insn_blt.py
index faf9db2..35d8121 100644
--- a/insns/insn_blt.py
+++ b/insns/insn_blt.py
@@ -19,4 +19,12 @@ class rvfi_insn_blt(rvfi_insn_SB_type):
         m.d.comb += self.spec_pc_wdata.eq(next_pc)
         m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok)
 
+        # default assignments
+        m.d.comb += self.spec_rd_addr.eq(0)
+        m.d.comb += self.spec_rd_wdata.eq(0)
+        m.d.comb += self.spec_mem_addr.eq(0)
+        m.d.comb += self.spec_mem_rmask.eq(0)
+        m.d.comb += self.spec_mem_wmask.eq(0)
+        m.d.comb += self.spec_mem_wdata.eq(0)
+
         return m