M-Labs
/
riscv-formal-nmigen
6
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Fix minor bug in JAL instruction specification

This commit is contained in:
Donald Sebastian Leung 2020-09-15 16:12:34 +08:00
parent 0f4a2a76bd
commit c4daa89a88
2 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
README.md
View File

@ -32,7 +32,7 @@ This should run in the order of a few hours.
### Progress ### Progress
- [ ] Instruction Checks (mostly passing) - [ ] Instruction Checks (mostly passing)
- [ ] JAL failing at line 202 - [x] JAL failing at line 202
- [ ] LB, LH, LW, LBU, LHU, SB, SH, SW: Parser error - invalid slice - [ ] LB, LH, LW, LBU, LHU, SB, SH, SW: Parser error - invalid slice
- [ ] SRL failing at line 201 - [ ] SRL failing at line 201
- [x] PC forward checks - [x] PC forward checks

2
rvfi/insns/insn_jal.py
View File

@ -22,7 +22,7 @@ class InsnJal(Insn):
m.d.comb += self.ialign16.eq(0) m.d.comb += self.ialign16.eq(0)
next_pc = Signal(self.params.xlen) next_pc = Signal(self.params.xlen)
m.d.comb += next_pc.eq(self.rvfi_rs1_rdata + self.insn_imm) m.d.comb += next_pc.eq(self.rvfi_pc_rdata + self.insn_imm)
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_opcode == 0b1101111)) m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_opcode == 0b1101111))
m.d.comb += self.spec_rd_addr.eq(self.insn_rd) m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_pc_rdata + 4, 0)) m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_pc_rdata + 4, 0))