From c4daa89a88e2b263441376892ddc3a35de3a996c Mon Sep 17 00:00:00 2001
From: Donald Sebastian Leung
Date: Tue, 15 Sep 2020 16:12:34 +0800
Subject: [PATCH] Fix minor bug in JAL instruction specification
---
README.md | 2 +-
rvfi/insns/insn_jal.py | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/README.md b/README.md
index 6e9b731..f573bc7 100644
--- a/README.md
+++ b/README.md
@@ -32,7 +32,7 @@ This should run in the order of a few hours.
### Progress
- [ ] Instruction Checks (mostly passing)
- - [ ] JAL failing at line 202
+ - [x] JAL failing at line 202
- [ ] LB, LH, LW, LBU, LHU, SB, SH, SW: Parser error - invalid slice
- [ ] SRL failing at line 201
- [x] PC forward checks
diff --git a/rvfi/insns/insn_jal.py b/rvfi/insns/insn_jal.py
index ac4201d..4c7420e 100644
--- a/rvfi/insns/insn_jal.py
+++ b/rvfi/insns/insn_jal.py
@@ -22,7 +22,7 @@ class InsnJal(Insn):
m.d.comb += self.ialign16.eq(0)
next_pc = Signal(self.params.xlen)
- m.d.comb += next_pc.eq(self.rvfi_rs1_rdata + self.insn_imm)
+ m.d.comb += next_pc.eq(self.rvfi_pc_rdata + self.insn_imm)
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_opcode == 0b1101111))
m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_pc_rdata + 4, 0))