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riscv-formal-nmigen
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Use m-labs nmigen repo

This commit is contained in:
Donald Sebastian Leung 2020-09-21 11:30:48 +08:00
parent 425bc49784
commit c1a4617d74
2 changed files with 3 additions and 2 deletions
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1
README.md
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@ -35,6 +35,7 @@ The RV32I, RV32M, RV64I and RV64M ISAs are currently implemented but only RV32IM
In no particular order: In no particular order:
- Allow configurable limit for no. of running processes in order to prevent thrashing
- Combine individual instruction checks into single ISA check (currently, doing so takes forever even when depth is set to only `20`) - Combine individual instruction checks into single ISA check (currently, doing so takes forever even when depth is set to only `20`)
## License ## License

4
shell.nix
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@ -2,9 +2,9 @@ let
pkgs = import <nixpkgs> { }; pkgs = import <nixpkgs> { };
nmigen-latest = pkgs.python3Packages.nmigen.overrideAttrs(oa: { nmigen-latest = pkgs.python3Packages.nmigen.overrideAttrs(oa: {
src = pkgs.fetchFromGitHub { src = pkgs.fetchFromGitHub {
owner = "DonaldKellett"; owner = "m-labs";
repo = "nmigen"; repo = "nmigen";
rev = "03726c7e3f307f27626bcc7dffe75abe17b2a390"; rev = "39602ae3fdd143f3aa130278fb185cf3ff98d6da";
sha256 = "1b0rjbb6is6nzbcnxrwh5iv4k9xcac0ijq5kp47wdg9rhbnaa5w0"; sha256 = "1b0rjbb6is6nzbcnxrwh5iv4k9xcac0ijq5kp47wdg9rhbnaa5w0";
}; };
}); });