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riscv-formal-nmigen
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Fix parser error: invalid slice for memory-related instruction checks

This commit is contained in:
Donald Sebastian Leung 2020-09-16 12:30:14 +08:00
parent ee19bc49e7
commit a6b072efcf
3 changed files with 4 additions and 7 deletions
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5
README.md
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@ -31,10 +31,7 @@ This should run in the order of a few hours.
### Progress ### Progress
- [ ] Instruction Checks (mostly passing) - [x] Instruction Checks
- [x] JAL failing at line 202
- [ ] LB, LH, LW, LBU, LHU, SB, SH, SW: Parser error - invalid slice
- [x] SRL failing at line 201
- [x] PC forward checks - [x] PC forward checks
- [x] PC backward checks - [x] PC backward checks
- [x] Register checks - [x] Register checks

2
rvfi/insns/insn_rv32i_i_type_load.py
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@ -29,7 +29,7 @@ class InsnRV32IITypeLoad(InsnRV32IIType):
m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
m.d.comb += self.spec_rd_addr.eq(self.insn_rd) m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
m.d.comb += self.spec_mem_addr.eq(self.addr & ~(int(self.params.xlen // 8) - 1)) m.d.comb += self.spec_mem_addr.eq(self.addr & ~(int(self.params.xlen // 8) - 1))
m.d.comb += self.spec_mem_rmask.eq(((1 << self.mask_shift) - 1) << (self.addr - self.spec_mem_addr)) m.d.comb += self.spec_mem_rmask.eq(((1 << self.mask_shift) - 1) << (self.addr - self.spec_mem_addr)[:5])
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, Value.as_signed(self.result) if self.is_signed else self.result, 0)) m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, Value.as_signed(self.result) if self.is_signed else self.result, 0))
m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
m.d.comb += self.spec_trap.eq(((self.addr & (self.mask_shift - 1)) != 0) | ~self.misa_ok) m.d.comb += self.spec_trap.eq(((self.addr & (self.mask_shift - 1)) != 0) | ~self.misa_ok)

4
rvfi/insns/insn_rv32i_s_type.py
View File

@ -28,8 +28,8 @@ class InsnRV32ISType(Insn):
m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2)
m.d.comb += self.spec_mem_addr.eq(self.addr & ~(int(self.params.xlen // 8) - 1)) m.d.comb += self.spec_mem_addr.eq(self.addr & ~(int(self.params.xlen // 8) - 1))
m.d.comb += self.spec_mem_wmask.eq(((1 << self.mask_shift) - 1) << (self.addr - self.spec_mem_addr)) m.d.comb += self.spec_mem_wmask.eq(((1 << self.mask_shift) - 1) << (self.addr - self.spec_mem_addr)[:5])
m.d.comb += self.spec_mem_wdata.eq(self.rvfi_rs2_rdata << (8 * (self.addr - self.spec_mem_addr))) m.d.comb += self.spec_mem_wdata.eq(self.rvfi_rs2_rdata << (8 * (self.addr - self.spec_mem_addr))[:8])
m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
m.d.comb += self.spec_trap.eq(((self.addr & (self.mask_shift - 1)) != 0) | ~self.misa_ok) m.d.comb += self.spec_trap.eq(((self.addr & (self.mask_shift - 1)) != 0) | ~self.misa_ok)
else: else: