diff --git a/README.md b/README.md
index 24fa2f8..adbed46 100644
--- a/README.md
+++ b/README.md
@@ -31,10 +31,7 @@ This should run in the order of a few hours.
 
 ### Progress
 
-- [ ] Instruction Checks (mostly passing)
-  - [x] JAL failing at line 202
-  - [ ] LB, LH, LW, LBU, LHU, SB, SH, SW: Parser error - invalid slice
-  - [x] SRL failing at line 201
+- [x] Instruction Checks
 - [x] PC forward checks
 - [x] PC backward checks
 - [x] Register checks
diff --git a/rvfi/insns/insn_rv32i_i_type_load.py b/rvfi/insns/insn_rv32i_i_type_load.py
index 3ef5e55..c21411c 100644
--- a/rvfi/insns/insn_rv32i_i_type_load.py
+++ b/rvfi/insns/insn_rv32i_i_type_load.py
@@ -29,7 +29,7 @@ class InsnRV32IITypeLoad(InsnRV32IIType):
             m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
             m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
             m.d.comb += self.spec_mem_addr.eq(self.addr & ~(int(self.params.xlen // 8) - 1))
-            m.d.comb += self.spec_mem_rmask.eq(((1 << self.mask_shift) - 1) << (self.addr - self.spec_mem_addr))
+            m.d.comb += self.spec_mem_rmask.eq(((1 << self.mask_shift) - 1) << (self.addr - self.spec_mem_addr)[:5])
             m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, Value.as_signed(self.result) if self.is_signed else self.result, 0))
             m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
             m.d.comb += self.spec_trap.eq(((self.addr & (self.mask_shift - 1)) != 0) | ~self.misa_ok)
diff --git a/rvfi/insns/insn_rv32i_s_type.py b/rvfi/insns/insn_rv32i_s_type.py
index 6e4cf9d..d3060e8 100644
--- a/rvfi/insns/insn_rv32i_s_type.py
+++ b/rvfi/insns/insn_rv32i_s_type.py
@@ -28,8 +28,8 @@ class InsnRV32ISType(Insn):
             m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
             m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2)
             m.d.comb += self.spec_mem_addr.eq(self.addr & ~(int(self.params.xlen // 8) - 1))
-            m.d.comb += self.spec_mem_wmask.eq(((1 << self.mask_shift) - 1) << (self.addr - self.spec_mem_addr))
-            m.d.comb += self.spec_mem_wdata.eq(self.rvfi_rs2_rdata << (8 * (self.addr - self.spec_mem_addr)))
+            m.d.comb += self.spec_mem_wmask.eq(((1 << self.mask_shift) - 1) << (self.addr - self.spec_mem_addr)[:5])
+            m.d.comb += self.spec_mem_wdata.eq(self.rvfi_rs2_rdata << (8 * (self.addr - self.spec_mem_addr))[:8])
             m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
             m.d.comb += self.spec_trap.eq(((self.addr & (self.mask_shift - 1)) != 0) | ~self.misa_ok)
         else: