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riscv-formal-nmigen
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Add SRLIW instruction

This commit is contained in:
Donald Sebastian Leung 2020-08-27 13:42:38 +08:00
parent d837f6f8f6
commit 94c19ed7f7
2 changed files with 21 additions and 0 deletions
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4
rvfi/insns/insn_slliw.py
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@ -1,5 +1,9 @@
from .insn_rv64i_i_type_shift import * from .insn_rv64i_i_type_shift import *
"""
SLLIW instruction
"""
class InsnSlliw(InsnRV64IITypeShift): class InsnSlliw(InsnRV64IITypeShift):
def __init__(self, params): def __init__(self, params):
super().__init__(params, 0b000000, 0b001) super().__init__(params, 0b000000, 0b001)

17
rvfi/insns/insn_srliw.py Normal file
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@ -0,0 +1,17 @@
from .insn_rv64i_i_type_shift import *
"""
SRLIW instruction
"""
class InsnSrliw(InsnRV64IITypeShift):
def __init__(self, params):
super().__init__(params, 0b000000, 0b101)
def elaborate(self, platform):
m = super().elaborate(platform)
result = Signal(32)
m.d.comb += result.eq(self.rvfi_rs1_rdata[:32] >> self.insn_shamt)
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, (Mux(result[31], 2 ** (self.params.xlen - 32) - 1, 0) << 32) | result, 0))
return m