diff --git a/rvfi/insns/insn_slliw.py b/rvfi/insns/insn_slliw.py
index 982c693..42a4b62 100644
--- a/rvfi/insns/insn_slliw.py
+++ b/rvfi/insns/insn_slliw.py
@@ -1,5 +1,9 @@
 from .insn_rv64i_i_type_shift import *
 
+"""
+SLLIW instruction
+"""
+
 class InsnSlliw(InsnRV64IITypeShift):
     def __init__(self, params):
         super().__init__(params, 0b000000, 0b001)
diff --git a/rvfi/insns/insn_srliw.py b/rvfi/insns/insn_srliw.py
new file mode 100644
index 0000000..05f41b6
--- /dev/null
+++ b/rvfi/insns/insn_srliw.py
@@ -0,0 +1,17 @@
+from .insn_rv64i_i_type_shift import *
+
+"""
+SRLIW instruction
+"""
+
+class InsnSrliw(InsnRV64IITypeShift):
+    def __init__(self, params):
+        super().__init__(params, 0b000000, 0b101)
+    def elaborate(self, platform):
+        m = super().elaborate(platform)
+
+        result = Signal(32)
+        m.d.comb += result.eq(self.rvfi_rs1_rdata[:32] >> self.insn_shamt)
+        m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, (Mux(result[31], 2 ** (self.params.xlen - 32) - 1, 0) << 32) | result, 0))
+
+        return m