M-Labs/riscv-formal-nmigen
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Add SLTIU instruction

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This commit is contained in:
Donald Sebastian Leung 2020-08-10 17:29:55 +08:00
parent 84f4b75267
commit 71f8a594a6
1 changed files with 15 additions and 0 deletions
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insns/InsnSltiu.py Normal file
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from InsnRV32IITypeArith import *
"""
SLTIU instruction
"""
class InsnSltiu(InsnRV32IITypeArith):
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED):
super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b011)
def elaborate(self, platform):
m = super().elaborate(platform)
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_rs1_rdata < self.insn_imm, 0))
return m