diff --git a/insns/InsnSltiu.py b/insns/InsnSltiu.py
new file mode 100644
index 0000000..2bf4d3a
--- /dev/null
+++ b/insns/InsnSltiu.py
@@ -0,0 +1,15 @@
+from InsnRV32IITypeArith import *
+
+"""
+SLTIU instruction
+"""
+
+class InsnSltiu(InsnRV32IITypeArith):
+    def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED):
+        super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b011)
+    def elaborate(self, platform):
+        m = super().elaborate(platform)
+
+        m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_rs1_rdata < self.insn_imm, 0))
+
+        return m