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riscv-formal-nmigen
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Fix AUIPC instruction

This commit is contained in:
Donald Sebastian Leung 2020-07-30 16:12:10 +08:00
parent 4d62caadc7
commit 6cff1038be
1 changed files with 10 additions and 1 deletions
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11
insns/insn_auipc.py
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@ -8,10 +8,19 @@ class rvfi_insn_auipc(rvfi_insn_U_type):
def elaborate(self, platform): def elaborate(self, platform):
m = super(rvfi_insn_auipc, self).elaborate(platform) m = super(rvfi_insn_auipc, self).elaborate(platform)
# LUI instruction # AUIPC instruction
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_opcode == 0b0010111)) m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_opcode == 0b0010111))
m.d.comb += self.spec_rd_addr.eq(self.insn_rd) m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_pc_rdata + self.insn_imm, 0)) m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_pc_rdata + self.insn_imm, 0))
m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
# default assignments
m.d.comb += self.spec_rs1_addr.eq(0)
m.d.comb += self.spec_rs2_addr.eq(0)
m.d.comb += self.spec_trap.eq(~self.misa_ok)
m.d.comb += self.spec_mem_addr.eq(0)
m.d.comb += self.spec_mem_rmask.eq(0)
m.d.comb += self.spec_mem_wmask.eq(0)
m.d.comb += self.spec_mem_wdata.eq(0)
return m return m