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riscv-formal-nmigen
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Fix BEQ instruction

This commit is contained in:
Donald Sebastian Leung 2020-07-30 16:24:04 +08:00
parent 9ddc5563f7
commit 4146a2ed20
2 changed files with 8 additions and 8 deletions
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8
insns/insn_SB_type.py
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@ -27,12 +27,4 @@ class rvfi_insn_SB_type(rvfi_insn_general):
m.d.comb += self.misa_ok.eq(1) m.d.comb += self.misa_ok.eq(1)
m.d.comb += self.ialign16.eq(0) m.d.comb += self.ialign16.eq(0)
# default assignments
m.d.comb += self.spec_rd_addr.eq(0)
m.d.comb += self.spec_rd_wdata.eq(0)
m.d.comb += self.spec_mem_addr.eq(0)
m.d.comb += self.spec_mem_rmask.eq(0)
m.d.comb += self.spec_mem_wmask.eq(0)
m.d.comb += self.spec_mem_wdata.eq(0)
return m return m

8
insns/insn_beq.py
View File

@ -19,4 +19,12 @@ class rvfi_insn_beq(rvfi_insn_SB_type):
m.d.comb += self.spec_pc_wdata.eq(next_pc) m.d.comb += self.spec_pc_wdata.eq(next_pc)
m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok)
# default assignments
m.d.comb += self.spec_rd_addr.eq(0)
m.d.comb += self.spec_rd_wdata.eq(0)
m.d.comb += self.spec_mem_addr.eq(0)
m.d.comb += self.spec_mem_rmask.eq(0)
m.d.comb += self.spec_mem_wmask.eq(0)
m.d.comb += self.spec_mem_wdata.eq(0)
return m return m